KT3170 LOW POWER DTMF RECEIVER
INTRODUCTION
The KT3170 is a complete Dual Tone Multiple Frequency
(DTMF) receiver that is fabricated by low power CMOS
and the Switched-Capacitor Filter technology.
This LSI consists of band split filters, which seperates
counting section which verifies the frequency and
duration of the received tones before passing the cor-
responding code to the output bus. It decodes all 16
DTMF tone pairs into a 4bits digital code.
The externally required components are minimized by
on chip provision of a differential input AMP, clock
oscillator and latched three state interface. The on chip
clock generator requires only a low cost TV cystal as
an external component.
FEATURES
Detects all 16 standard tones.
Low power consumption : 15mW (Typ)
Single power supply : 5V
Uses inexpensive 3.58MHz crystal
Three state outputs for microprocessor interface
Good quality and performance for using in
exchange system
Power down mode/input inhibit
APPLICATIONS
PIN CONFIGURATION
PABX
Central Office
Paging Systems
Remote Control
Credit Card Systems
Key Phone System
Answering Phone
Home Automation System
Mobile Radio
Remote Data Entry
Fig. 1
Device
Package
Operating
KT3170N
18-DIP-300A
- 25
C ~ + 75
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
KT3170
IN+
IN-
GS
V
REF
I
IN
PDN
OSC1
OSC2
GND
V
DD
SI/GTO
ESO
DSO
Q4
Q3
Q2
Q1
OE
18-DIP-300A
ORDERING INFORMATION
KT3170 LOW POWER DTMF RECEIVER
PIN DESCRIPTION
Pin No
Symbol
Description
1
IN +
Non inverting input of the op amp.
2
IN -
Inverting input of the op amp.
3
GS
Gain Select. The output used for gain adjustment of analog input
signal with a feedback resistor.
4
V
REF
Reference Voltage output (V
DD
/2, Typ) can be used to bias the op amp
input of V
DD
/2.
5
I
IN
Input inhibit. High input states inhibits the detection of tones. This
pin is pulled down internally.
6
PDN
Control input for the stand-by power down mode. Power down occurs
when the signal on this input is in high states. This pin is pulled down
internally.
7, 8
OSC1
OSC2
Clock input/output. A inexpensive 3.579545MHz crystal connected
between these pins completes internal oscillator. Also, external clock
can be used.
9
GND
Ground pin.
10
OE
Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is
High and open circuited (High impedance) when disabled by pulling OE
low. Internal pull up resistor built in.
11 - 14
Q1 - Q4
Three state data output. When enabled by OE, these digital outputs
provide the hexadecimal code corresponding to the last valid tone
pair received.
15
DSO
Delayed Steering Output. Indicates that valid frequencies have been
present for the required guard time, thus constituting a valid signal.
Presents a logic high when a received tone pair has been registered
and the output latch is updated. Returns to logic low when the
voltage on SI/GTO falls below V
TH
.
16
ESO
Early Steering Outputs. Indicates detection of valid tone output a
logic high immediately when the digital algorithm detects a
recognizable tone pair. Any momentary loss of signal condition will
cause ESO to return to low.
17
SI/GTO
Steering Input/Guard Time Output. A voltage greater the V
TS
detected at SI causes the device to register the detected tone pair
and update the output latch. A voltage less than V
TS
frees the device
to accept a new tone pair. The GTO output acts to reset the external
steering time constant, and its state is a function of ESO and the
voltage on SI
18
V
DD
Power Supply (+5V, Typ)
KT3170 LOW POWER DTMF RECEIVER
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V, Ta = 25
C, unless otherwise noted)
Characteristics
Symbol
Value
Unit
Power Supper Voltage
Analog Input Voltage Range
Digital Input Voltage Range
Output Voltage Range
Current On Any Pin
Operating Temperature
Storage Temperature
V
DD
V
I (A)
V
I (D)
V
O
I
I
T
OPR
T
STG
6
- 0.3 ~ V
DD
+ 0.3
- 0.3 ~ V
DD
+ 0.3
- 0.3 ~ V
DD
+ 0.3
10
- 40 ~ + 85
-60 ~ + 150
V
V
V
V
mA
C
C
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Operating Voltage
V
DD
-
4.75
-
5.25
V
Operating Current
I
DD
-
-
3.0
9.0
mA
Power Dissipation
P
D
-
-
15
45
mW
Input Voltage Low
V
IL
-
-
-
1.5
V
Input Voltage High
V
IH
-
3.5
-
-
V
Input Leakage Current
I
I (LKG)
V
IN
= GND or V
DD
-
0.1
-
A
Pull Up Current On OE Pin
I
PU
OE = GND
-
7.5
15
A
Analog Input Impedance
R
I
f
IN
= 1KHz
8
10
-
M
Steering Input Threshold Voltage
V
TH
-
2.2
-
2.5
V
Output Voltage Low
V
OL
No Load
-
-
0.03
V
-
V
OH
No Load
4.97
-
V
Output Current
I
O (SINK)
V
OL
= 0.4V
1
2.5
-
mA
Output Current
I
O (SOURCE)
V
OH
= 4.6V
0.4
0.8
-
mA
V
REF
Output Voltage
V
O (REF)
-
2.4
-
2.8
V
V
REF
Output Resistance
R
O (REF)
-
-
10
-
K
Analog Input Offset Voltage
V
IO
-
-
25
-
mV
Power Supply Rejection Ratio
PSRR
Gain Setting Amp
at 1KHz
-
60
-
dB
Common Mode Rejection Ratio
CMRR
- 3.0V < V
IN
< 3.0V
-
60
-
dB
Open Loop Voltage Gain
G
V
Gain Setting Amp at 1KHz
-
65
-
dB
Open Loop Unit Gain Bandwidth
BW
-
-
1.5
-
MHz
Analog Output Voltage Swing
V
O (P-P)
R
L
= 100K
-
4.5
-
V
P-P
Acceptable Capacitive Load
C
L
GS
-
100
-
pF
Acceptable Resistive Load
R
L
GS
-
50
-
K
Analog Input Common Mode
Voltage Range
V
CM
No Load
-
3.0
-
V
P-P
KT3170 LOW POWER DTMF RECEIVER
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 5V, Ta = 25
C, f
CK
= 3.579545MHz)
Notes : 1. Digit sequence consists of all 16 DTMF tones.
2. Tone duration = 40mS, Tone pause = 40mS.
3. Nominal DTMF frequencies are used.
4. Both tones in the composite signal have an equal amplitude.
5. Tone pair is deviated by
1.5%
2Hz.
6. Bandwidth limited (3KHz) Gaussian Noise.
7. The precise dial tone frequencies are (350Hz and 440Hz)
2%.
8. For an error rate of better than 1 in 10000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specitied maximum frequency deviation.
11. This item also applies to a third
tone injected onto the power supply.
12. Referenced to Fig. 1 Input DTMF tone level at -28dBm.
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Valid Input Signal Range
(each tone of composite signal)
-
-
Dual Tone Twist Accept
TW
-
-
10
-
dB
Acceptable Frequency Deviation
f
-
-
-
1.5%
2Hz
-
Frequency Deviation Reject
f
R
-
3.5%
-
-
-
Third Tone Tolerance
T3rd
-
-25
-16
-
dB
Noise Tolerance
T
N
-
-
-12
-
dB
Dial Tolerance
DT
-
18
22
-
dB
Crystal Clock Frequency
f
CK
-
3.5759 3.5795 3.5831
MHz
Maximum Clock Input Rise Time
t
R (MAX)
External Clock
-
-
110
nS
Maximum Clock Input Fall Time
t
F (MAX)
External Clock
-
-
110
nS
Acceptable Clock Input Duty Cycle
D
CK
External Clock
40
50
60
%
Acceptable Capacitive Load
C
L
OSC2 PIN
-
-
30
pF
Tone Present Detect Time
t
DET (P)
-
5
11
14
mS
Tone Absent Detect Time
t
DET (A)
-
0.5
4
8.5
mS
Minimum Tone Duration Accept
t
TDA (MIN)
User Adjustable
-
-
40
mS
Maximum Tone Duration Reject
t
TDR (MAX)
User Adjustable
20
-
-
mS
Acceptable Interdigit Pause
t
IDP (A)
User Adjustable
-
-
40
mS
Rejectable Interdigit Pause
t
IDP (R)
User Adjustable
20
-
-
mS
Propagation Delay Time SI to Q
t
D (SI-Q)
OE = High
-
8
11
S
Propagation Delay Time SI to DSO
t
D (SI-D)
OE = High
-
12
16
S
Output Data Setup Q to DSO
t
SU
OE = High
-
3.4
-
S
Propagation Delay Time OE to Q
(Enable)
t
D (QE-Q) EN
-
Propagation Delay Time OE to Q
(disable)
t
D (OE-Q) DIS
-
-
V
I (VAL)
R
L
= 10K, C
L
= 50pF
R
L
= 10K, C
L
= 50pF
-29
1.0
dBm
50
300
60
nS
nS
KT3170 LOW POWER DTMF RECEIVER
TEST CIRCUIT
HL74LS47
3
b
c
LT
RDO
ABI
d
GND
V
CC
f
g
a
c
d
HL74HCTLS02
8
14
12
11
9
1
4
7
1
10
2
6
13
4
5
8
7
2
3
5
6
R3
C1
300K
LED
KT3170
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
100K
R2
R1
100K
X - tal 2
0.1
F
3
2
1
4
5
6
7
8
9
0
*
#
9
8
7
6
5
4
3
2
10
11
12
13
14
15
16
17
18
1
X - tal 1
V
CC
V
CC
V
CC
V
CC
a
1
LTS542R
com
d
4
5
c dp
2
3
V
CC
10
9
8
7
6
g
com
f
a
b
16
15
14
13
12
11
10
9
R10
R9
R8
R7
R6
R5
R4
V
CC
KS58006
Fig. 2
PDF 
ZIP