- -1 -
Rev. 1.0 Feb. 2003
M312L5628MT0
184pin 1U Registered DDR SDRAM MODULE
2GB DDR SDRAM MODULE
Registered 184pin DIMM
(256Mx72 ((128Mx72)*2)based on stacked 256Mx4 DDR SDRAM)
72-bit ECC/Parity
Revision 1.0
Feb. 2003
- 0 -
Rev. 1.0 Feb. 2003
M312L5628MT0
184pin 1U Registered DDR SDRAM MODULE
Revision History
Revision 0.0 (Oct. 2001)
1.First release for internal usage.
Revision 0.1 (Dec. 2001)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.
- Revised AC parameter table
- Deleted typical current in IDD spec. table
- Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
- Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
- Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
- Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
- Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
- Rename tREF(Refresh interval time) to tREFI at DDR200/266
- Changed tWR value from 2tCK to 15ns.
--Rename tCDLR(Write data out to Read command) t0 tWTR
- Added tDAL(tWR+tRP)
Revision 0.2 (Jan. 2002)
- Added tRAP(Active to Read with auto Precharge connand)
Revision 1.0 (Feb. 2003)
1.Corrected typo
From
To
DDR266A
DDR266B
DDR200
DDR266A
DDR266B
DDR200
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tHZ
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
tLZ
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
tWPST
(tCK)
0.25
0.25
0.25
0.4
0.6
0.4
0.6
0.4
0.6
tPDEX
10ns
10ns
10ns
7.5ns
7.5ns
10ns
- 1 -
Rev. 1.0 Feb. 2003
M312L5628MT0
184pin 1U Registered DDR SDRAM MODULE
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Front Pin Front Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
/RESET
VSS
DQ8
DQ9
DQS1
VDDQ
*CK1
*/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
*/CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DQS11
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DQS17
A10
CB6
VDDQ
CB7
VSS
DQ36
DQ37
VDD
DQS13
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DQS14
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
VDD
DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
The Samsung M312L5628MT0 is 256M bit x 72 Double Data
Rate SDRAM high density memory modules. The Samsung
M312L5628MT0 consists of thirty-six CMOS 128M x 4 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages, mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M312L5628MT0
is Dual In-line Memory Modules and intend-ed for mounting
into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
GENERAL DESCRIPTION
PIN DESCRIPTION
* These pins are not used in this module.
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Bank Select Address
DQ0 ~ DQ63
Data input/output
CB0 ~ CB7
Check bit(Data-in/data-out)
DQS0 ~ DQS17
Data Strobe input/output
CK0,CK0 Clock
input
CKE0,CKE1
Clock enable input
CS0, CS1
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
VDD
Power supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (
2.3V to 3.6V
)
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD identification flag
RESET
Reset enable
NC
No connection
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
KEY
KEY
M312L5628MT0 DDR SDRAM 184pin DIMM 256Mx72 DDR SDRAM
184pin DIMM based on stacked 256Mx4, 4bank, 8K refresh with SPD
Performance range
Power supply : Vdd: 2.5V
0.2V, Vddq: 2.5V
0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1200 mil, double sided component
Part No.
Max Freq.
Interface
M312L5628MT0-C(L)A2 133MHz(7.5ns@CL=2)
SSTL_2
M312L5628MT0-C(L)B0 133MHz(7.5ns@CL=2.5)
M312L5628MT0-C(L)A0 100MHz(10ns@CL=2)
FEATURE
- 2 -
Rev. 1.0 Feb. 2003
M312L5628MT0
184pin 1U Registered DDR SDRAM MODULE
RA0 - RA12
A0-An: SDRAMs D0 - D35
RAS: SDRAMs D0 - D35
RCAS
CAS: SDRAMs D0 - D35
RCKE1
CKE: SDRAMs D18 - D35
PCK
WE: SDRAMs D0 - D35
RCKE0
RBA0 - RBAn
BA0-BAn: SDRAMs D0 - D35
RAS
CAS
CKE0
CKE1
RCS1
CS1
BA0-BAN
A0-A12
R
E
G
I
S
T
E
R
RRAS
RWE
CS0
RCS0
WE
PCK
RESET
CKE: SDRAMs D0 - D17
PLL
CK0,CK0
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
V
SS
D0 - D35
D0 - D35
V
DD
/V
DDQ
D0 - D35
D0 - D35
VREF
V
DDSPD
SPD
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Functional Block Diagram
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQS0
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM0/DQS9
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM2/DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM3/DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM4/DQS13
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM5/DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM7/DQS16
RS0
RS1
DQS4
DQS1
DQS5
DQS2
DQS3
DM6/DQS15
DQS6
DQS7
DQ15
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D0
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D1
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D2
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D3
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D4
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D5
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D6
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D7
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D9
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D10
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D11
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D12
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D13
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D14
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D15
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D16
S
DM
DM1/DQS10
V
SS
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D18
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D19
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D20
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D21
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D22
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D23
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D24
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D25
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D27
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D28
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D29
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D30
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D31
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D32
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D33
S
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
D34
S
DM
CB0
CB1
CB2
CB3
DQS8
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D8
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D26
S
DM
CB4
CB5
CB6
CB7
DM8/DQS17
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D17
S
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
D35
S
DM
- 3 -
Rev. 1.0 Feb. 2003
M312L5628MT0
184pin 1U Registered DDR SDRAM MODULE
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Notes 1. Includes
25mV margin for DC offset on V
REF
, and a combined total of
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
3nH.
2.V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70
C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V
DD
of 2.5V)
V
DD
2.3
2.7
I/O Supply voltage
V
DDQ
2.3
2.7
V
I/O Reference voltage
V
REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
DDQ
+0.3
V
4
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and CK inputs
V
IN
(DC)
-0.3
V
DDQ
+0.3
V
Input Differential Voltage, CK and CK inputs
V
ID
(DC)
0.3
V
DDQ
+0.6
V
3
Input crossing point voltage, CK and CK inputs
V
IX
(DC)
1.15
1.35
V
5
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver)
;V
OUT
=
V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver)
;V
OUT
= V
TT
- 0.45V
I
OL
9
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
& V
DDQ
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
54
W
Short circuit current
I
OS
50
mA
Absolute Maximum Rate
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