DRAM MODULE

M364E040(8)4BT0-C

M364E040(8)4BT0-C EDO Mode
4M x 64 DRAM DIMM Using 4Mx16, 4K & 8K Refresh, 5V

The Samsung M364E040(8)4BT0-C is a 4Mx64bits Dynamic
RAM high density memory module. The Samsung

M364E040(8)4BT0-C consists of four CMOS 4Mx16bits
DRAMs in TSOP-II 400mil packages and two 16 bits driver IC
in TSSOP package mounted on a 168-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The
M364E040(8)4BT0-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.

GENERAL DESCRIPTION

PD Note :PD & ID Terminals must each be pulled up through a resistor to V

at the next higher

level assembly. PDs will be either open (NC) or driven to V

via on-board buffer circuits.

ID Note : IDs will be either open (NC) or connected directly to V

without a buffer.

FEATURES

· Part Identification

· Extended Data Out Mode Operation

· CAS-before-RAS Refresh capability

· RAS-only and Hidden refresh capability

· TTL compatible inputs and outputs

· Single 5V

10% power supply

· JEDEC standard pinout & Buffered PDpin

· Buffered input except RAS and DQ

· PCB : Height(1000mil), single sided component

Part number

PKG

Ref.

CBR Ref.

ROR Ref.

M364E0404BT0-C

TSOPll

4K/64ms

M364E0484BT0-C

TSOPll

4K/64ms

8K/64ms

PIN NAMES

Pins marked

are not used in this module.

Pin Names

Function

A0, B0, A1 - A11

Address Input(4K ref.)

A0, B0, A1 - A12

Address Input(8K ref.)

DQ0 - DQ71

Data In/Out

W0, W2

Read/Write Enable

OE0, OE2

Output Enable

RAS0, RAS2

Row Address Strobe

CAS0 - CAS7

Column Address Strobe

Power(+5V)

Ground

No Connection

PDE

Presence Detect Enable

PD1 - 8

Presence Detect

ID0 - 1

ID bit

RSVD

Reserved Use

RFU

Reserved for Future Use

PD & ID Table

PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C

Pin

50NS

60NS

PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8

1
1
0
1
1
0
0
1

1
1
0
1
1
1
1
1

ID0
ID1

0
0

PIN CONFIGURATIONS

NOTE : A12 is used for only M364E0484BT0-C (8K Ref.)

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Front

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

*DQ8

DQ9

DQ10
DQ11
DQ12
DQ13

DQ14
DQ15
DQ16

*DQ17

RSVD
RSVD

CAS0

Pin

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Front

CAS2
RAS0

OE0

A0
A2
A4
A6
A8

A10
A12
V

RFU
RFU

OE2

RAS2
CAS4
CAS6

RSVD
RSVD

DQ18
DQ19

DQ20
DQ21

Pin

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

Front

DQ22
DQ23

DQ24

RFU
RFU
RFU
RFU

DQ25

*DQ26

DQ27

DQ28
DQ29
DQ30
DQ31

DQ32
DQ33
DQ34

*DQ35

PD1
PD3
PD5
PD7

ID0

Pin

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

Back

DQ36
DQ37
DQ38
DQ39

DQ40
DQ41
DQ42
DQ43

*DQ44

DQ45
DQ46
DQ47
DQ48
DQ49

DQ50
DQ51
DQ52

*DQ53

RSVD
RSVD

RFU

CAS1

Pin

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

Back

CAS3

*RAS1

RFU

A1
A3
A5
A7
A9

A11

*A13

RFU

*RAS3

CAS5
CAS7

PDE

RSVD
RSVD

DQ54
DQ55

DQ56
DQ57

Pin

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

Back

DQ58
DQ59

DQ60

RFU
RFU
RFU
RFU

DQ61

*DQ62

DQ63

DQ64
DQ65
DQ66
DQ67

DQ68
DQ69
DQ70

*DQ71

PD2
PD4
PD6
PD8

ID1

PERFORMANCE RANGE

Speed

RAC

CAC

HPC

-C50

50ns

18ns

84ns

20ns

-C60

60ns

20ns

104ns

25ns

DRAM MODULE

M364E040(8)4BT0-C

FUNCTIONAL BLOCK DIAGRAM

Vcc

Vss

0.1 or 0.22uF Capacitor
under each DRAM

To all DRAMs

A0
B0

A1-A11(A12)

W0, OE0
W2, OE2

U0-U1
U2-U3
U0-U3
U0-U1
U2-U3

RAS0

OE0

CAS1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16

CAS2

CAS3

DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25

DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34

CAS4

CAS5

DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43

DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52

CAS6

CAS7

DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61

DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70

RAS2

OE2

CAS0

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ8
DQ9

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

A1-A11(A12)

Note : A12 is used for only M364E0484BT0 (8K ref.)

UCAS

LCAS

UCAS

LCAS

UCAS

LCAS

UCAS

LCAS

DRAM MODULE

M364E040(8)4BT0-C

* NOTE : I

CC1

, I

CC3

, I

CC4

and I

CC6

are dependent on output loading and cycle rates. Specified values are obtained with the output open.

is specified as an average current. In I

CC1

and I

CC3

, address can be changed maximum once while RAS=V

. In I

CC4

address can be changed maximum once within one EDO mode cycle time,

HPC

ABSOLUTE MAXIMUM RATINGS *

* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.

Item

Symbol

Rating

Unit

Voltage on any pin relative V

Voltage on V

supply relative to V

Storage Temperature
Power Dissipation
Short Circuit Output Current

, V

OUT

stg

-1 to +7.0
-1 to +7.0

-55 to +125

V
V

RECOMMENDED OPERATING CONDITIONS

(Voltage referenced to V

, T

= 0 to 70

*1 : V

+2.0V at pulse width

20ns, which is measured at V

*2 : -2.0V at pulse width

20ns, which is measured at V

Item

Symbol

Min

Typ

Max

Unit

Supply Voltage
Ground
Input High Voltage
Input Low Voltage

4.5

2.4

-1.0

5.0

-
-

5.5

0.8

V
V
V
V

DC AND OPERATING CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)

CC1

CC2

CC3

CC4

CC5

CC6

IL)

OL)

Symbol

Speed

M364E0404BT0

M364E0484BT0

Unit

Min

Max

Min

Max

CC1

-50
-60

-
-

480
440

-
-

360
320

mA
mA

CC2

Don

t care

100

CC3

-50
-60

-
-

480
440

-
-

360
320

mA
mA

CC4

-50
-60

-
-

440
400

-
-

400
360

mA
mA

CC5

Don

t care

CC6

-50
-60

-
-

480
440

-
-

360
320

mA
mA

I(L)

O(L)

Don

t care

-10

-5

-10

-5

uA
uA

Don

t care

2.4

0.4

2.4

0.4

V
V

: Operating Current * (RAS, CAS, Address cycling @

=min)

: Standby Current (RAS=CAS=W=V

)

: RAS Only Refresh Current * (CAS=V

, RAS cycling @

=min)

: Extended Data Out Mode Current * (RAS=V

, CAS cycling :

HPC

=min)

: Standby Current (RAS=CAS=W=Vcc-0.2V)

: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @

=min)

: Input Leakage Current (Any input 0

Vcc+0.5V, all other pins not under test=0 V)

: Output Leakage Current(Data Out is disabled, 0V

OUT

Vcc)

: Output High Voltage Level (I

= -5mA)

: Output Low Voltage Level (I

= 4.2mA)

DRAM MODULE

M364E040(8)4BT0-C

CAPACITANCE

= 25

C, f = 1MHz)

Item

Symbol

Min

Max

Unit

Input capacitance[A0, B0, A1 - A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0 - 71]

IN1

IN2

IN3

IN4

20
20
24
20
17

pF
pF
pF
pF
pF

AC CHARACTERISTICS

C, V

=5.0V

10%. See notes 1,2.)

Test condition : V

=2.6/0.8V, V

=2.0/0.8V, output loading CL=100pF

Parameter

Symbol

-50

-60

Unit

Note

Min

Max

Min

Max

Random read or write cycle time

104

Read-modify-write cycle time

RWC

133

155

Access time from RAS

RAC

Access time from CAS

CAC

3,4,5,13

Access time from column address

3,10,13

CAS to output in Low-Z

CLZ

3,13

OE to output in Low-Z

OLZ

3,13

Output buffer turn-off delay from CAS

CEZ

6,11,13

Transition time(rise and fall)

RAS precharge time

RAS pulse width

RAS

10K

RAS hold time

RSH

CAS hold time

CSH

CAS pulse width

CAS

10K

RAS to CAS delay time

RCD

4,13

RAS to column address delay time

RAD

10,13

CAS to RAS precharge time

CRP

Row address set-up time

ASR

Row address hold time

RAH

Column address set-up time

ASC

Column address hold time

CAH

Column address to RAS lead time

RAL

Read command set-up time

RCS

Read command hold referenced to CAS

RCH

Read command hold referenced to RAS

RRH

-2

8,13

Write command set-up time

WCS

Write command hold time

WCH

Write command pulse width

Write command to RAS lead time

RWL

Write command to CAS lead time

CWL

Data set-up time

-2

9,13

Data hold time

9,13

Refresh period(4K & 8K)

REF

CAS to W delay time

CWD

7,16

RAS to W delay time

RWD

7,13

DRAM MODULE

M364E040(8)4BT0-C

AC CHARACTERISTICS

C, V

=5.0V

10%. See notes 1,2.)

Parameter

Symbol

-50

-60

Unit

Note

Min

Max

Min

Max

Column address to W delay time

AWD

CAS precharge time to W delay time

CPWD

CAS setup time(CAS-before-RAS refresh)

CSR

13,18

CAS hold time(CAS-before-RAS refresh)

CHR

RAS to CAS precharge time

RPC

Access time from CAS precharge

CPA

3,13

Hyper page cycle time

HPC

Hyper page read-modify-write cycle time

HPRWC

CAS precharge time(Hyper page cycle)

RAS pulse width (Hyper page cycle)

RASP

200K

RAS hold time from CAS precharge

RHCP

W to RAS precharge time(C-B-R refresh)

WRP

W to RAS hold time(C-B-R refresh)

WRH

OE access time

OEA

OE to data delay

OED

Output buffer turn off delay time from OE

OEZ

OE command hold time

OEH

Output data hold time(C-B-R refresh)

DOH

Output buffer turn off delay time from RAS

REZ

6,11

Output buffer turn off delay time from W

WEZ

6,13

W to data delay

WED

OE to CAS hold time

OCH

CAS hold time to OE

CHO

OE precharge time

OEP

W pulse width (Hyper page cycle)

WPE

PDE to Valid PD bit

PDE to PD bit Inactive

PDOFF

Present Detect Read Cycle

DRAM MODULE

M364E040(8)4BT0-C

NOTES

An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.

Input voltage levels are V

. V

(min) and V

(max) are ref-

erence levels for measuring timing of input signals. Transition

times are measured between V

(min) and V

(max) and are

assumed to be 5ns for all inputs.

Measured with a load equivalent to 2 TTL loads and 100pF.

Operation within the

RCD

(max) limit insures that

RAC

(max)

can be met.

RCD

(max) is specified as a reference point only.

RCD

is greater than the specified

RCD

(max) limit, then

access time is controlled exclusively by

CAC

Assumes that

RCD

(max).

This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V

WCS

RWD

CWD

AWD

and

CPWD

are not restrictive operat-

ing parameter. They are included in the data sheet as electri-

cal characteristics only. If

WCS

(min) the cycle is an

early write cycle and the data out pin will remain high imped-

ance for the duration of the cycle. If

RWD

(min),

CWD

(min),

AWD

(min) and

CPWD

(min).

The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data

out(at access time) is indeterminate.

Either

RCH

RRH

must be satisfied for a read cycle.

These parameters are referenced to the CAS leading edge in
early write cycles.

Operation within the

RAD

(max) limit insures that

RAC

(max)

can be met.

RAD

(max) is specified as reference point only. If

RAD

is greater than the specified

RAD

(max) limit, then

access time is controlled by

If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.

ASC

6ns.

The timing skew from the DRAM to the DIMM resulted from

the addition of buffers.

ASC

CAH

are referenced to the earlier CAS falling edge.

is specified from the last CAS rising edge in the previous

cycle to the first CAS falling edge in the next cycle.

CWD

is referenced to the later CAS falling edge at word read-

modify-write cycle.

CWL

is specified from W falling edge to the earlier CAS rising

edge.

CSR

is referenced to earlier CAS falling low before RAS tran-

sition low.

10.

12.

13.

11.

14.

15.

16.

17.

18.

DRAM MODULE

M364E040(8)4BT0-C

DOH

HYPER PAGE READ CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

RCD

ASR

CRP

Don

t care

Undefined

OEP

COLUMN

ADDRESS

CAS

HPC

RHCP

CSH

RAD

RAH

ASC

CAH

ASC

CAH

RCS

RCH

ASC

COLUMN

ADDRESS

COLUMN

ADDR

VALID

DATA-OUT

OEZ

OEA

OEP

CAC

OEA

CPA

CAC

CPA

VALID

DATA-OUT

VALID

DATA-OUT

OEZ

CLZ

RAC

OEA

OLZ

CAC

RRH

CHO

REZ

OEZ

CAC

OCH

CPA

CAC

VALID

DATA-OUT

¡ó

ASC

DRAM MODULE

M364E040(8)4BT0-C

HYPER PAGE READ AND WRITE MIXED CYCLE

RAS

CAS

COLUMN

ADDRESS

ROW

ADDR

RASP

Don

t care

Undefined

I/OH

I/OL

WEZ

HPC

RAD

RAH

ASC

CAH

ASC

CAH

RCH

RCS

RCH

ASC

COLUMN

ADDRESS

COL.

ADDR

VALID

DATA-OUT

REZ

WCS

VALID

DATA-OUT

VALID

DATA-OUT

VALID

DATA-IN

RAC

COL.

ADDR

CAS

ASR

CAS

ASC

RCH

WCH

WPE

CLZ

CPA

WED

WEZ

CAC

OEA

READ(

CAC

)

READ(

CPA

)

WRITE

READ(

)

DRAM MODULE

M364E040(8)4BT0-C

CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

RAS

CAS

COLUMN

ADDRESS

RAS

RSH

CHR

RAL

CSR

CPT

CAS

ASC

CAH

READ CYCLE

DATA-OUT

REZ

CLZ

WRITE CYCLE

DATA-IN

CWD

CWL

RWL

READ-MODIFY-WRITE

AWD

OEA

CAC

VALID

DATA-OUT

I/OH

I/OL

Don

t care

Undefined

OEA

OEZ

RCS

CLZ

OEZ

OED

WRP

WRH

RRH

RCH

RCS

CAC

WRP

WRH

WCS

WCH

CWL

RWL

WRP

WRH

VALID

DATA-IN

NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.

CEZ

WEZ

DRAM MODULE

M364E040(8)4BT0-C

Tolerances :

.005(.13) unless otherwise specified

The used device is 4Mx16 DRAM with EDO mode, TSOP II.
DRAM Part No. : M364E0404BT0 - K4E641611B
M364E0484BT0 - K4E661611B

PACKAGE DIMENSIONS

5.250

5.014

Units : Inches (millimeters)

R 0.079

(R 2.000)

0.250

(6.350)

1.450

(36.830)

2.150

(54.61)

0.350

.
1

i
n

(
2

.
5

i
n

)

.
7

(
1

.
7

)

.118DIA

.004

(3.000DIA

.100)

(8.890)

0.250

(6.350)

.450
(11.430)

4.550

(115.57)

0.157

0.004

(4.000

0.100)

0.054

(1.372)

(127.350)

(133.350)

.
0

(
2

.
4

)

0.118

(3.000)

.
1

(
3

.
0

)

0.100Max

(2.54Max)

0.050

0.0039

(1.270

0.10)

.
1

i
n

(
4

.
1

i
n

)

( Back view )

( Front view )

0.050

0.039

.002

0.01Max

(0.25 Max)

(1.000

.050)

(1.270)

.
1

i
n

(
2

.
5

i
n

)

Detail C

0.250

(6.350)

Detail A

0.1230

.0050

(3.125

±.

125)

Detail B

0.079

.0040

(2.000

.100)

0.250

(6.350)

0.1230

.0050

(3.125

±.

125)

0.079

.0040

(2.000

.100)

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