184pin Unbuffered DDR SDRAM MODULE

M368L1713CTL

Rev. 0.3 May. 2002

Revision History

Revision 0.0 (Oct. 2001)

1. First release

Revision 0.1 (Nov. 2001)

1. Added DDR333 function
2. Updated DDR333 test specification
3. Deleted typical current in IDD spec. table
4. Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
5. Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
6. Changed unit of tMRD from tCK to ns at DDR333
7. Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
8. Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
9. Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
10. Rename tREF(Refresh interval time) to tREFI at DDR200/266

11. Rename tCDLR(Last write data to Read command) to tWTR

Revision 0.2 (Jan. 2002)

1. Added tRAP(Active to Read with auto precharge command)

Revision 0.3 (May. 2002)

1. Change pin location of A13 from pin 103 to pin 167

184pin Unbuffered DDR SDRAM MODULE

M368L1713CTL

Rev. 0.3 May. 2002

GENERAL DESCRIPTION

PIN DESCRIPTION

* These pins are not used in this module.

Pin Name

Function

A0 ~ A11

Address input (Multiplexed)

BA0 ~ BA1

Bank Select Address

DQ0 ~ DQ63

Data input/output

DQS0 ~ DQS7

Data Strobe input/output

CK0,CK0 ~ CK2,CK2 Clock input
CKE0

Clock enable input

/CS0

Chip select input

RAS

Row address strobe

CAS

Column address strobe

Write enable

DM0 ~ DM7

Data - in mask

VDD

Power supply (2.5V)

VDDQ

Power Supply for DQS(2.5V)

VSS

Ground

VREF

Power supply for reference

VDDSPD

Serial EEPROM Power
Supply (2.3V to 3.6V)

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

VDDID

VDD identification flag

No connection

PIN CONFIGURATIONS (Front side/back side)

Pin Front Pin Front Pin Front

Pin

Back

Pin

Back

Pin

Back

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

VREF

DQ0
VSS
DQ1

DQS0

DQ2

VDD

DQ3

NC
NC

VSS
DQ8
DQ9

DQS1

VDDQ

CK1

/CK1

VSS

DQ10
DQ11
CKE0

VDDQ

DQ16
DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

53
54
55
56
57
58
59
60
61

DQ24

VSS

DQ25
DQS3

VDD

DQ26
DQ27

VSS

*CB0
*CB1

VDD

*DQS8

*CB2

VSS

*CB3

BA1

DQ32

VDDQ

DQ33
DQS4
DQ34

VSS

BA0

DQ35
DQ40

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42
DQ43

VDD

*/CS2
DQ48
DQ49

VSS

/CK2

CK2

VDDQ
DQS6

DQ50
DQ51

VSS

VDDID

DQ56
DQ57

VDD

DQS7

DQ58
DQ59

VSS

SDA
SCL

93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123

VSS
DQ4
DQ5

VDDQ

DM0
DQ6
DQ7
VSS

NC
NC
NC

VDDQ

DQ12
DQ13

DM1
VDD

DQ14
DQ15

*CKE1

VDDQ

*BA2

DQ20

*A12
VSS

DQ21

A11

DM2
VDD

DQ22

DQ23

124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

145
146
147
148
149
150
151
152
153

VSS

DQ28
DQ29

VDDQ

DM3

DQ30

VSS

DQ31

*CB4
*CB5

VDDQ

CK0

/CK0

VSS

*DM8

A10

*CB6

VDDQ

*CB7

VSS

DQ36
DQ37

VDD
DM4

DQ38
DQ39

VSS

DQ44

154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184

/RAS

DQ45

VDDQ

/CS0

*/CS1

DM5
VSS

DQ46
DQ47
*/CS3

VDDQ

DQ52
DQ53

*A13
VDD
DM6

DQ54
DQ55

VDDQ

DQ60
DQ61

VSS
DM7

DQ62
DQ63

VDDQ

SA0
SA1
SA2

VDDSPD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

KEY

M368L1713CTL DDR SDRAM 184pin DIMM

16Mx64 DDR SDRAM 184pin DIMM based on 16Mx8

The Samsung M368L1713CTL is 16M bit x 64 Double Data
Rate SDRAM high density memory modules.
The Samsung M368L1713CTL consists of eight CMOS 16M x
8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 184pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM. The
M368L1713CTL is Dual In-line Memory Modules and intended
for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.

� Performance range

� Power supply : Vdd: 2.5V

�

0.2V, Vddq: 2.5V

�

0.2V

�

Double-data-rate architecture; two data transfers per clock cycle

� Bidirectional data strobe(DQS)
� Differential clock inputs(CK and CK)
� DLL aligns DQ and DQS transition with CK transition
� Programmable Read latency 2, 2.5 (clock)
� Programmable Burst length (2, 4, 8)
� Programmable Burst type (sequential & interleave)
� Edge aligned data output, center aligned data input
� Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
� Serial presence detect with EEPROM
� PCB :

Height 1250 mil, double sided component

Part No.

Max Freq.

Interface

M368L1713CTL-C(L)B3 166MHz(6ns@CL=2.5)

SSTL_2

M368L1713CTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L1713CTL-C(L)B0 133MHz(7.5ns@CL=2.5)

FEATURE

184pin Unbuffered DDR SDRAM MODULE

M368L1713CTL

Rev. 0.3 May. 2002

Functional Block Diagram

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

D M

I/O 7
I/O 6
I/O 1
I/O 0

D 0

DM0

I/O 5
I/O 4
I/O 3
I/O 2

DQ12
DQ13
DQ14

DQ8
DQ9
DQ10
DQ11

D M

I/O 7
I/O 6
I/O 1
I/O 0

D 1

I/O 5
I/O 4
I/O 3

DM1

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM2

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM3

DQ36
DQ37
DQ38
DQ39

DQ32
DQ33
DQ34
DQ35

I/O 7
I/O 6
I/O 1
I/O 0

DM4

I/O 5
I/O 4
I/O 3
I/O 2

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42
DQ43

I/O 7
I/O 6
I/O 1
I/O 0

D 5

I/O 5
I/O 4
I/O 3
I/O 2

DM5

DQ52
DQ53
DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

D M

I/O 7
I/O 6
I/O 1
I/O 0

D 6

I/O 5
I/O 4
I/O 3
I/O 2

DQ60
DQ61
DQ62
DQ63

DQ56
DQ57
DQ58
DQ59

I/O 7
I/O 6
I/O 1
I/O 0

I/O 5
I/O 4
I/O 3
I/O 2

DM7

A0 - A 13

A0-A13: SDRAMs D0 - D7

RAS

RAS: SDRAMs D0 - D7

CAS

CAS: SDRAMs D0 - D7

CKE0

CKE: SDRAMs D0 - D7

W E

WE : SDRAMs D0 - D7

CS0

C S

BA0 - BA1

BA0-BA1: SDRAMs D0 - D7

DQS0

DQS

DQS4

DQS1

DQS5

DQS

DQS2

DQS

DQS3

DQS

DM6

DQS6

DQS7

DQ15

I/O 2

DQS

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.

*Clock Net Wiring

Card
Edge

Dram1

Cap

Dram3

Cap

Dram5

Cap

R=120

*(Cap)

Cap will replace DRAM3

*If two DRAMs are loaded,

* Clock Wiring

Clock
Input

SDRAMs

CK0/CK0
CK1/CK1
CK2/CK2

2 SDRAMs
3 SDRAMs
3 SDRAMs

Serial PD

SA0

SA1

SA2

S C L

S D A

D0 - D7

DDQ

D0 - D7

VREF

DDSPD

SPD

184pin Unbuffered DDR SDRAM MODULE

M368L1713CTL

Rev. 0.3 May. 2002

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

I N

, V

OUT

-0.5 ~ 3.6

Voltage on V

D D

supply relative to Vss

-1.0 ~ 3.6

Voltage on V

DDQ

supply relative to Vss

DDQ

-1.0 ~ 3.6

Storage temperature

STG

-55 ~ +150

�

Power dissipation

Short circuit current

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)

Notes 1. Includes

�

25mV margin for DC offset on V

REF

, and a combined total of

�

50mV margin for all AC noise and DC offset on V

REF

bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V

REF

and internal DRAM noise coupled

TO V

REF

, both of which may result in V

REF

noise. V

REF

should be de-coupled with an inductance of

3nH.

2.V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to

REF

, and must track variations in the DC level of V

R E F

3. V

is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the dc level of the same.

6. These charactericteristics obey the SSTL-2 class II standards.

Recommended operating conditions(Voltage referenced to V

=0V, T

=0 to 70

�

Parameter

Symbol

Min

Max

Unit

Note

Supply voltage(for device with a nominal V

of 2.5V)

2.3

2.7

I/O Supply voltage

DDQ

2.3

2.7

I/O Reference voltage

R E F

VDDQ/2-50mV

VDDQ/2+50mV

I/O Termination voltage(system)

REF

-0.04

R E F

+0.04

Input logic high voltage

(DC)

R E F

+0.15

DDQ

+0.3

Input logic low voltage

(DC)

-0.3

REF

-0.15

Input Voltage Level, CK and CK inputs

(DC)

-0.3

DDQ

+0.3

Input Differential Voltage, CK and CK inputs

(DC)

0.3

DDQ

+0.6

Input crossing point voltage, CK and CK inputs

(DC)

1.15

1.35

Input leakage current

-2

Output leakage current

O Z

-5

Output High Current(Normal strengh driver)
;V

OUT

= V

+ 0.84V

O H

-16.8

Output High Current(Normal strengh driver)
;V

OUT

= V

- 0.84V

16.8

Output High Current(Half strengh driver)
;V

OUT

+ 0.45V

O H

-9

Output High Current(Half strengh driver)
;V

OUT

= V

- 0.45V

Электронный компонент: M368L1713CTL-CB3