184pin Unbuffered DDR SDRAM MODULE
M368L6423DTM
Rev. 1.0 Dec. 2002
512MB DDR SDRAM MODULE
Unbuffered 184pin DIMM
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
64-bit Non-ECC/Parity
Revision 1.0
Dec. 2002
New PC2700 gerber based
184pin Unbuffered DDR SDRAM MODULE
M368L6423DTM
Rev. 1.0 Dec. 2002
Revision History
Revision 1.0 (Dec. 2002)
1. First release
184pin Unbuffered DDR SDRAM MODULE
M368L6423DTM
Rev. 1.0 Dec. 2002
The Samsung M368L6423DTM is 32M bit x 64 Double Data
Rate SDRAM high density memory module based on fifth gen.
of 256Mb DDR SDRAM respectively. The Samsung
M368L6423DTM consists of sixteen CMOS 32M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M368L6423DTM
Dual In-line Memory Module and is intended for mounting into
184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
GENERAL DESCRIPTION
PIN DESCRIPTION
* These pins are not used in this module.
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Bank Select Address
DQ0 ~ DQ63
Data input/output
DQS0 ~ DQS7
Data Strobe input/output
CK0,CK0 ~ CK2, CK2 Clock input
CKE0,CKE1
Clock enable input
CS0, CS1
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DM0 ~ 7
Data - in mask
VDD
Power supply (2.5V)
VDDQ
Power Supply for DQS(2.5V)
VSS
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (2.3V to 3.6V)
SDA
Serial data I/O
SCL
Serial clock
SA0 ~ 2
Address in EEPROM
VDDID
VDD identification flag
NC
No connection
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Front Pin Front Pin Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
/CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
*CB0
*CB1
VDD
*DQS8
A0
*CB2
VSS
*CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
CK0
/CK0
VSS
*DM8
A10
*CB6
VDDQ
*CB7
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
KEY
M368L6423DTM DDR SDRAM 184pin DIMM
64Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
FEATURE
KEY
Performance range
Power supply : Vdd: 2.5V
0.2V, Vddq: 2.5V
0.2V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 2, 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1250 (mil), double sided component
Part No.
Max Freq.
Interface
M368L6423DTM-CB3
166MHz(6ns@CL=2.5)
SSTL_2
184pin Unbuffered DDR SDRAM MODULE
M368L6423DTM
Rev. 1.0 Dec. 2002
Functional Block Diagram
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D0
DM0
DM
D9
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ11
DM
I/O 7
I/O 6
I/O 1
I/O 0
D1
DM
D10
I/O 5
I/O 4
I/O 3
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
DM1
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
I/O 7
I/O 6
I/O 1
I/O 0
D2
DM
D11
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM2
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
I/O 7
I/O 6
I/O 1
I/O 0
D3
DM
D12
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM3
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
I/O 7
I/O 6
I/O 1
I/O 0
D4
DM4
DM
D13
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
I/O 7
I/O 6
I/O 1
I/O 0
D5
DM
D14
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM5
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
I/O 7
I/O 6
I/O 1
I/O 0
D6
DM
D15
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
I/O 7
I/O 6
I/O 1
I/O 0
D7
DM
D16
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM7
A0 - A12
A0-A12: DDR SDRAMs D0 - D15
RAS
RAS: DDR SDRAMs D0 - D15
CAS
CAS: DDR SDRAMs D0 - D15 CKE0
CKE: DDR SDRAMs D0 - D7
WE
WE: DDR SDRAMs D0 - D15
CS0
CS1
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
CS
Clock Wiring
CK0/CK0
Clock
Input
DDR SDRAMs
CK1/CK1
4 DDR SDRAMs
6 DDR SDRAMs
6 DDR SDRAMs
CKE1
CKE: DDR SDRAMs D8 - D15
BA0 - BA1
BA0-BAn: DDR SDRAMs D0 - D15
DQS0
DQS
DQS4
DQS1
DQS5
DQS
DQS
DQS2
DQS
DQS
DQS3
DQS
DQS
DM6
DQS6
DQS7
DQ15
I/O 2
I/O 5
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
DQS
CK2/CK2
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
WP
V
SS
D0 - D15
D0 - D15
V
DD
/V
DDQ
D0 - D15
D0 - D15
VREF
V
DDID
Strap: see Note 4
V
DDSPD
SPD
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms +
5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD
VDDQ.
5. BAx, Ax, RAS, CAS, WE resistors: 3
Ohms + 5%
*Clock Net Wiring
Card
Edge
D3/D0/D5
D4/D1/D6
Cap/D2/D7
Cap/D9/D14
D12/D10/D15
D13/D11/D16
R=120
CK0/1/2
Cap will replace DRAM
*If four DRAMs are loaded,
*
*
*D8, D17 is assigned for ECC Comp.
184pin Unbuffered DDR SDRAM MODULE
M368L6423DTM
Rev. 1.0 Dec. 2002
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to Vss
V
DD
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to Vss
V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
24
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Notes 1. Includes
25mV margin for DC offset on V
REF
, and a combined total of
50mV margin for all AC noise and DC offset on V
REF
,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled
TO V
REF
, both of which may result in V
REF
noise. V
REF
should be de-coupled with an inductance of
3nH.
2.V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to
V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70
C)
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V
DD
of 2.5V)
V
DD
2.3
2.7
I/O Supply voltage
V
DDQ
2.3
2.7
V
I/O Reference voltage
V
REF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
DDQ
+0.3
V
4
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
4
Input Voltage Level, CK and CK inputs
V
IN
(DC)
-0.3
V
DDQ
+0.3
V
Input Differential Voltage, CK and CK inputs
V
ID
(DC)
0.3
V
DDQ
+0.6
V
3
Input crossing point voltage, CK and CK inputs
V
IX
(DC)
1.15
1.35
V
5
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver)
;V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver)
;V
OUT
=
V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver)
;V
OUT
= V
TT
- 0.45V
I
OL
9
mA
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