DRAM MODULE
M372E0405BT0-C
Buffered 4Mx72 DIMM
Revision 0.1
June 1998
(4Mx16 & 4Mx4 base)
DRAM MODULE
M372E0405BT0-C
Revision History
Version 0.0 (Sept. 1997)
Removed two AC parameters t
CACP
(access time from CAS) and t
AAP
(access time from col. addr.) in AC CHARACTERISTICS.
Changed the parameter t
CAC
(access time from CAS) from 18ns to 20ns @ -5 in AC CHARACTERISTICS.
Version 0.1 (June 1998)
The 3rd.(4th.) generation of 64M(16M) DRAM components are applied for this module.
DRAM MODULE
M372E0405BT0-C
M372E0405BT0-C EDO Mode
4M x 72 DRAM DIMM Using 4Mx16 & 4Mx4, 4K Refresh, 5V
The Samsung M372E0405BT0-C is a 4Mx72bits Dynamic
RAM high density memory module. The Samsung
M372E0405BT0-C consists of four 4Mx16bits & two 4Mx4bits
CMOS DRAM in SOJ/TSOP-II 400mil packages and two 16
bits driver IC in TSSOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The M372E0405BT0-
C is a Dual In-line Memory Module and is intended for mount-
ing into 168 pin edge connector sockets.
GENERAL DESCRIPTION
Part Identification
- M372E0405BT0-C (4096cycles/64ms Ref. TSOP ll)
Extended Data Out Mode Operation
CAS-before-RAS Refresh capability
RAS-only and Hidden refresh capability
TTL compatible inputs and outputs
Single 5V
10% power supply
JEDEC standard pinout & Buffered PDpin
Buffered input except RAS and DQ
PCB : Height(1000mil), single sided component
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
HPC
-C50
50ns
18ns
84ns
20ns
-C60
60ns
20ns
104ns
25ns
PD Note :PD & ID Terminals must each be pulled up through a register to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
PIN NAMES
Pins marked
*
are not used in this module.
Pin Names
Function
A0, B0, A1 - A11
Address Input(4K ref.)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0, RAS2
Row Address Strobe
CAS0, CAS4
Column Address Strobe
V
CC
Power(+5V)
V
SS
Ground
NC
No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
PD & ID Table
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
Pin
50NS
60NS
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
0
ID0
ID1
0
0
0
0
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
*CAS2
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
A12
V
CC
RFU
RFU
V
SS
OE2
RAS2
CAS4
*CAS6
W2
V
CC
RSVD
RSVD
DQ18
DQ19
V
SS
DQ20
DQ21
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
RSVD
RSVD
V
CC
RFU
*CAS1
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
*CAS3
*RAS1
RFU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
RFU
B0
V
SS
RFU
*RAS3
*CAS5
*CAS7
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
FEATURES
DRAM MODULE
M372E0405BT0-C
RAS2
W2
OE2
B0
CAS4
A1-A11
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
A0
B0
A1-A11
W0, OE0
W2, OE2
U0-U2
U3-U5
U0-U5
U0-U2
U3-U5
RAS0
W0
OE0
A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
CAS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A1-A11
DQ16
DQ17
DQ18
DQ19
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
U0
U1
U2
U3
U4
U5
DRAM MODULE
M372E0405BT0-C
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
*
I
CC2
I
CC3
*
I
CC4
*
I
CC5
I
CC6
*
I(
IL)
I(
OL)
V
OH
V
OL
Symbol
Speed
M372E0405BT0
Unit
Min
Max
I
CC1
-50
-60
-
-
720
660
mA
mA
I
CC2
Don
t care
-
100
mA
I
CC3
-50
-60
-
-
720
660
mA
mA
I
CC4
-50
-60
-
-
660
600
mA
mA
I
CC5
Don
t care
-
30
mA
I
CC6
-50
-60
-
-
720
660
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-5
10
5
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
V
V
* NOTE : I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
-1 to +7.0
-1 to +7.0
-55 to +125
6
50
V
V
C
W
mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+2.0V at pulse width
20ns, which is measured at V
CC
.
*2 : -2.0V at pulse width
20ns, which is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
4.5
0
2.4
-1.0
*2
5.0
0
-
-
5.5
0
V
CC
*1
0.8
V
V
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: Extended Data Out Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
PDF 
ZIP