DRAM MODULE
M372F0805DT0-C
REV. 0.1 Oct. 2000
M372F0805DT0-C EDO Mode
8M x 72 DRAM DIMM with ECC Using 4Mx16 & 4Mx4, 4K Refresh, 3.3V
The Samsung M372F0805DT0-C is a 8Mx72bits Dynamic
RAM high density memory module. The Samsung
M372F0805DT0-C consists of eight 4Mx16bits & four
4Mx4bits CMOS DRAMs in TSOP-II 400mil packages and two
16 bits driver IC in TSSOP package mounted on a 168-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor
is mounted on the printed circuit board for each DRAM. The
M372F0805DT0-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
GENERAL DESCRIPTION
PD Note :PD & ID Terminals must each be pulled up through a register to V
CC
at the next higher
level assembly. PDs will be either open (NC) or driven to V
SS
via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to V
SS
without a buffer.
Part Identification
- M372F0805DT0-C(4096cycles/64ms Ref. TSOP ll)
Extended Data Out Mode Operation
CAS-before-RAS Refresh capability
RAS-only and Hidden refresh capability
TTL compatible inputs and outputs
Single 3.3V
0.3V power supply
JEDEC standard pinout & Buffered PDpin
Buffered input except RAS and DQ
PCB : Height(1000mil), double sided component
PIN NAMES
Pins marked
*
are not used in this module.
Pin Names
Function
A0, B0, A1 - A11
Address Input(4K ref.)
DQ0 - DQ71
Data In/Out
W0, W2
Read/Write Enable
OE0, OE2
Output Enable
RAS0 - RAS3
Row Address Strobe
CAS0, 1,4,5
Column Address Strobe
V
CC
Power(+3.3V)
V
SS
Ground
NC
No Connection
PDE
Presence Detect Enable
PD1 - 8
Presence Detect
ID0 - 1
ID bit
RSVD
Reserved Use
RFU
Reserved for Future Use
PD & ID Table
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
Pin
50NS
60NS
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
0
ID0
ID1
0
0
0
0
PIN CONFIGURATIONS
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
DQ16
DQ17
V
SS
RSVD
RSVD
V
CC
W0
CAS0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
*CAS2
RAS0
OE0
V
SS
A0
A2
A4
A6
A8
A10
A12
V
CC
RFU
RFU
V
SS
OE2
RAS2
CAS4
*CAS6
W2
V
CC
RSVD
RSVD
DQ18
DQ19
V
SS
DQ20
DQ21
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ22
DQ23
V
CC
DQ24
RFU
RFU
RFU
RFU
DQ25
DQ26
DQ27
V
SS
DQ28
DQ29
DQ30
DQ31
V
CC
DQ32
DQ33
DQ34
DQ35
V
SS
PD1
PD3
PD5
PD7
ID0
V
CC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
V
SS
DQ36
DQ37
DQ38
DQ39
V
CC
DQ40
DQ41
DQ42
DQ43
DQ44
V
SS
DQ45
DQ46
DQ47
DQ48
DQ49
V
CC
DQ50
DQ51
DQ52
DQ53
V
SS
RSVD
RSVD
V
CC
RFU
CAS1
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
*CAS3
RAS1
RFU
V
SS
A1
A3
A5
A7
A9
A11
*A13
V
CC
RFU
B0
V
SS
RFU
RAS3
CAS5
*CAS7
PDE
V
CC
RSVD
RSVD
DQ54
DQ55
V
SS
DQ56
DQ57
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ58
DQ59
V
CC
DQ60
RFU
RFU
RFU
RFU
DQ61
DQ62
DQ63
V
SS
DQ64
DQ65
DQ66
DQ67
V
CC
DQ68
DQ69
DQ70
DQ71
V
SS
PD2
PD4
PD6
PD8
ID1
V
CC
FEATURES
PERFORMANCE RANGE
Speed
t
RAC
t
CAC
t
RC
t
HPC
-C50
50ns
18ns
84ns
20ns
-C60
60ns
20ns
104ns
25ns
DRAM MODULE
M372F0805DT0-C
REV. 0.1 Oct. 2000
DQ16
-
DQ19
DQ20
-
DQ35
DQ0
-
DQ15
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
A0
B0
A1-A11
W0, OE0
W2, OE2
U0-U2,U6-U8
U3-U5,U9-U11
U0-U11
U0-U2,U6-U8
U3-U5,U9-U11
RAS0
W0
OE0
A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CAS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A1-A11
DQ0
DQ1
DQ2
DQ3
U0
U1
U2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
U6
U7
U8
RAS3
W2
OE2
B0
CAS4
A1-A11
RAS1
DQ52
-
DQ55
DQ56
-
DQ71
DQ36
-
DQ51
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
U3
U4
U5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
U9
U10
U11
RAS2
CAS1
CAS5
DRAM MODULE
M372F0805DT0-C
REV. 0.1 Oct. 2000
I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time, t
HPC
.
* NOTE :
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
V
IN
, V
OUT
V
CC
T
stg
P
D
I
OS
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
12
50
V
V
C
W
mA
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
I
CC1
*
I
CC2
I
CC3
*
I
CC4
*
I
CC5
I
CC6
*
I(
IL)
I(
OL)
V
OH
V
OL
Symbol
Speed
M372F0805DT0
Unit
Min
Max
I
CC1
-50
-60
-
-
666
606
mA
mA
I
CC2
Don
t care
-
100
mA
I
CC3
-50
-60
-
-
666
606
mA
mA
I
CC4
-50
-60
-
-
526
466
mA
mA
I
CC5
Don
t care
-
30
mA
I
CC6
-50
-60
-
-
666
606
mA
mA
I
I(L)
I
O(L)
Don
t care
-10
-10
10
10
uA
uA
V
OH
V
OL
Don
t care
2.4
-
-
0.4
V
V
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current (RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
: Extended Data Out Mode Current * (RAS=V
IL
, CAS cycling : t
HPC
=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
V
IN
Vcc+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
V
OUT
Vcc)
: Output High Voltage Level (I
OH
= -2mA)
: Output Low Voltage Level (I
OL
= 2mA)
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70
C)
*1 : V
CC
+1.3V at pulse width
15ns, which is measured at V
CC
.
*2 : -1.3V at pulse width
15ns, which is measured at V
SS
.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
V
CC
V
SS
V
IH
V
IL
3.0
0
2.0
-0.3
*2
3.3
0
-
-
3.6
0
V
CC
+0.3
*1
0.8
V
V
V
V
DRAM MODULE
M372F0805DT0-C
REV. 0.1 Oct. 2000
CAPACITANCE
(T
A
= 25
C, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0, B0, A1 - A11]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0, 1,4,5]
Input/Output capacitance[DQ0 - 71]
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
-
-
-
-
-
20
20
31
20
24
pF
pF
pF
pF
pF
Test condition : V
ih
/V
il
=2.2/0.7V, V
oh
/V
ol
=2.0/0.8V, output loading CL=100pF
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
t
RC
84
104
ns
Read-modify-write cycle time
t
RWC
128
153
ns
Access time from RAS
t
RAC
50
60
ns
3,4,10
Access time from CAS
t
CAC
18
20
ns
3,4,5,13
Access time from column address
t
AA
30
35
ns
3,10,13
CAS to output in Low-Z
t
CLZ
8
8
ns
3,13
OE to output in Low-Z
t
OLZ
8
8
ns
3,13
Output buffer turn-off delay from CAS
t
CEZ
8
18
8
18
ns
6,11,13
Transition time(rise and fall)
t
T
1
50
1
50
ns
2
RAS precharge time
t
RP
30
40
ns
RAS pulse width
t
RAS
50
10K
60
10K
ns
RAS hold time
t
RSH
13
15
ns
13
CAS hold time
t
CSH
36
38
ns
13
CAS pulse width
t
CAS
8
10K
10
10K
ns
RAS to CAS delay time
t
RCD
15
32
18
40
ns
4,13
RAS to column address delay time
t
RAD
10
20
13
25
ns
10,13
CAS to RAS precharge time
t
CRP
10
10
ns
13
Row address set-up time
t
ASR
5
5
ns
13
Row address hold time
t
RAH
5
8
ns
13
Column address set-up time
t
ASC
0
0
ns
14
Column address hold time
t
CAH
7
10
ns
14
Column address to RAS lead time
t
RAL
30
35
ns
13
Read command set-up time
t
RCS
0
0
ns
Read command hold referenced to CAS
t
RCH
0
0
ns
8
Read command hold referenced to RAS
t
RRH
-2
-2
ns
8,13
Write command set-up time
t
WCS
0
0
ns
7
Write command hold time
t
WCH
7
10
ns
Write command pulse width
t
WP
7
10
ns
Write command to RAS lead time
t
RWL
13
15
ns
13
Write command to CAS lead time
t
CWL
7
10
ns
17
Data set-up time
t
DS
-2
-2
ns
9,13
Data hold time
t
DH
13
15
ns
9,13
Refresh period
t
REF
64
64
ms
CAS to W delay time
t
CWD
33
38
ns
7,16
RAS to W delay time
t
RWD
68
82
ns
7,13
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
DRAM MODULE
M372F0805DT0-C
REV. 0.1 Oct. 2000
AC CHARACTERISTICS
(0
C
T
A
70
C, V
CC
=3.3V
0.3V. See notes 1,2.)
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Column address to W delay time
t
AWD
45
53
ns
7
CAS precharge time to W delay time
t
CPWD
47
58
ns
CAS setup time(CAS-before-RAS refresh)
t
CSR
10
10
ns
13,18
CAS hold time(CAS-before-RAS refresh)
t
CHR
8
8
ns
13
RAS to CAS precharge time
t
RPC
3
3
ns
13
Access time from CAS precharge
t
CPA
33
40
ns
3,13
Hyper page cycle time
t
HPC
20
25
ns
12
Hyper page read-modify-write cycle time
t
HPRWC
70
77
ns
12
CAS precharge time(Hyper page cycle)
t
CP
7
10
ns
15
RAS pulse width (Hyper page cycle)
t
RASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
t
RHCP
35
40
ns
13
W to RAS precharge time(C-B-R refresh)
t
WRP
15
15
ns
13
W to RAS hold time(C-B-R refresh)
t
WRH
8
8
ns
13
OE access time
t
OEA
18
20
ns
13
OE to data delay
t
OED
15
18
ns
13
Output buffer turn off delay time from OE
t
OEZ
8
18
8
18
ns
13
OE command hold time
t
OEH
5
5
ns
Output data hold time(C-B-R refresh)
t
DOH
10
10
ns
13
Output buffer turn off delay time from RAS
t
REZ
3
13
3
13
ns
6,11
Output buffer turn off delay time from W
t
WEZ
8
18
8
18
ns
6,13
W to data delay
t
WED
20
20
ns
13
OE to CAS hold time
t
OCH
5
5
ns
CAS hold time to OE
t
CHO
5
5
ns
OE precharge time
t
OEP
5
5
ns
W pulse width (Hyper page cycle)
t
WPE
5
5
ns
PDE to Valid PD bit
t
PD
10
10
ns
PDE to PD bit Inactive
t
PDOFF
2
7
2
7
ns
Present Detect Read Cycle
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