Rev. 0.0 Jun. 1999

M377S1620DT3

PC100 Registered DIMM

PIN NAMES

* These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

Pin Name

Function

A0 ~ A11

Address input (Multiplexed)

BA0 ~ BA1

Select bank

DQ0 ~ DQ63

Data input/output

CB0 ~ CB7

Check bit (Data-in/data-out)

CLK0

Clock input

CKE0

Clock enable input

CS0, CS2

Chip select input

RAS

Row address strobe

CAS

Colume address strobe

Write enable

DQM0 ~ 7

DQM

Power supply (3.3V)

Ground

REF

Power supply for reference

REGE

SDA

Serial data I/O

SCL

Serial clock

SA0 ~ 2

Address in EEPROM

Don

t use

No connection

Write protection

PIN CONFIGURATIONS (Front side/back side)

Pin

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

Front

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7
DQ8

DQ9

DQ10
DQ11
DQ12
DQ13

DQ14
DQ15

CB0
CB1

NC
NC

DQM0

Pin

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Front

DQM1

CS0

A0
A2
A4
A6
A8

A10/AP

BA1

CLK0

CS2

DQM2
DQM3

NC
NC

CB2
CB3

DQ16
DQ17

Pin

57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84

Front

DQ18
DQ19

DQ20

REF

*CKE1

DQ21
DQ22
DQ23

DQ24
DQ25
DQ26
DQ27

DQ28
DQ29
DQ30
DQ31

*CLK2

**SDA

**SCL

Pin

85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112

Back

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39
DQ40

DQ41
DQ42
DQ43
DQ44
DQ45

DQ46
DQ47

CB4
CB5

NC
NC

CAS

DQM4

Pin

113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

Back

DQM5

*CS1

RAS

A1
A3
A5
A7
A9

BA0

A11
V

*CLK1

*A12

CKE0

*CS3

DQM6
DQM7

*A13

NC
NC

CB6
CB7

DQ48
DQ49

Pin

141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168

Back

DQ50
DQ51

DQ52

REF

REGE

DQ53
DQ54
DQ55

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

*CLK3

**SA0
**SA1
**SA2

The Samsung M377S1620DT3 is a 16M bit x 72 Synchronous

Dynamic RAM high density memory module. The Samsung

M377S1620DT3 consists of eighteen CMOS 16Mx4 bit Syn-

chronous DRAMs in TSOP-II 400mil packages, three 18-bits

Drive ICs for input control signal, one PLL in 24-pin TSSOP

package for clock and one 2K EEPROM in 8-pin TSSOP pack-

age for Serial Presence Detect on a 168-pin glass-epoxy sub-

strate. Two 0.22uF and one 0.0022uF decoupling capacitors

are mounted on the printed circuit board in parallel for each

SDRAM. The M377S1620DT3 is a Dual In-line Memory Mod-

ule and is intented for mounting into 168-pin edge connector

sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies allows the same device to be useful for a variety of high

bandwidth, high performance memory system applications.

GENERAL DESCRIPTION

M377S1620DT3 SDRAM DIMM (Intel 1.2 ver. Base)

16Mx72 SDRAM DIMM with PLL & Register based on 16Mx4, 4Banks, 4K Ref., 3.3V Synchronous DRAMs with SPD

FEATURE

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

�

Performance range

� Burst mode operation
� Auto & self refresh capability (4096 Cycles/64ms)
� LVTTL compatible inputs and outputs
� Single 3.3V

�

0.3V power supply

� MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
� All inputs are sampled at the positive going edge of the
system clock
� Serial presence detect with EEPROM
� PCB : Height (1,700mil) , double sided component

Part No.

Max Freq. (Speed)

M377S1620DT3-C1H

100MHz (10ns @ CL=2)

M377S1620DT3-C1L

100MHz (10ns @ CL=3)

Rev. 0.0 Jun. 1999

M377S1620DT3

PC100 Registered DIMM

PIN CONFIGURATION DESCRIPTION

Pin

Name

Input Function

CLK

System clock

Active on the positive going edge to sample all inputs.

Chip select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+tss prior to valid command.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

BA0 ~ BA1

Bank select address

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Write enable

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

DQM0 ~ 7

Data input/output mask

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

REGE

Register enable

The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V

through 10K ohm

Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

CB0 ~ 7

Check bit

Check bits for ECC.

Write protection

WP pin is connected to V

through 47K

Resistor.

When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write-protected.

Power supply/ground

Power and ground for the input buffers and the core logic.

Rev. 0.0 Jun. 1999

M377S1620DT3

PC100 Registered DIMM

CB4~7

DQ44~47

DQ36~39

FUNCTIONAL BLOCK DIAGRAM

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

Serial PD

SDA

SCL

SA1 SA2

SA0

PCLK0

BCS0

CKE0

A0~B

A11,B

BA0,B

BA1,B

RAS,B

CAS,B

BDQM0

DQ0~3

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

DQ4~7

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

PCLK1

BDQM1

DQ8~11

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

DQ12~15

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

CB0~3

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

PCLK4

BDQM2

DQ20~23

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

PCLK5

A0~B

A11,B

BA1,B

RAS,B

CAS,B

BDQM3

DQ28~31

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

DQ24~27

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D10

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D11

BDQM5

DQ40~43

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D12

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D14

DQ48~51

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D13

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D15

BDQM6

DQ52~55

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D17

BDQM7

DQ60~63

CLK
CS
CKE
Add,CTL
DQM
DQ0~3

D16

DQ56~59

CKE0

BDQM4

DQ32~35

PCLK3

BCS2

DQ16~19

47K

PCLK2

,BA0

SN74ALVC162835

,BA1

CS2

CKE0

DQM2,3,6,7

RAS, B

CAS, B

RAS, B

CAS, B

BCS0
BDQM0,1,4,5

10k

SN74ALVC162835

PCLK6

REGE

11.

BA1

11.

BA1

BCS2
B

CKE0

BDQM2,3,6,7

SN74ALVC162835

RAS,CAS,WE

11.

BA1

11.

BA1

BCS2
B

CKE0

BDQM2,3,6,7

BA0

CS0

DQM0,1,4,5

* Note
1. Unused clock termination : 10

and 12pF

2. The actual values of

will depend upon the PLL chosen.

CDC2509

IY0

IY1

IY2

IY3

IY4

2Y0

2Y1

CLK
FIBIN

CLK0

FBOUT

PCLK0

PCLK1

PCLK2

PCLK3

PCLK4

PCLK5

PCLK6

27pF

Rev. 0.0 Jun. 1999

M377S1620DT3

PC100 Registered DIMM

*1. Register Input

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK

RAS

CAS

RAS

CAS

CAS latency(refer to *1)

tSAC

tRDL

Read

Row Active

Command

Row Active

Write

Command

Precharge
Command

1CLK

td, tr = Delay of register (74ALVC162835)

Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVC162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D

is to be issued 1clock after write command in external timing because D

is issued directly to module.

: Don

care

STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)

*2. Register Output

*3. SDRAM

REG

Control Signal(RAS,CAS,WE)

OUT

=2CLK+1CLK

tRAC(refer to *1)

tRAC(refer to *2)

CAS latency(refer to *2)

Qa0

Qa1

Qa2

Qa3

Db0

Db1

Db2

Db3

=2CLK

Precharge
Command

Rev. 0.0 Jun. 1999

M377S1620DT3

PC100 Registered DIMM

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

OUT

-1.0 ~ 4.6

Voltage on V

supply relative to Vss

, V

DDQ

-1.0 ~ 4.6

Storage temperature

STG

-55 ~ +150

�

Power dissipation

Short circuit current

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Note :

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

= 0V, T

= 0 to 70

�

Parameter

Symbol

Min

Typ

Max

Unit

Note

Supply voltage

3.0

3.3

3.6

Input high voltage

2.0

3.0

DDQ

+0.3

Input low voltage

-0.3

0.8

Output high voltage

2.4

= -2mA

Output low voltage

0.4

= 2mA

Input leakage current

-10

CAPACITANCE

= 3.3V, T

= 23

�

C, f = 1MHz, V

REF

=1.4V

�

200

mV)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A

~ A

)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0)

Input capacitance (CLK0)

Input capacitance (CS0, CS2)

Input capacitance (DQM0 ~ DQM7)

Input capacitance (BA0 ~ BA1)

Data input/output capacitance (DQ0 ~ DQ63)

Data input/output capacitance (CB0 ~ CB7)

IN1

IN2

IN3

IN4

IN5

IN6

IN7

OUT

1. V

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Notes :

Электронный компонент: M377S1620DT3-C1H