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Электронный компонент: P13B16212A

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M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
The Samsung M464S3254DTS is a 32M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M464S3254DTS consists of eight CMOS 16M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy
substrate. Three 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each SDRAM. The
M464S3254DTS is a Small Outline Dual In-line Memory Module
and is intended for mounting into 144-pin edge connector sock-
ets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
Performance range
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Serial presence detect with EEPROM
PCB : Height (1,250mil), double sided component
Part No.
Max Freq. (Speed)
M464S3254DTS-L7C/C7C
133MHz@CL=2
M464S3254DTS-L7A/C7A
133MHz@CL=3
M464S3254DTS-L1H/C1H
100MHz @ CL=2
M464S3254DTS-L1L/C1L
100MHz @ CL=3
FEATURE
GENERAL DESCRIPTION
M464S3254DTS SDRAM SODIMM
32Mx64 SDRAM SODIMM based on 16Mx16, 4Banks, 8K Refresh,3.3V Synchronous DRAMs with SPD
PIN NAMES
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63
Data input/output
CLK0 ~ CLK1
Clock input
CKE0 ~ CKE1
Clock enable input
CS0 ~ CS1
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
DQM
V
DD
Power supply (3.3V)
V
SS
Ground
SDA
Serial data I/O
SCL
Serial clock
DU
Don
t use
NC
No connection
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQM0
DQM1
V
DD
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQM4
DQM5
V
DD
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
DQ14
DQ15
V
SS
NC
NC
CLK0
V
DD
RAS
WE
CS0
CS1
DU
V
SS
NC
NC
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
DQ46
DQ47
V
SS
NC
NC
CKE0
V
DD
CAS
CKE1
A12
*A13
CLK1
V
SS
NC
NC
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
A9
A10/AP
V
DD
DQM2
DQM3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
**SDA
V
DD
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
BA1
A11
V
DD
DQM6
DQM7
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
**SCL
V
DD
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Voltage Key
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ
0
~
63
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
FUNCTIONAL BLOCK DIAGRAM
V
DD
Vss
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM
To all SDRAMs
A0 ~ A12, BA0 & 1
CKE0
RAS
CAS
WE
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U3
DQM4
CS0
DQM0
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM
CS
UDQM
DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
LDQM
CS
UDQM
DQM6
DQM2
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQM
CS
UDQM
DQM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
LDQM
CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM
CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM
CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM
CS
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQM
CS
UDQM
CS1
CKE1
SDRAM U4 ~ U7
U0/U4
U1/U5
CLK0/1
U2/U6
U3/U7
DQn
Every DQ pin of SDRAM
10
Serial PD
SDA
SCL
SA1 SA2
SA0
WP
47K
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to Vss
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
8
W
Short circuit current
I
OS
50
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70
C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
3.0
3.3
3.6
V
Input high voltage
V
IH
2.0
3.0
V
DDQ
+0.3
V
1
Input low voltage
V
IL
-0.3
0
0.8
V
2
Output high voltage
V
OH
2.4
-
-
V
I
OH
= -2mA
Output low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
LI
-10
-
10
uA
3
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23
C, f = 1MHz, V
REF
= 1.4V
200
mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A
0
~ A
12
, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0 ~ CKE1)
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0 ~ CS1)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
OUT
25
25
15
15
15
10
13
45
45
25
21
25
12
18
pF
pF
pF
pF
pF
pF
pF
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
C)
Parameter
Symbol
Test Condition
Version
Unit
Note
-7C
-7A
-1H
-1L
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
t
RC
(min)
I
O
= 0 mA
560
520
520
520
mA
1
Precharge standby cur-
rent in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 10ns
16
mA
I
CC2
PS
CKE & CLK
V
IL
(max), t
CC
=
16
Precharge standby cur-
rent in non power-down
mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
160
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
80
Active standby current in
power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 10ns
48
mA
I
CC3
PS
CKE & CLK
V
IL
(max), t
CC
=
48
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
240
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
200
mA
Operating current
(Burst mode)
I
CC4
I
O
= 0 mA
Page burst
4banks Activated.
t
CCD
= 2CLKs
680
680
640
640
mA
1
Refresh current
I
CC5
t
RC
t
RC
(min)
1000
920
880
880
mA
2
Self refresh current
I
CC6
CKE
0.2V
C
24
mA
L
12
mA
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
Notes :
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
0.3V, T
A
= 0 to 70
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
50pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
Unit
Note
-7C
-7A
-1H
-1L
Row active to row active delay
t
RRD
(min)
15
15
20
20
ns
1
RAS to CAS delay
t
RCD
(min)
15
20
20
20
ns
1
Row precharge time
t
RP
(min)
15
20
20
20
ns
1
Row active time
t
RAS
(min)
45
45
50
50
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
60
65
70
70
ns
1
Last data in to row precharge
t
RDL
(min)
2
CLK
2, 5
Last data in to Active delay
t
DAL
(min)
2 CLK + tRP
-
5
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
ea
4
CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-7C
-7A
-1H
-1L
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
7.5
1000
10
1000
10
1000
ns
1
CAS latency=2
7.5
10
10
12
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
5.4
6
6
ns
1,2
CAS latency=2
5.4
6
6
7
Output data
hold time
CAS latency=3
t
OH
3
3
3
3
ns
2
CAS latency=2
3
3
3
3
CLK high pulse width
t
CH
2.5
2.5
3
3
ns
3
CLK low pulse width
t
CL
2.5
2.5
3
3
ns
3
Input setup time
t
SS
1.5
1.5
2
2
ns
3
Input hold time
t
SH
0.8
0.8
1
1
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
5.4
6
6
ns
CAS latency=2
5.4
6
6
7
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
t care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
12,
A
11
A
9
~ A
0
Note
Register
Mode register set
H
X
L
L
L
L
X
OP code
1,2
Refresh
Auto refresh
H
H
L
L
L
H
X
X
3
Self
refresh
Entry
L
3
Exit
L
H
L
H
H
H
X
X
3
H
X
X
X
3
Bank active & row addr.
H
X
L
L
H
H
X
V
Row address
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
L
Column
address
(A
0
~ A
8
)
4
Auto precharge enable
H
4,5
Write &
column address
Auto precharge disable
H
X
L
H
L
L
X
V
L
Column
address
(A
0
~ A
8
)
4
Auto precharge enable
H
4,5
Burst stop
H
X
L
H
H
L
X
X
6
Precharge
Bank selection
H
X
L
L
H
L
X
V
L
X
All banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
X
X
X
Precharge power down mode
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
V
V
V
DQM
H
V
X
7
No operation command
H
X
H
X
X
X
X
X
L
H
H
H
1. OP Code : Operand code
A
0
~ A
12
& BA
0
~ BA
1
: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
Tolerances :
.006(.15) unless otherwise specified
The used device is 16Mx16 SDRAM, TSOP
SDRAM Part No. : K4S561632D
PACKAGE DIMENSIONS
2.66
2.50
Units : Inches (Millimeters)
2-R 0.078 Min
(2.00 Min)
0.18
(4.60)
0.91
(23.20)
1.29
(32.80)
0
.
2
4
(
6
.
0
)
0.13
0
.
7
9
(
2
0
.
0
0
)
(3.30)
(63.60)
(67.56)
Detail Z
0.16
0.0039
(4.00
0.10)
0.06
0.0039
(1.50
0.1)
2-
0.07
(1.80)
1
.
2
5
(
3
1
.
7
5
)
0.16
0.039
(4.00
0.10)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
0.150 Max
0.04
0.0039
(1.00
0.10)
0
.
1
2
5

M
i
n
(
3
.
2
0

M
i
n
)
(3.80 Max)
0
.
1
5
7

M
i
n
(
4
.
0
0

M
i
n
)
1
59
61
143
2
60
62
144
0.03 TYP
0.024
0.001
0.008
0.006
(0.200
0.150)
(0.600
0.050)
(0.80 TYP)
0
.
1
0
0

M
i
n
(
2
.
5
4
0

M
i
n
)
Detail Y
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
Byte#.
Function described
Function Supported
Hex value
Note
-7C
-7A
-1H
-1L
-7C
-7A
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
13
0Dh
1
4
# of column address on this assembly
9
09h
1
5
# of module Rows on this assembly
2 Row
02h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
7.5ns
10ns
10ns
75h
75h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
5.4ns
6ns
6ns
54h
54h
60h
60h
2
11
DIMM configuration type
Non parity
00h
12
Refresh rate & type
7.8us, support self refresh self
82h
13
Primary SDRAM width
x16
10h
14
Error checking SDRAM width
None
00h
15
Minimum clock delay for back-to-back random column
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered/Non-Registered &
redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
10ns
12ns
75h
A0h
A0h
C0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
6ns
7ns
54h
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
2
26
SDRAM access time @CAS latency of 1
-
00h
2
27
Minimum row precharge time (=t
RP
)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
28
Minimum row active to row active delay (t
RRD
)
15ns
15ns
20ns
20ns
0Fh
0Fh
14h
14h
29
Minimum RAS to CAS delay (=t
RCD
)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
30
Minimum activate precharge time (=t
RAS
)
45ns
45ns
50ns
50ns
2Dh
2Dh
32h
32h
31
Module Row density
2 Row of 128MB
20h
32
Command and Address signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
33
Command and Address signal input hold time
0.8ns
0.8ns
1ns
1ns
08h
08h
10h
10h
34
Data signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
M464S3254DTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L
Organization : 32MX64
Composition : 16MX16 *8
Used component part # : K4S561632D-TL7C/7A/1H/1L,TC7C/7A/1H/1L
# of rows in module : 2row
# of banks in component : 4 banks
Feature : 1,250 mil height & double sided component
Refresh : 8K/64ms
Contents :
M464S3254DTS
Rev. 0.0 Jan. 2002
PC133/PC100 SODIMM
SERIAL PRESENCE DETECT INFORMATION
Byte #
Function described
Function Supported
Hex value
Note
-7C
-7A
-1H
-1L
-7C
-7A
-1H
-1L
35
Data signal input hold time
0.8ns
0.8ns
1ns
1ns
08h
08h
10h
10h
36~61
Superset information (maybe used in future)
-
00h
62
SPD data revision code
Current release Intel spd 1.2B/A
12h
63
Checksum for bytes 0 ~ 62
-
79h
BAh
21h
51h
64
Manufacturer JEDEC ID code
Samsung
CEh
65~71
...... Manufacturer JEDEC ID code
Samsung
00h
72
Manufacturing location
Onyang Korea
01h
73
Manufacturer part # (Memory module)
M
4Dh
74
Manufacturer part # (DIMM configuration)
4
34h
75
Manufacturer part # (Data bits)
Blank
20h
76
...... Manufacturer part # (Data bits)
6
36h
77
...... Manufacturer part # (Data bits)
4
34h
78
Manufacturer part # (Mode & operating voltage)
S
53h
79
Manufacturer part # (Module depth)
3
33h
80
...... Manufacturer part # (Module depth)
2
32h
81
Manufacturer part # (Refresh, # of banks in Comp. & inter-
5
35h
82
Manufacturer part # (Composition component)
4
34h
83
Manufacturer part # (Component revision)
D
44h
84
Manufacturer part # (Package type)
T
54h
85
Manufacturer part # (PCB revision & type)
S
53h
86
Manufacturer part # (Hyphen)
" - "
2Dh
87
Manufacturer part # (Power)
L / C
4Ch / 43h
88
Manufacturer part # (Minimum cycle time)
7
7
1
1
37h
37h
31h
31h
89
Manufacturer part # (Minimum cycle time)
C
A
H
L
43h
41h
48h
4Ch
90
Manufacturer part # (TBD)
Blank
20h
91
Manufacturer revision code (For PCB)
S
53h
92
...... Manufacturer revision code (For component)
D-die (5th Gen.)
44h
93
Manufacturing date (Year)
-
-
3
94
Manufacturing date (Week)
-
-
3
95~98
Assembly serial #
-
-
4
99~12
Manufacturer specific data (may be used in future)
Undefined
-
5
126
System frequency for 100MHz
100MHz
64h
127
Intel Specification details
Detailed 100MHz Information
CFh
CFh
CFh
CDh
128+
Unused storage locations
Undefined
-
5
1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung
s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung
s own purpose.
Note :