AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

INTRODUCTION

AM: AM RF MIXER, AM OSC,
AM_IF AMP, AM Detector,
AGC, Tuning LED Driver,
OSC Buffer, IF Buffer

FM: RF AMP, FM RF MIXER,
FM OSC, FM_IF AMP,
Quadrature Detector,
Tuning LED Driver,
OSC Buffer, IF Buffer

MPX: PLL, Stereo Decoder, Stereo LED, MPX VCO Self-adjustment

DTS : Prescaler, AM/FM Programmable Divider, AM/FM IF Counter, Lock Detector, LED Controller

Microprocessor Interface

FEATURE

Adopt New FCC

AM/FM 1 Chip DTS with PLL

MPX-VCO Self-adjustment

Programmable Divider
FM: 10 to 160MHz <pulse swallow technique>
AM: 0.5 to 10MHz <direct division technique>

IF COUNTER : 0.4 to 12MHz <AM/FM IF COUNTING>

Reference Frequency
Twelve Selectable Frequency
1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100kHz
(Selectable Crystal 75kHz, 3.6MHz, 7.2MHz, 10.8MHz choice)

Built-in Transistor for forming an active low-pass filter

Package : 44 QFP/48 LQFP

ORDERING INFORMATION

Device

Package

Supply voltage

Operating Temperature

S1A0903X01-Q0R0

44-QFP-1010B

2 to 7V

-20 to +75

S1A0903X01-E0R0

48-LQFP-0707AN

44-QFP-1010B

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

BLOCK DIAGRAM

44-QFP

LOUT

ROUT

TUNLED

STLED

VSSA

AOUT

AIN

VSSX

XOUT

XIN

MIXOUT

AMLOWCUT

GND_RF

FMRFIN

AMRFIN

FMRFOUT

VCC_RF

AMOSC

VDDA

FMOSC

VCDC

IO[20:0]

IF[18:0]

R[3:0]

N[3:0]

N[16:4]

UL[1:0]

XS[1:0]

GT[1:0]

TEST[1:0]

DZ[1:0]

DLC

DOC[1:0]

IFCS

VREG

TEST3

VDD

TEST2

TEST1

VSSD

PD[6:0]

MUTE

IFS[1:0]

MOST

TUNLEDC

AMIFIN

VCC

AGCCAP

FMIFIN

DETOUT

GND

MPXIN

LPF1

LPF2

LPF3

FMQUAD

DET

AGC

DET

LEVEL

DET

MIX

OSC

1/2

HYS

LED

CONTROL

COUNTER

VCO

MPX VCO

CONTROL

PILOT

DET

PHASE

DET

F/F

DECODER

LED

DRV

LED

DRV

PRESCALER

MAIN

COUNTER

SWALLOW

COUNTER

PFD

DOC[1:0]

TEST[1:0]

DLC

TUNLEDC

MOST

OS[1:0]

XS[1:0]

R[3:0]

IFCS

MUTEC

MUTE

IFS[1:0]

GT[1:0]

DZ[1:0]

UL[1:0]

N[15:0]

DATA SHIFT REGISTER

CHARGE

PUMP

LOCK

DETECT

REF

DIVIDER

TEST CONTROL

SERIAL INTERFACE

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

BLOCK DIAGRAM

48-LQFP

LOUT

ROUT

TUNLED

STLED

VSSA

AOUT

AIN

VSSX

XOUT

XIN

MIXOUT

AMLOWCUT

GND_RF

FMRFIN

AMRFIN

FMRFOUT

VCC_RF

AMOSC

VDDA

FMOSC

VCDC

IO[20:0]

IF[18:0]

R[3:0]

N[3:0]

N[16:4]

UL[1:0]

XS[1:0]

GT[1:0]

TEST[1:0]

DZ[1:0]

DLC

DOC[1:0]

IFCS

VREG

TEST3

VDD

TEST2

TEST1

VSSD

PD[6:0]

MUTE

IFS[1:0]

MOST

TUNLEDC

AMIFIN

VCC

AGCCAP

FMIFIN

DETOUT

GND

MPXIN

LPF1

LPF2

LPF3

FMQUAD

DET

AGC

DET

LEVEL

DET

MIX

OSC

1/2

HYS

LED

CONTROL

COUNTER

VCO

MPX VCO

CONTROL

PILOT

DET

PHASE

DET

F/F

DECODER

LED

DRV

LED

DRV

PRESCALER

MAIN

COUNTER

SWALLOW

COUNTER

PFD

DOC[1:0]

TEST[1:0]

DLC

TUNLEDC

MOST

OS[1:0]

XS[1:0]

R[3:0]

IFCS

MUTEC

MUTE

IFS[1:0]

GT[1:0]

DZ[1:0]

UL[1:0]

N[15:0]

DATA SHIFT REGISTER

CHARGE

PUMP

LOCK

DETECT

REF

DIVIDER

TEST CONTROL

SERIAL INTERFACE

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

PIN CONFIGURATION

Pin No.

Symbol

In/Out

Function

44-QFP

48-LQFP

LOUT

Stereo left channel output

ROUT

Stereo right channel output

TUNLED

Tuning LED

STLED

Stereo LED

VSSA

Ground

AOUT

Connections for the Tr. used for the PLL active LPF.

AIN

PLL charge pump output

VSSX

Crystal GND

XOUT

Crystal oscillator element connection

XIN

(75kHz, 3.6MHz, 7.2MHz, 10.8MHz)

Serial data output to the microprocessor

Clock used for data synchronization for serial data input(DI)
and serial data output(DO)

Serial data input from the microprocessor

Chip enable for serial I/O

VSSD

Ground

TEST1

I/O

Only for test

TEST2

I/O

TEST3

VDD

Regulator voltage input

VREG

Regulator voltage output

No connection

* 48-LQFP: 9, 17 pin NC

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

PIN CONFIGURATION (Continued)

Pin No.

Symbol

In/Out

Function

44-QFP

48-LQFP

VCDC

VCC ripple rejection cap.

FMOSC

FM oscillator input

VDDA

Power

AMOSC

AM oscillator input

VCC_RF

RF-Power

FMRFOUT

FM RF output

AMRFIN

AM RF input

FMRFIN

FM RF input

GND_RF

RF-Ground

AMLOWCUT

AM lowcut cap.

MIXOUT

AM/FM MIX output

AGCCAP

AGC cap.

AMIFIN

AM IF input

FMIFIN

FM IF input

VCC

Power

LPF1

connection for the phase detector and the VCO LPF

GND

Ground

MPXIN

MPX input

DETOUT

AM/FM Detect Output

LPF2

connection for the VCO LPF

LPF3

connection for the pilot detector and the phase detector LPF

FMQUAD

connection for the FM QUAD detector resonator

* 48-LQFP: 33, 41 pin NC

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

PIN DESCRIPTION

ANALOG BLOCK I/O PIN

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

LOUT

ROUT

VCC

GND

1/2

1.1

TUNLED

STLED

GND

VCC 37

3/4

VSSA

AOUT

AIN

VSSA

VCC 37

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

ANALOG BLOCK I/O PIN (Continued)

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

VDD

VSSA

cf. Digital block I/O PIN

VREG

GND

VDDA 25

1.8

VCCCAP

GND

VCC 37

2.85

3.0

FMOSC

VCC_RF

GND

3.0

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

ANALOG BLOCK I/O PIN (Continued)

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

VDDA

3.0

AMOSC

VCC

GND

3.0

VCC_RF

3.0

FMRFOUT

FMRFIN

GND_RF

VCC_RF

VCC 37

3.0

0.8

AMRFIN

VCC_RF

GND_RF

3.0

FMRFIN

cf. PIN28

GND_RF

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

ANALOG BLOCK I/O PIN (Continued)

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

AMLOWCUT

VCC

GND

1.7

MIXOUT

VCC_RF

FM MIX

GND

AM MIX

GND_RF

VCC

3.0

2.9

AGCCAP

VCC

GND

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

ANALOG BLOCK I/O PIN (Continued)

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

AMIFIN

VCC

GND

3.0

FMIFIN

VCC

GND

3.0

VCC

3.0

LPF1

cf. PIN42

2.2

GND

MPXIN

GND

VCC 37

0.8

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

ANALOG BLOCK I/O PIN (Continued)

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

DETOUT

VCC

GND

1.0

LPF1

LPF2

GND

VCC

GND

VCC

2.2

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

ANALOG BLOCK I/O PIN (Continued)

(Terminal voltage: Typical terminal voltage at no signal with test circuit, V

= 3V, Ta = 25

Pin No.

Pin Name

Internal Circuit

(Standard 44-QFP Device)

Terminal(Typ.)

Voltage (V)

44-QFP

48-LQFP

LPF3

GND

VCC 37

2.2

FMQUAD

GND

VCC 37

2.2

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

DIGITAL BLOCK I/O PIN

Pin No.

Pin Name

Internal Circuit

Remark

44-QFP

48-LQFP

(Standard 44-QFP device)

VSSX

XOUT

XIN

VDDA

VDD

VSSX

VSSD

13/14/15

VSSD

TEST1

TEST2

17/18

VDD

VSSD

CDL

TEST3

VDD

VSSD

CDL

VDD

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

INPUT AND OUTPUT OF SERIAL DATA

SERIAL DATA FORMAT AND TIMING

Internal

data latching

Old

New

tLC

tDH

tEH

VIH

VIL

VIH

VIL

VIH

VIL

tCL

tCH

tSU

tHD

tES

tDC

Figure 1. Serial Data I/O Format and Timing

Parameter

Symbol

Conditions

Ratings

Unit

Min.

Typ.

Max.

Data setup time

DI, CL

0.75

Data hold time

DI, CL

0.75

Cock low level time

0.75

Clock high level time

0.75

CE setup time

CE, CL

0.75

CE hold time

CE, CL

0.75

Data latch change time

0.75

Data output time

DO, CL

0.35

DO, CE

0.35

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

STRUCTURE OF DI CONTROL DATA(SERIAL DATA INPUT)

[ IN1 MODE ]

[ IN2 MODE ]

I20

I19

I18

I17

I16

DSR
Data

tEH

tLC

tES

tHD

tSU

OLD

NEW

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

OS1

OS0

N15

N14

N13

N12

N11

N10

IFCS

MUTEC

MUTE

ADDRESS

OSC

SELECT

PROGRAMMABLE DIVISOR DATA

(N1[3:0] : 4 BIT , N2[15:4] : 12 BIT)

IF CNT. START

MUTE OFF

CONTROL

MUTE ON/OFF

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

XS1

XS0

IFS1

IFS0

GT1

GT0

DZ1

DZ0

UL1

UL0

DOC1

DOC0

DLC

TUNLEDC

MOST

TEST1

TEST0

ADDRESS

X'TAL

SELECT

REFERENCE

DIVIDER DATA

SENSITIVITY

CONTROL

MEASURE

TIME

DEADZONE

CONTROL

UNLOCK

CONTROL

DO PIN

CONTROL

DEADLOCK

CLEAR

TUNLED

CONTROL

MO/ST

CONTROL

TEST

DATA

Figure 2. Serial Data Input Timing and Format

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

DI CONTROL DATA

No.

Control Block/Data

Function

Programmable Divider

Data

OS<1:0>

N<15:0>

Select the input source

FM : Real divisor = 2

AM : Real divisor = N

N[3:0] are "don't care" in the case of AMLF

If Counter

Start Data

IFCS

IF counter start control data

IFCS = 1 : Start the IF counter

IFCS = 0 : Reset the IF counter

After OUTMODE SIO, IFCS is automatically reset to 0

Mute

Control Data

MUTEC, MUTE

MUTE select/control data

MUTEC = 0 : Microprocessor set MUTE

MUTE is automatically reset when tuning LED is on

Whenever BAND is switched from AM to FM, MUTE is automatically

on until MPX VCO free-running frequency self_adjustment is end

Reference

Crystal Data

XS<1:0>

Crystal selection data

OS1

OS0

LSB

AM/FM

Frequency Range

Divisor(N)

160MHz

256

65535

AMLF

0.5

10MHz

4096

MUTEC

MUTE

Function

MUTE off

Self controlled

MUTE on

MUTE off

Microprocessor

MUTE on

controlled

XS1

XS0

CRYSTAL OSC.

3.6MHz

75kHz

7.2MHz

10.8MHz

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

DI CONTROL DATA (Continued)

No.

Control Block/Data

Function

Reference

Frequency

Select Data

R<3:0>

Reference frequency selection

PLL stop mode

Programmable divider and IF counter are stopped.
Charge Pump's output is a high- impedance state.

All stop mode

All the frequency of DTS control block is stopped Control data are
holded the previous state

: No use

Sensitivity

Control Data

IFS<1:0>

IF sensitivity control

Reference frequency

3.6,7.2,10.8MHz

75kHz

100 kHz

50 kHz

25 kHz

15 kHz

12.5 kHz

10 kHz

9 kHz

6.25 kHz

5 kHz

3.125 kHz

3 kHz

1 kHz

All stop

PLL stop + X'tal OSC. stop

PLL stop

IFS1

IFS0

Sensitivity (AM / FM)

0dB / 0dB

-4B / -5dB

-8B / -10dB

-12/ -16dB

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

DI CONTROL DATA (Continued)

No.

Control Block/Data

Function

If Counter

Control Data

GT<1:0>

Select IF counter measurement time

Dead Zone

Control Data

DZ<1:0>

Dead zone data

ON: Both of NMOS and PMOS in Charge pump turn on in the same

time and Dead zone is reduced

OFF: Each of NMOS and PMOS in Charge pump turn mutual

exclusively on

Unlock State

Control Data

UL<1:0>

decide the LOCK state with the width of Phase error(

DOC[1:0] = 2: DO pin is controlled with LOCK state

UL[1:0] = 1: Width of

E set DO pin low, else high

GT1

GT0

Measurement time (ms)

DZ1

DZ0

Charge Pump

DeadZone

--0

-0

OFF

++0

UL1

UL0

E Detection Width

DO Pin State

stopped

hold the previous state

E is directly out

0.55us

E is extended by 2ms

1.11us

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

DI CONTROL DATA (Continued)

No.

Control Block/Data

Function

DO Pin

Control Data

DOC<1:0>

DO pin control data

When CE is low, DOC[1:0] controls DO pin

Deadlock Clear

Control Data

DLC

Deadlock clear data

DLC = 1 : The output of Charge pump is forcibly set to low, which

makes control voltage VCC and gets out of DEADLOCK condition

DLC = 0 : Normal operation

Tuning Led

Control Data

TUNLEDC

LED control data

Abobe condition is IFS[1:0] = 0

The point of turning Tuning LED on depends on the value of IFS[1:0]

Mono, Stereo Control Data

MOST

MONO/STEREO control

MOST = 1 : Set STEREO mode

MOST = 0 : Set forcibly MONO mode

Test

Control Data

TEST<1:0>

Test data

DOC1 DOC0

Function

DO pin open

DTS PLL = lock, DO pin = open

IF counting = end, DO pin = low

TUNLEDC

32dB

=> LED On

45dB

=> LED On

32dB

and within

450kHz

5kHz

=> LED On

45dB

and within

10.7MHz

12.5kHz

=> LED On

TEST1

TEST0

Function

NORMAL OPERATION

TEST MODE1

TEST MODE2

TEST MODE3

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

STRUCTURE OF DO OUTPUT DATA(SERIAL TEST DATA OUTPUT)

[ OUT MODE ]

O20

O18

O17

O16

tHD

tSU

tDH

tDC

tEH

tES

O19

O20

O19

O18

O17

O16

O15

O14

O13

O12

O11

O10

STID

LOCK

C18

C17

C16

C15

C14

C13

C12

C11

C10

STEREO

INDICATE

LOCK

STATE

IF COUNTER BINARY DATA

Figure 3. Serial Data Output Timing and Format

DI OUTPUT DATA

No.

Control Block/Data

Function

STEREO INDICATION DATA

STID

STID = 1 : detect STEREO
STID = 0 : detect MONO

PLL LOCKED STATE DATA

LOCK

LOCK = 1 : PLL is lock
LOCK = 0 : PLL isn't lock

IF COUNTER BINARY DATA

C18

C18 : IF counter value (MSB)
C0 : IF counter value (LSB)

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

STRUCTURE OF TEST MODE DO OUTPUT DATA(SERIAL DATA OUTPUT)

[TEST MODE0 ]

[ TEST MODE1,2,3]

O20

O18

O17

O16

tHD

tSU

tDH

tDC

tEH

tES

O19

OS1

O20

O19

O18

O17

O16

O15

O14

O13

O12

O11

O10

OS0

N15

N14

N13

N12

N11

N10

IFCS

MUTEC

MUTE

O20

O19

O18

O17

O16

O15

O14

O13

O12

O11

O10

XS1

XS0

IFS1

IFS0

GT1

GT0

DZ1

DZ0

UL1

UL0

DOC1

DOC0

DLC

TUNLEDC

MOST

TEST1

TEST0

Figure 4. Serial Test Data Output Timing and Format

DO OUTPUT DATA

No.

Mode

Function

TEST MODE0

When TEST[1:0]=0 in MODE2 data,
IN1 data in Data Shift Register is sent from DO pin to Microprocessor
synchronously with the CL

TEST MODE1,2,3

When TEST[1:0]=1,2,3 in MODE2 data,
IN1 data in Data Shift Register is sent from DO pin to Microprocessor
synchronously with the CL

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

PROGRAMMABLE DIVIDER STRUCTURE

SERIAL INTERFACE

O20

O18

O17

O16

O19

I20

I18

I17

I16

I19

Figure 5. Serial I/O Timing

A[1:0]

Mode

DI / DO

Remarks

TEST

Data of IN1(TEST[1:0]=0) or IN2(TEST[1:0]=1,2,3) latched in DSR are

transferred to serial interface, which data are transferred to Micro-
processor through DO pin synchronized with the CL

IN1

Data I[20:0] from DI pin are latched in IN1 or IN2 Data shift register on

B point.

IN2

When OS[1:0] in IN1 MODE is changed, N[16:0] is changed and R[3:0]

is changed from PLL STOP MODE, Fr and Fc counter are reset which
make lock time of PLL fixed.

OUT

Data of OUT MODE latched in DSR are transferred on A point, which

data transferred to Microprocessor through DO pin synchronized with
the CL.

IFCS bit is reset on B point, which makes Micro-processor restart IF

counter

DOC1

DOC0

OUTMODE

DO Pin State

Open

When LOCK bit in OUT MODE is high, DO pin holds the
low state.

When IF counting is end, DO pin holds the low state.

Open

OUTMODE data are transferred through DO pin

X : don't care

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

1/N BLOCK

1/N block is used for frequency down-scaling from AM OSC. or FM OSC. to reference frequency Fr and
Prescaler, Swallow Counter, Main Counter is used for a natural number dividing.

FM OSC/2

AM OSC

XIN

[A]

Prescaler

1/16, 1/17

[B]

[C]

Swallow

Counter

Main

Counter

N[3:0]

N[15:0]

Phase

Frequency

Detector

R[3:0]

Reference

Divider

AM = fr=fc=AMOSC/N
FM = fr=fc=FMOSC/2N

N Divider

Figure 6. 1/N block diagram

OS1

OS0

Input Frequency

Input Frequency Range

FM / 2

80 MHz

AMLF

0.5

10 MHz

N = (16

N2) + N1

= 17

N1 + 16

(N2 - N1)

Fc is derived from OSC. divided by N, N2 is derived from N[16:4] and N1 is derived from N[3:0]

17XN1

16X(N2-N1)

counting number of M.C

counting number of S.C

divisor of Prescaler

counting number of M.C

Figure 7. 1/N counting method

Prescaler : operates on FM MODE.

Swallow Counter : counts down with N1 divisor and divides Fp by 17 on operation of swallow counter and
divide by 16 until S.C reloads N1 at the end of Fc 1 period.

Main Counter : makes Fc divided by N2 divisor from Fp divided by 16 or 17

Reference Divider : makes Fr divided by R[3:0] divisor from X'tal.

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

For FM with a step size of 50kHz
FM RF = 89.3MHz (IF = 10.7MHz)
FM VCO = 100.0MHz
Reference clock(Fr) = 50kHz
100.0MHz(FM VCO)

50kHz(fr)

2 = 1000

03E8(hex)

1
5

1
4

1
3

1
2

1
1

1
0

C
S

T
E

X : don't care

For AMLF with a step size of 9kHz
AMLF RF = 1161kHz (IF = 450kHz)
AM VCO = 1611kHz
Reference clock(fr) = 9kHz
1611kHz(AM VCO)

9kHz(fr) = 179

OB3(hex)

1
5

1
4

1
3

1
2

1
1

1
0

C
S

T
E

X : don't care

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

Fc generated by First example of setting 'N' divisor
N[15:0] = 03E8(hex) = 1000(dec)
N1 = N[3:0] = 8
N2 = N[15:4] = 3E(hex) = 62(dec)
Fc is divided by 17 with the amount of N1 and divided by 16 with the amount of N2 - N1 in Figure. 8.

OSC/2

Divided

by 16

Divided

by 17

Divided by 17 (N1)

Divided by 16 (N2 - N1)

Figure 8. Generated FC by First Example

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

PHASE FREQUENCY DETECTOR

STATE1

STATE2

STATE3

A=V

B=V

A=V

B=V

A=V

B=V

Figure 9. PFD state diagram

VDD

VSSA

Figure 10. PFD scheme

States are changed on rising edges of Fr or Fc in Figure. 9(Fr moving to higher states and Fc moving to lower
states) Suppose the circuit is initially in state 1, Then alternate rising edges on Fr and Fc will cycle between
states 1 and 2. If Fc is constantly falling behind Fr in phase, as in the timing diagram(Figure. 11 A point), then
eventually there will be two Fr rising edges without an intervening Fc rising edge. This will take the circuit to state
3, and thereafter it will cycle between state 2 and state3.
For phase difference of Fc and Fr is almost zero, the rising edges of Fr and Fc are coincident, and the PD
remains in state 2 almost all the time

Z-state Phase Frequency Detector is composed of 3-State PFD and two MOS gates

State 1 : make the frequency of Fc slower.

State 2 : hold the frequency of Fc.

State 3 : make the frequency of Fc faster.

State transition at rising edges of Fr and Fc

rising edge of Fr : cause current state to go high

rising edge of Fc : cause current state to go low

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

VFC

VFR

State

VPD

Figure 11. Timing Diagram (DZ[1:0]=0)

differences of deadzone (in Figure. 10)

DZ[1]

DZ[0]

MX2 path

MX4 path

PMOS / NMOS

DeadZone

remarks

on/on

--0

(1)

on/on

-0

(2)

off/off

(3)

off/off

++0

(4)

DZ[1:0] = 0 mode : Even though PLL loop is locked, generate phase error pulse and phase error

correction pulse which make Deadzone reduced.

DZ[1:0] = 1 mode : Same as Dz[1:0] = 0 mode, but a width of phase error correction pulse is relatively
narrower.

DZ[1:0] = 2 mode : Generate only phase error pulse but phase error correction pulse.

DZ[1:0] = 3 mode : Same as DZ[1:0] = 2 mode, but a width of phase error pulse is relatively narrower.

DZ[1:0] = 0 or 1

Excellent C/N characteristics

Sidebands may be created by reference frequency leakage

Sidebands may be created by low-frequency leakage due to the correction pulse envelope.

DZ[1:0] = 2 or 3

PLL loop stable

DEADZONE

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

Old data

New data ( OS[1:0] or N[15:0] is changed )

DSR's

Data

VPD

Figure 12. PFD and PD Output Relationship

Error pulse is made from rising edge of Fr and Fc.

If rising edge of Fc is slower than that of Fr, set Vpd to low

make the frequency of Fc fast. (Figure. 9 state1)

If rising edge of Fc is faster than that of Fr, set Vpd to high

make the frequency of Fc slow. (Figure. 9 state3)

A region with no

Error makes Vpd high impedance and hold the frequency of Fc

When data are changed in OS[1:0], N[15:0] or changed in R[3:0] from PLL stop mode.

reset Fc and Fr counter(Figure. 12 A) and change PFD in state 2

After new data is latched, accurate

Error can be reflected on the first phase error(Figure. 12 B)

Lock time can be estimated in advance depending on N[15:0] or OS[1:0] is changed

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

LOCKED STATE DETECTION TIMING

preset

Lock

Error

N(16)

R(4)

VCO

L.P.F

1/R

1/N

Lock

Detector

Phase

Frequency

Detector

Figure 13. Lock Detection Scheme

Getting LOCK State

UL[1:0]

LOCK state in serial data

LOCK state on DO pin

Remarks

hold the previous state

E is out directly depending on SIO

timing

E is out directly

when

E is narrower than

E width more than 2ms, set LOCK

LOCK bit in serial data reflects LOCK state regardless of DOC[1:0]

DO pin reflects LOCK state only when DOC[1:0] is 2

LOCK : DO pin = open , UNLOCK : DO pin = low

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

Old data

New data ( OS[1:0] or N[15:0] is changed )

DSR's

Data

VCO

frequency

Error

LOCK bit

DO pin

LOCK

UNLOCK

LOCK

data in

data out

Figure 14. Lock detection timing diagram

LOCK bit in serial data

LOCK bit in serial data shows UNLOCK because VCO frequency isn't stable (Figure. 14 A)

wait at least several cycle and check LOCK again(Figure. 14 B)

needs several LOCK check in order to get more reliable result.

LOCK state on DO pin

Only when DOC[1:0]=1 and UL[1:0]

0, LOCK state can be checked on DO pin

needs several LOCK check in order to get more reliable result.

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

IF COUNTER

Count IF frequency during measurement time(GT[1:0]), start counting on IFCS setting high.

GT[1:0]

IF Counter

DSR
C[18:0]

IFCS

4/8/16/

32ms

LSB MSB

0 - 18

Figure 15. IF Counter Structure

C[18:0] = F

GT : Counted value (the number of pulse)

GT1

GT0

Measurement time(GT)

GT1

GT0

Measurement time(GT)

4 ms

16 ms

8 ms

32 ms

IFCS

Measurement

Time

Frequency

Figure 16. IF counter operation

In Figure. 16

When IFCS bit is zero, IF counter is reset. On IFCS bit is turning to one, IF counter starts to count IF
frequency during measurement time. Then IF counter holds the counted value. If DOC[1:0] is 3, inform

the micro- processor of the end of counting by means of setting DO pin to be low.

IF counter is automatically reset after sending serial data to Micro- processor and ready to count.

If IF frequency less than 45kHz(FM : 1.07MHz) comes into IF counter during first 100us of measurement
time(GT[1:0]), inform Micro-processor of the end of counting by means of setting DO pin to be low in the
case that DOC[1:0] is 3, even though measurement time isn't passed .

After measurement time(GT[1:0]) is passed, IFCS bit has to be held 1. Unless IFCS bit is held to be one,
counted IF value is all reset to be 0.

IFCS bit is automatically reset after Micro-processor reads the counted IF values.

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

MPX VCO FREE-RUNNING-FREQUENCY SELF-ADJUSTING CONTROLLER

FMSW

PD[6:0]

1111110

55.47ms

0.853ms

1111101

XXXXXXX

ADJUST

MODE

1111111

0.853ms

Figure 17. MPX VCO Free-Running Adjustment Timing Diagram

Whenever band is switched to the FM mode, FM MPX VCO free-running frequency will be adjusted between
302.5kHz and 309.5kHz using control code PD[6:0]

A region : wait time for MPX VCO to oscillate due to band switching.

B region : measure MPX VCO free-running frequency and check whether free-running frequency is between
302.5kHz

309.5kHz or not. If MPX VCO free-running frequency is between 302.5kHz

309.5kHz, hold

the control code and end the adjusting.

C region : reduce control code PD[6:0] into 1 step, make free-running frequency fast. If PD[6:0] is
1111111(bin), VCO frequency will be minimum frequency and If PD[6:0] is 0000000(bin), VCO frequency will
be maximum frequency.

In adjusting MPX VCO free-running, MUTE will be set to one.

The result of MPX VCO free-running adjust is out through TEST1 pin, when TEST[1:0] is zero.

TEST1 pin = 1 : operating VCO free-running adjustment

TEST1 pin = 0 : success adjusting VCO free-running between 302.5kHz

309.5kHz

TEST1 pin = 1.172kHz/2 : 1.172kHz/2 frequency is out when first adjustment cycle
(maximum adjustment time : 164.7ms / 1 cycle) is failed. Try to adjust VCO free-running on and on,
TEST1 pin is set to be zero when VCO free-running frequency is between 302.5kHz

309.5kHz

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

TEST FUNCTION

TEST[1:0]

TEST1 Pin

TEST2 Pin

TEST3 Pin

Remarks

OUT

ADJRESULT

(1)

TFCOUT

TFROUT

TMPXVCO

(2)

TIF

TLEDRSTB

TIFMINMAX

(2)

TFCIN

TFRIN

(2)

ADJRESULT : out MPX VCO adjustment result

1 : on adjusting

0 : success in adjustment

1.172kHz : 1st. adjustment cycle is failed, but adjusting 2nd, 3rd adjustment cycle.

TFCOUT : Fc Frequency divided by N[16:0]

TIF : IF frequency comes in through external source for test

TFCIN : Fc frequency comes in through external source for test

TLEDRSTB : counter reset signal of tuning LED control block comes in through external source for test

TFRIN : Fr frequency comes in through external source for test

TFROUT : Fr frequency divided by R[4:0]

TMPXVCO : MPX VCO free-running frequency which is end of adjusting

TIFMINMAX : Minimum and maximum of IF frequency which is used to check tuning LED operation

TEST[1:0]=0 :inform the state of MPX VCO free-running adjustment

TEST[1:0]=1 : Fc frequency for testing N divider block, Fr frequency for testing X'tal divider block, MPX
VCO free-running frequency for testing MPX VCO self adjusting block

TEST[1:0]=2 : IF frequency, reset signal of LED control counter and IF Min. Max value for testing LED
control block

TEST[1:0]=3 : Fc and Fr frequency for testing PFD and LOCK detector

(1) : If A[1:0] is zero, send the IN1 MODE data latched in DSR to Micro- processor through DO pin
synchronized with falling edge of CL

(2) : If A[1:0] is zero, send the IN2 MODE data latched in DSR to Micro- processor through DO pin
synchronized with falling edge of CL

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Ratings

Unit

Remarks

Supply Voltage

Operating Temperature

Top

-20

+75

Storage Temperature

Tstg

-55

+150

Power Dissipation

Pdmax

1800

TEMPERATURE CHARACTERISTICS

Parameter

Symbol

Condition

Ratings

Unit

Remarks

Quiescent circuit current1(FM)

Icc1

-20

+75

uA/

Quiescent circuit current2(AM)

Icc2

-20

+75

uA/

ELECTRO_STATIC DISCHARGE CHARACTERISTICS

Parameter

Condition

Pin No.

Ratings

Unit

Remarks

Human Body Model

C = 100pF, R = 1.5k

ALL PINS

2000

Machine Model

C = 200pF, R = 0 k

ALL PINS

200

CDM

ALL PINS

500

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

ELECTRICAL CHARACTERISTICS

(Ta = 25

C, Vcc = 3V. unless otherwise specified)

FM F/E : f = 98MHZ, fm = 1kHz,

f = 22.5kHz, AM : f = 1MHz, fm = 1kHz, 30% Mod

FM IF : f = 10.7MHZ, fm = 1kHz,

f = 22.5kHz, MPX : f = 1kHz, L+R = 90%, P = 10%, Vi = 150mV)

Parameter

Symbol

Condition

Ratings

Unit

Min.

Typ.

Max.

Supply Voltage Range

Vcc

2.0

7.0

Supply Current

Iccq1

FM, Vi = 0

Iccq2

AM, Vi = 0

2.5

F/E

Input Limiting

Voltage

Vi lim1

Vo = -3dB

dBu

Local Oscillation

Voltage

Vosc

fosc = 108.7MHz

110

Input Limiting

Voltage

Vi lim2

Vo = -3dB

dBu

Detection Output

Voltage

Vo det1

Vi = 80dBu

110

S/N Ratio

S/N1

Vi = 80dBu

FM IF

AM Depression

Ratio

AMR

Vi = 80dBu

THD

THD1

Vi = 80dBu

0.2

1.0

LED Turning On

Vl11

IFS[1:0] = 0

sensitivity

VI12

IFS[1:0] = 1

VI13

IFS[1:0] = 2

VI14

IFS[1:0] = 3

Voltage Gain

Gv1

Vi = 26dBu

Detection Output

Voltage

Vo det2

Vi = 60dBu

110

LED Turning On

Vl21

IFS[1:0] = 0

VI22

IFS[1:0] = 1

VI23

IFS[1:0] = 2

VI24

IFS[1:0] = 3

AM IF

S/N Ratio

S/N2

Vi = 60dBu

THD

THD2

Vi = 60dBu

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

ELECTRICAL CHARACTERISTICS (Continued)

(Ta = 25

C, Vcc = 3V. unless otherwise specified)

FM F/E : f = 98MHZ, fm = 1kHz,

f = 22.5kHz, AM : f = 1MHz, fm = 1kHz, 30% Mod

FM IF : f = 10.7MHZ, fm = 1kHz,

f = 22.5kHz, MPX : f = 1kHz, L+R = 90%, P = 10%, Vi = 150mV)

Parameter

Symbol

Condition

Ratings

Unit

Min.

Typ.

Max.

Maximum Input Voltage

Vimax

Stereo, THD = 3%

300

450

Voltage Gain

Gv2

-5

-1

0.5

Channel Balance

Mono

-1.5

1.5

THD1

THD3

Mono

0.2

1.0

MPX

THD2

THD4

Stereo

0.2

1.0

Separation 1

CS1

Stereo, f=100Hz

Separation 2

CS2

Stereo, f=1kHz

Separation 3

CS3

Stereo, f=10kHz

LED Turning On

Sensitivity

Vlon

TUNLED=ON,

Pilot only

LED Turning Off

Sensitivity

Vloff

TUNLED = OFF,

Pilot only

Lamp Hysteresis

Capture Range

Pilot only

S/N Ratio

S/N3

Mono

Mute Attenuation

Amute

Input

High Level

Vih

CE, DI, CL

0.7Vreg

Voltage

Low Level

Vil

CE, DI, CL

0.3Vreg

Output

High Level

Voh1

PD : lo=-1mA

0.7Vreg

Voltage

Low Level

Vol1

PD : lo=1mA

0.3Vreg

Vol2

DO : lo=5mA

0.3Vreg

DTS

Output Voltage Range

Aout

Internal Feedback

Registance

XIN

0.4

Input Current

Iin1

CE, DI, CL=VDD or

GND

Iin2

XIN=VDD or GND

1.3

Idd1

X'tal=10.8MHz,

FM=130MHz

2.5

Supply Current

Idd2

PLL stop mode,

X'tal=10.8MHz

0.3

Idd3

PLL stop mode,

X'tal stop mode

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

TEST CIRCUIT

44-QFP

micro-

processor

TEST IN

B.P.F

19kHz

BRF

0.022uF 2k

AMRFIN

FMRFIN

330

0.47uF

IFT1

1uF

450k

10.7M

330

VCC1

FMIFIN

AMIFIN

220uF

0.1uF

0.1

GND

4.7uF

DETOUT

MPXIN

0..1uF

3.3uF

0.33

10.7M

OUT

4.7uF

0.015uF

560

VCC2

10K

0.047

1uF

2.2K

0.022

10K

X_SW

20pF

TEST1

TEST2

TEST3

TEST OUT

0.1uF

10uF

2.2uF

68pF

4.7K

VD1

0.1uF

220uF

33K

VD4

470pF

220uF

0.1uF

4.7K

68pF

VD2

2.7mH

10K

S1A0903X01

0.015uF

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

TEST CIRCUIT

48-LQFP

micro-

processor

TEST IN

B.P.F

19kHz

BRF

0.022uF 2k

AMRFIN

FMRFIN

330

0.47uF

IFT1

1uF

450k

10.7M

330

VCC1

FMIFIN

AMIFIN

220uF

0.1uF

0.1

GND

4.7uF

DETOUT

MPXIN

0..1uF

3.3uF

0.33

10.7M

OUT

4.7uF

0.015uF

560

VCC2

10K

0.047

1uF

2.2K

0.022

10K

X_SW

20pF

TEST1

TEST2

TEST3

TEST OUT

0.1uF

10uF

2.2uF

68pF

4.7K

VD1

0.1uF

220uF

33K

VD4

470pF

220uF

0.1uF

4.7K

68pF

VD2

2.7mH

10K

S1A0903X01

0.015uF

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

APPLICATION CIRCUIT

44-QFP

micro-

processor

B.P.F

Antenna

330

0.47uF

IFT1

1uF

450k

10.7M

VCC1

220uF

0.1uF

GND

3.3uF

0.33uF

10.7M

560

VCC2

10K

0.047

1uF

2.2K

0.022

10K

20pF

0.1uF

10uF

2.2uF

68pF

4.7K

VD1

0.1uF

220uF

33K

VD4

470pF

220uF

0.1uF

4.7K

68pF

VD2

10K

S1A0903X01

1000p

4.7u

LOUT

0.015

4.7uF

ROUT

4.7uF

7.2M

20pF

10pF

12pF

33K

Antenna

VD3

22nF

0.015

B.P.F

: GFMG7 (KOREA SANGSHIN ELECTRIC Co.Ltd)

F1 (450kHz)

: 450 BL(Toko co.Ltd)

F2 (10.7MHz)

: SFE 10.7MA5 (MURATA Co.Ltd)

F3 (10.7MHz)

: CDALA10M7GA115A-B0 (MURATA Co.Ltd)

VD1, VD2

: KV1471 (Toko co.Ltd)

VD3, VD4

: KV1236 (Toko co.Ltd)

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

APPLICATION CIRCUIT

48-LQFP

micro-

processor

B.P.F

Antenna

330

0.47uF

IFT1

1uF

450k

10.7M

VCC1

220uF

0.1uF

GND

3.3uF

0.33uF

10.7M

560

VCC2

10K

0.047

1uF

2.2K

0.022

10K

20pF

0.1uF

10uF

2.2uF

68pF

4.7K

VD1

0.1uF

220uF

33K

VD4

470pF

220uF

0.1uF

4.7K

68pF

VD2

10K

S1A0903X01

1000p

4.7u

LOUT

0.015

4.7uF

ROUT

4.7uF

7.2M

20pF

10pF

12pF

33K

Antenna

VD3

22nF

0.015

B.P.F

: GFMG7 (KOREA SANGSHIN ELECTRIC Co.Ltd)

F1 (450kHz)

: 450 BL(Toko co.Ltd)

F2 (10.7MHz)

: SFE 10.7MA5 (MURATA Co.Ltd)

F3 (10.7MHz)

: CDALA10M7GA115A-B0 (MURATA Co.Ltd)

VD1, VD2

: KV1471 (Toko co.Ltd)

VD3, VD4

: KV1236 (Toko co.Ltd)

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

0.5

1.0

2.0

4.0

8.0

16.0

100

THD

(%)

RF Input Level

(dBu)

AM RF THD -RF Level

Vcc=3V
fin=1MHz
fm=1kHz,MOD=30%

0.5

1.5

2.5

3.5

4.5

5.5

Iccq2

(mA)

Vcc (V)

AM Iccq - Vcc

Vcc=3V
fin=1MHz

100

125

150

175

200

225

250

Voa1,

Voa2

(dB)

AM Modulation

(%)

AM RF Voa1,Voa2 - Modulation Level

Vcc=3V
fin=1MHz
fm=1kHz
Voa1 = RF IN 26dBu
Voa2 = RF IN 60dBu

Voa2

Voa1

-60

-50

-40

-30

-20

-10

10 20

30 40

50 60 70

80 90 100

RF Input Level (dBu)

AM RF Voa2,S/Na -RF Level

Vcc=3V
fin=1MHz
fm=1kHz,MOD=30%

Voa2,

S/Na

(dB)

Voa2

S/Na

AM Modulation

(%)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

20 30 40 50 60 70 80

THD

(%)

AM RF THD - Modulation Level

Vcc=3V
fin=1MHz
fm=1kHz
RF IN 60 dBu

-5

-4

-3

-2

-1

Voa2

(dB)

Vcc (V)

AM Voa2 - Vcc

Vcc=3V
fin=1MHz
fm=1kHz,MOD=30%
Voa2=RF IN 60dBu

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

THDf

(%)

RF Input Level (dBu)

FM RF+IF THDf-RF Level

Vcc=3V
fin=98MHz
fm=1kHz

f=22.5kHz

-20

100

-60

-50

-40

-30

-20

-10

Vof,S/Nf

(dB)

RF Input Level (dBu)

FM RF+IF Vof,S/Nf - RF Level

Vof

S/Nf

Vcc=3V
fin=98MHz
fm=1kHz

f=22.5kHz

-20

-10

100

0.0

0.5

1.0

1.5

2.0

2.5

THDf

(%)

IF Input Level (dBu)

FM IF THD - IF Level

Vcc=3V
fin=10.7MHz
fm=1kHz

f=22.5kHz

-20

110

-60

-50

-40

-30

-20

-10

Vof,

S/Nf
(dB)

FM IF Vof,S/Nf - IF Level

Vcc=3V
fin=10.7MHz
fm=1kHz

f=22.5kHz

IF Input Level (dBu)

Vof

S/Nf

-20

100

FM Icc - Vcc

Icc

(mA)

Vcc (V)

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

(MHz)

100

TURNS

1-4

WIRE

7*(1/2)

0.45m/m

KWANG SUNG

PART NO

SP-2065

FM RF

(MHz)

100

TURNS

1-4

WIRE

6*(1/2)

0.45m/m

KWANG SUNG

PART NO

SP-2066

FM OSC

SP-2065

SP-2066

(MHz)

796

TURNS

1-3

WIRE

KWANG SUNG

PART NO

KS50N-354

AM OSC

KS50N-354

(uH)

110

Co (pF)

470

TURNS

1-3

4-6

115

KWANG SUNG

PART NO

KS50N-SAA

AM IFT (MIX OUT)

KS50-SAA

1-3

(MHz)

455

S1A0903X01

AM/FM 1CHIP TUNER WITH PLL

TERMONOLOGY

DeadZone

PFD has to detect subtle phase error and makes phase error signal. There is a region that PFD doesn't make any
phase error pulse due to the propagation delay or other factors, which is called Deadzone.
Performance of PLL frequency synthesizer depends on the width of DeadZone
The characteristic of PFD is not ideal A(Figure. 18) but curved B(Fig. 18) because PLL frequency synthesizer
operates on reference signal just like a LPF(low pass filter)
The cause of Deadzone is that PFD doesn't generate phase error signal even though there is a phase error
between reference frequency and VCO divided by N. In general deadzone has several nano seconds width.
To implement a high S/N ratio system, the width of Deadzone is as narrow as possible. But, RF leakage in
MIXER block comes into VCO, which causes be a noise.

(ns)

DeadZone

Figure 18. PFD Characteristic

AM/FM 1CHIP TUNER WITH PLL

S1A0903X01

Application Note

1. Recommend using filter with 330

I/O impedance as 10.7MHz IF filter

2. Output gain of RF mixer is fixed by both of 330

10.7MHz IF filter. Thereafter to control output gain of mixer depends on changing load register on PIN 34, which
case both of input impedance of IF filter and load register are recommended to have same impedance.

3. Application of a input pin CE, DI, CL depends on the output of Micro-processor(Figure. 19). Input pin of CE,
CL, DI must be set to be VDD using R1 and R2 In the case of Figure.19 <B>.

VREG

100K

VREG

VDD

S1A0903X01

MICOM

CL,DI,CE

(13,14,15)

MICOM

CL,DI,CE

(13,14,15)

< A >

< B >

S1A0903X01

Figure 19. Connection between SIO and Microprocessor

4. Crystal can be selectable among 75kHz, 3.6MHz, 7.2MHz, 10.8MHz. The connection must be the same as
Figure. 20 to share crystal for Micro-processor

XIN

MICOM

S1A0903X01

Figure 20. Connection X'tal for Micro-processor

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S1A0903X01-Q0R0

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S1A0903X01-Q0R0