DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

DEFLECTION PROCESSOR

The S1D2511B01 is a monolithc integrated circuit
assembled in 32 pins shrunk dual in line plastic pack-
age. This IC controls all the functions related to the hori-
zontal and vertical deflection in multimodes or multi-
frequency computer display monitors.
The internal sync processor, combined with the very
powerful geometry correction block make the S1D2511B
suitable for very high performance monitors with very
few external components. The horizontal jitter level is
very low. It is particularly well suited for high-end 15

and 17

monitors.

FUNCTIONS

· Defiection Processor

· I

C BUS Control

· B+ Regulator

· Vertical Parabola Generator

· Horizontal and Vertical dynamic focus

FEATURES

(HORIZONTAL)

· Self-adaptative

· Dual PLL concept

· 150kHz maximum frequency

· X-RAY protection input

· I

C controls : Horizontal duty-cycle, H-position,free running

frequency, frequency generator for burn-in mode.

(VERTICAL)

· Vertical ramp generator

· 50 to 165Hz AGC loop

· Geometry tracking with V-POS & AMP

· I

C Controls :

V-AMP, V-POS, S-CORR, C-CORR

C GEOMETRY CORRECTIONS)

· Vertical parabola generator
(Pincushion-E/W, Keystone)

· Horizontal Dynamic Phase
(Side Pin balance & parallelogram)

· Horizontal and vertical dynamic focus
(Horizontal Focus Amplitude, Horizontal
Focus Symmetry, Vertical Focus Amplitude)

(GENERAL)

· Sync Processor

· 12V supply voltage

· Hor. & Vert, lock/unlock outputs

· Read/Write I

C interface

· Vertical moire

· B+ Regulator

-Internal PWM generator for B+ current mode

step-up converter.

- Switchable to step-down converter

- I

C adjustable B+ reference voltage

- Output pulses synchronized on horizontal

frequency

- Internal maximum current limitation.

ORDERING INFORMATION

Device

Package

Operating Temperature

S1D2511B01-A0B0

32-SDIP

C -- 70

32-SDIP-400

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

BLOCK DIAGRAM

PHASE/

FREQUENCY

COMPARATOR

H-PHASE(7 bits)

LOCK/UNLOCK

IDENTIFICATION

PHASE

COMPARATOR

VCO

SAFETY

PROCESSOR

PHASE

SHIFTER

H-DUTY

(5 bits)

B+

CONTROLLER

I C INTERFACE

GEOMETRY

TRACKING

VACCAP

COMP

PLL1F

HLOCKOUT

HFLY

PLL2C

HOUT

VOUT

REF

Forced

Freq.

2 bits

Free running

5 bits

HOUT

BUFFER

SYNC INPUT

SELECT

(1bit)

SYNC

PROCESSOR

REF

Vcc

XRAY

RESET

GENERATOR

MOIRE

CANCEL

5 BITS+ON/OFF

B+ ADJUST

7 bits

VSYNC

S AND C

CORRECTION

VERTICAL

OSCILLATOR

RAMP GENERATOR

6 bits

8 bits

VPOS

7bits

keyst
6 bits

PCC

7 bits

VAMP

6 bits

Amp & symmetry

2x5 bits

Spin Bal

6 bits

Key Bal

6 bits

VAMP

7 bits

H POSITION

B+ OUT

REGIN

BGND

HFOCUS

CAP

FOCUS

ISENSE

EWOUT

VCAP

H/HVIN

HREF

VSYNC

VCC

XRAY

VREF

VGND

SDA

SCL

GND

HGND

BREATH

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

PIN DESCRIPTION

Table 1. Pin Description

Pin Name

Description

H/HVIN

TTL compatible horizontal sync input(Separate or composite)

VSYNCIN

TTL compatible vertical sync input (for separated H&V)

HLOCKOUT

First PLL lock/unlock output (0V unlocked - 5V locked)

PLL2C

Second PLL loop filter

Horizontal oscillator capacitor

Horizontal oscillator resistor

PLL1F

First PLL loop filter

HPOSITION

Horizontal position filter(Capacitor to be connected to HGND)

HFOCUSCAP

Horizontal dynamic focus oscillator capacitor

FOCUSOUT

Mixed horizontal and vertical dynamic focus output

HGND

Horizontal Section Ground

HFLY

Horizontal Flyback Input (positive polarity)

HREF

Horizontal Section Reference Voltage (to be filtered)

COMP

B+ error amplifier output for frequency compensation and gain setting

REGIN

Regulation input of B+ control loop

ISENSE

Sensing of external B+ switching transistor current or switch for step-down converter

B+GND

Ground (related to B+ reference adjustment)

BREATH

DC breathing input control(Compensation of vertical amplitude against EHV variation)

VGND

Vertical section ground

VAGCCAP

Memory capacitor for automatic gain control loop in vertical ramp generator

VREF

Vertical section reference voltage (to be filtered)

VCAP

Vertical sawtooth generator capacitor

VOUT

Vertical ramp output (with frequency independant amplitude and S or C corrections if any).
It is mixed with vertical position voltage and vertical moire.

EWOUT

Pincushion-East/West correction parabola output

XRAY

X-RAY protection input (with internal latch function)

HOUT

Horizontal drive output (internal transistor, open collector)

GND

General ground (referenced to Vcc)

BOUT

B+ PWM regulator output

Vcc

Supply voltage (12V typ)

SCL

C clock input

SDA

C data input

Supply voltage (5V typ)

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

REFERENCE DATA

Table 2. Reference Data

Parameter

Value

Unit

Horizontal frequency

15 to 150

kHz

Autosynch frequency (for given R0 and C0)

1 to 4.5FO

Horizontal sync polarity input

YES

Polarity detection (on both horizontal and vertical section)

YES

TTL Composite synch

YES

Lock/Unlock identification (on both horizontal 1st PLL and vertical section)

YES

C control for H-Position

±10

XRay protection

YES

C horizontal duty cycle adjust

30 to 60

C free running frequency adjustment

0.8 to 1.3FO

Stand-by function

YES

Dual polarity H-Drive outputs

Supply voltage monitoring

YES

PLL1 inhibition possibility

Blanking output

Vertical frequency

35 to 200

Vertical autosync (for 150nF on Pin22 and 470nF on Pin20)

50 to 165

Vertical S-Correction

YES

Vertical C-Correction

YES

Vertical amplitude adjustment

YES

DC breathing control on Vertical amplitude

YES

East/West parabola output(also known as Pin cushion output)

YES

East/West correction amplitude adjustment

YES

Keystone adjustment

YES

Internal dynamic horizontal phase control

YES

Side pin balance amplitude adjustment

YES

Parallelogram adjustment

YES

Tracking of geometric corrections with vertical amplitude and position

YES

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

SYNC PROCESSOR

OPERATING CODNITIONS

Item

Symbol

Value

Unit

Supply voltage (pin 29)

13.5

Supply voltage (pin 32)

5.7

Maximum voltage on Pin 4

Pin 9
Pin 5
Pins 6,7,8,14,15,16,20,22
Pins 10,18,23,24,25,26,28
Pins 1,2,3,30,31

4.0
5.5
6.4
8.0

V
V
V

ESD susceptibillty
Human body model, 100pF discharge through
1.5K

EIAJ norm, 200pF discharge through 0

VESD

300

Storage temperature

Tstg

- 40, +150

Operating temperature

Topr

0, +70

Item

Symbol

Value

Unit

Junction temperature

+150

Junction-ambient thermal resistance

C/W

Table 3. Sync Processor Operating Codnitions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Horizontal sync input voltage

HsVR

Pin 1

Minimum horizontal input pulse duration

MinD

Pin 1

0.7

Maximum horizontal input signal duty cycle

Mduty

Pin 1

Vertical sync input voltage

VsVR

Pin 2

Minimum vertical sync pulse width

VSW

Pin 2

Maximum vertical sync input duty cycle

VSmD

Pin 2

Maximum vertical sync width on TTL H/V composite

VextM

Pin 1

750

Sink and source current

HLOCKOUT

Pin 3

250

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

ELECTRICAL CHARACTERISTICS

( V

= 5V, Tamb = 25

C )

C READ/WRITE

(See also I

C table control and I

C sub address control)

OPERATING CONDITIONS

Table 4. Sync Processor Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Horizontal and vertical input threshold
voltage (pin 1, 2)

VINTH

Low level

High level

2.2

0.8

V
V

Horizontal and vertical pull-up resister

RIN

pins 1,2

200

Falling and rising output CMOS buffer

TfrOut

pin 3, Cout = 20pF

200

Horizontal 1st PLL lock output status
(pin 3)

VHlock

Locked, I

LOCKOUT

= -250

Unlocked, I

LOCKOUT

= +250

0
5

0.5

V
V

Extracted vsync integration time (% of

(9)

) on H/V composite

VoutT

C0 = 820pF

Table 5. I

C Read/Write Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Input High Level Voltage

VinH

3.0

5.0

Input Low Level Voltage

VinL

1.5

SCL Clock frequency

fSCL

200

kHz

Hold time before a new transmission can start

tBUF

1.3

Hold time for Start conditions

tHDS

0.6

Set-Up time for Stop conditions

tSUP

0.6

The Low Period of SCL

tLOW

1.3

The High Period of SCL

tHIGH

0.6

Hold time data

tHDAT

0.3

Set-Up time data

tSUPDAT

0.25

Rise time of SCL

1.0

Fall time of SCL

3.0

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

C BUS Timing Requirement

ELECTRICAL CHARACTERISTICS

( V

= 5V, Tamb = 25

HORIZONTAL SECTION

OPERATING CONDITIONS

Table 6. I

C Read/Write Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

C PROCESSOR

Maximum clock frequency

Fscl

Pin 30

400

kHz

Low period of the SCL clock

Tlow

Pin 30

1.3

High period of the SCL clock

Thigh

Pin 30

0.6

SDA and SCL input threshold

Vinth

Pin 30, 31

2.2

Acknowledge output voltage on SDA input with
3mA

VACK

Pin 31

0.4

Table 7. Horizontal Section Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

VCO

Minimum oscillator resistor

0(Min.)

Pin 6

Minimum oscillator capacitor

0(Min.)

Pin 5

390

Maximum oscillator frequency

(Max.)

150

kHz

OUTPUT SECTION

Maximum input peak current

I12m

Pin 12

Horizontal drive output maximum
current

HOI

Pin26, sunk current

tBUF

Start:Clock High

Stop:Clock High

SDA

SCL

tLOW

tHDS

tSUPDAT

Data Change:Clock Low

tSUP

tHDAT

tHIGH

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

ELECTRICAL CHARACTERISTICS

( V

= 5V, Tamb = 25

Table 8. Horizontal Section Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY AND REFERENCE VOLTAGE

Supply voltage

Vcc

Pin 29

10.8

13.2

Supply voltage

Pin 32

4.5

5.5

Supply current

Pin 29

Supply current

Pin 32

Horizontal reference voltage

REF-H

Pin 13, I=-2mA

7.4

8.6

Vertical reference voltage

REF-V

Pin 21, I=-2mA

7.4

8.6

Max. sourced current on V

REF-H

Pin 13

Max. sourced current on V

REF-V

Pin 21

1st PLL SECTION

Polarity integration delay

HpoIT

Pin 1

0.75

VCO control voltage (pin 7)

VCO

REF-H

=8V

f0
fH (Max.)

1.3
6.2

V
V

VCO gain (pin 7 )

COG

=6.49K

, C

=820pF,

dF/dV=1/11R

kHz/V

Horizontal phase adjustment

(11)

Hph

% of horizontal period

Horizontal phase setting value(Pin 8)

(11)

Minimum current value
Typical value
Maximum value

Hphmin

Hphtyp

Hphmax

Sub-address 01
Byte x 1111111
Byte x 1000000
Byte x 0000000

2.6
3.2
3.8

V
V
V

PLL1 filter current charge

IPII1U

IPII1L

PLL1 is unlocked
PLL1 is locked

140

Free running frequency

=6.49K

=820pF,

=0.97/8R

140

Free running frequency thermal drift

(no drift on external components)

(7)

dF0/dT

-150

ppm/c

Free running frequency adjustment
Minimum value
Maximum value

(Min.)

(Max.)

Sub-address 02
Byte x x x 11111
Byte x x x 00000

0.8
1.3

F0
F0

PLL1 capture range

=6.49K

=820pF,

from f

+0.5KHz to 4.5Fo

fH(Min.)
fH(Max.)

100

23.5

KHz
KHz

Safe forced frequency
SF1 Byte 11 x x x x x x
SF2 Byte 10 x x x x x x

SFF

Sub-address 02

2F0
3F0

2ND PLL SECTION HORIZONTAL OUTPUT SECTION

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

Flyback input threshold
voltage (pin12)

FBth

0.65

0.75

Horizontal jitter

Hjit

ppm

Horizontal drive output duty-cycle

(pin 26)

(1, 2)

Low level
High level

HDmin
HDmax

Sub-address 00

Byte xxx11111

Byte xxx00000

(2)

30
60

%
%

X-RAY protection input threshold
voltage

XRAYth

Pin 25

(12)

Internal clamping levels on 2nd PLL loop
filter (pin 4 )

Vphi2

Low level
High level

1.6
3.7

V
V

Threshold voltage to stop H-out, V-out
when V

< VSCinh

VSCinh

Pin 29

7.5

Horizontal drive output (low level)

HDvd

Pin 26 I

OUT

=30mA

0.4

HORIZONTAL DYNAMIC FOCUS FUNCTION

Horizontal dynamic focus sawtooth
Minimum level
Maximum level

HDFst

Capacitor on HfocusCap
and C0=820pF,
TH=20

S, Pin 9

4.7

V
V

Horizontal dynamic focus sawtooth
Discharge width

HDFdis

Start by Hfly center

400

Bottom DC output level

HDFDC

LOAD

=10K

, pin 10

DC output voltage thermal drift

TDHDF

200

ppm/C

Horizontal dynamic focus amplitude
Min Byte xxx11111
Typ Byte xxx10000
Max Byte xxx00000

HDFamp

Sub-address 03, pin 10,
FH=50kHz, Keystone
Typ

1.5

Vpp
Vpp
Vpp

Horizontal dynamic focus keystone
Min A/B Byte xxx11111
Typ Byte xxx10000
Max Byte xxx00000

HDFkeyst

Sub-address 04,
FH = 50kHz, Typ amp
B/A
A/B
A/B

2.2

3.5
1.0
3.5

VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA)

Vertical dynamic focus parabola (added to
horizontal one) amplitude with VOUT and
VPOS typical
Min. Byte 000000
Typ. Byte 100000
Max. Byte 111111

AMPVDF

Sub-address 0F

0.5

Vpp
Vpp
Vpp

Parabola amplitude function of VAMP
(tracking between VAMP and VDF) with

VPOS typ. (see figure 1)

(3)

VDFAMP

Sub-address 05
Byte 10000000
Byte 11000000
Byte 11111111

0.6

1.5

Vpp
Vpp
Vpp

Parabola assymetry function of VPOS
control (tracking between VPOS and VDF)
with VAMP Max.

VHDFKeyt

Sub-address 06
Byte x0000000
Byte x1111111

0.52
0.52

Vpp
Vpp

Table 8. Horizontal Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

VERTICAL SECTION

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

= 12V, Tamb = 25

Table 9. Vertical Section Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

OUTPUTS SECTION

Maximum EW output voltage

VEWM

Pin 24

6.5

Minimum EW output voltage

VEWm

Pin 24

1.8

Minimum load for less than 1% vertical amplitude drift

LOAD

Pin 20

Table 10. Vertical Section Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

VERTICAL RAMP SECTION

Voltage at ramp bottom point

VRB

REF-V

=8V, pin 22

Voltage at ramp top point (with sync) V

REF-V

VRT

REF-V

=8V, Pin 22

Voltage at ramp top point (without sync)

VRTF

Pin 22

VRT-01

Vertical sawtooth discharge time duration (pin 22)

VSTD

With 150nF cap

Vertical free running frequency

see

(4, 5)

VFRF

OSC(pin22)

=150nF

measured on pin 22

100

AUTO -SYNC frequency

(13)

ASFR

=150nF

See

(6)

165

Ramp amplitude drift versus frequency at
Maximum vertical amplitude

RAFD

=150nF

50Hz<f and f<165Hz

200

TBD

ppm/

Ramp linearity on pin 22 (

I22/I22)

see

(4, 5)

RIin

=4.3v,

2.5<V

<4.5V

0.5

Vertical position adjustment voltage
(pin 23 - VOUT centering)

Vpos

Sub address 06
Byte x0000000
Byte x1000000
Byte x1111111

3.65

3.2
3.5
3.8

3.3

V
V
V

Vertical output voltage
(peak-to-peak on pin 23 )

VOR

Sub address 05
Byte x0000000
Byte x1000000
Byte x1111111

3.5

2.25

3.75

2.5

V
V
V

Vertical output Maximum current(Pin 23)

VOI

±5

Max vertical S-correction amplitude

(14)

XOXXXXXX inhibits S-C

ORR

X1111111 gives max S-C

ORR

dVS

Sub address 07

V/Vpp at TV/4

V/Vpp at 3TV/4

-4

%
%

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

Vertical C-Corr amplitude
XOXXXXXX inhibits C-corr

Ccorr

Sub address 08

V/Vpp at TV/2

Byte X1000000
Byte X1100000
Byte X1111111

-3

0
3

%
%
%

EAST/WEST FUNCTION

DC output voltage with typ Vpos, keystone,
corner and corner balance inhibited

pin 24,
see figure 2

2.5

DC output voltage thermal drift

TDEW

see note 7

100

ppm/

Parabola amplitude with Vamp Max.
V-Pos typ, keystone ilhibited

EWpara

Sub address 0A
Byte 1111111
Byte 1010000
Byte 1000000

2.5

1.25

V
V
V

Parabola amplitude function of V-AMP control
(tracking between V-AMP and E/W) with typ Vpos

ketstone, EW Typ amplitude

(8)

EWtrack

Sub address 05
Byte 1000000
Byte 1100000
Byte 1111111

0.45

0.8

1.25

V
V
V

Keystone adjustment capability with typ Vpos,
EW typ amplitude and vertical amplitude max,

(8)

A/B Ratio(see figure 2)
B/A Ratio

KeyAdj

Sub address 09

Byte 1x000000
Byte 1x111111

1
1

Vpp
Vpp

Intrinsic keystone function of V-POS control
(tracking between V-pos and EW) Max amplitude

and vertical amplitude max.

(10)

A/B Ratio
B/A Ratio

Key-
Track

Sub address 09

Byte x0000000
Byte x1111111

0.52
0.52

INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION

Side pin balance parabola amplitude (figure3) with
Vamp max, V-POS typ and parallelogram inhibited

(8,9)

SPBpara

Sub address 0D
Byte x1111111
Byte x0000000

+1.4

-1.4

%TH
%TH

Side pin balance parabola amplitude function of
Vamp control (tracking between Vamp and SPB)
with SPB max, V-POS typ and parallelogram

inhibited

(8,9)

SPBtrack

Sub address 05
Byte 10000000
Byte 11000000
Byte 11111111

0.5
0.9
1.4

%TH
%TH
%TH

Parallelogram adjustment capability with Vamp

max, V-POS typ and SPB max

(8,9)

A/B Ratio
B/A Ratio

ParAdj

Sub address 0E

Byte x1111111
Byte x1000000

+1.4

-1.4

%TH
%TH

Intrinsic parallelogram function of Vpos control
(tracking between V-pos and DHPC) with Vamp

max, SPB max and parallelogram inhibited

(8, 9)

A/B Ratio
B/A Ratio

Partrack

Sub address 06

Byte x0000000
Byte x1111111

0.52
0.52

Table 10. Vertical Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

B+ SECTION

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

= 12V, Tamp = 25

C )

VERTICAL MOIRE

Vertical moire (measured on VOUTDC) pin 23

VMOIRE

Sub address 0C
Byte 01x11111

BREATHING COMPENSATION

DC breathing control range

(15)

BRRANG

V18

Vertical output variation versus DC breathing con-
trol (Pin 23)

BRADj

V18

REF-V

V18=4V

-10

%
%

Table 11. B+ Section

Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Minimum feedback resistor

FeedRes

Resistor between pins 15 and 14

Table 12. B+ Section Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Error amplifier open loop gain

OLG

At low frequency

(10)

Unity gain band width

UGBW

see

(7)

MHz

Regulation input bias current

IRI

Current sourced by pin 15
(PNP base)

0.2

Maximum guaranted error amplifier
output current

EAOI

Current sourced by pin 14
Current sunk by pin 14

0.5

mA
mA

Current sense input voltage gain

CSG

Pin 16

Max current sense input thres hold
voltage

MCEth

Pin 16

1.2

Current sense input bias current

ISI

Current sunk by pin 16
(NPN base )

Maxmum external power transistor on
time

Tonmax

% of H-period

@ f0=27kHz

(16)

100

B+ output low level saturation voltage

B+OSV

with I

=10mA

0.25

Internal reference voltage

REF

On error amp
(+) input for subaddress 0B
byte 1000000

4.8

Table 10. Vertical Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

NOTES;

1.Duty cycle is the ratio of power transistor OFF time period. Power transistor is OFF when output transistor is
OFF.
2.Initial condition for safe operation start up.
3.S and C correction are inhibited so the output sawtooth has a linear shape.
4.With register 07 at byte x0xxxxxx (s-correction control is inhibited) then the S correction is inhibited, consequently
the sawtooth has a linear shape.
5.With register 08 at byte x0xxxxxx (C-Correction control is inhibited) then the C correction is inhibited,
consequently the sawtooth has a linear shape.
6.It is frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value
on pin 22, and with a constant ramp amplitude.
7.These parameters are not tested on each unit. They are measured during out internal qualification.
8.Refers to notes 4 & 5 from last section.
9.TH is the Horizontal period.
10.These parameters are not tested on each unit. They are measured during our internal qualification procedure
which incudes characterization on batches comming from corners of our processes and also temperature char
acterization.
11. See Figure 11 for explanation of reference phase.
12. See Figure 15.
13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single
capacitor value on Pin 22 and with a constant ramp amplitude.
14. TV is the vertical period.
15. When not used the DC breathing control pin must be connected to 12V.
16. The external power transistor is OFF during 400ns of the HFOCUSCAP discharge.

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

C BUS ADDRESS TABLE

Slave Address (8C): Write Mode

Sub Address Definition

Slave Address (8D): Read Mode

No Sub Address needed

Horizontal drive selection/horizontal duty cycle

Horizontal position

Forced frequcny /free running frequency

Synchro priority / horizontal focus amplitude

Refresh /horizontal focus keystone

Vertical ramp amplitude

Vertical position adjustment

S Correction

C Correction

E/W keystone

E/W amplitude

B+ reference adjustment

Vertical moire

Side pin balance

Parallelogram

Vertical dynamic focus amplitude

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

C BUS ADDRESS TABLE (continued)

WRITE MODE

HDrive

0, off

[1],on

Horizontal duty cycle

[0]

Xray

1,reset

[0]

Horizontal phase adjustment

[1]

[0]

Forced frequency

Free running frequency

1,on,

[0],off

1,F0x2

[0],F0x3

[0]

Sync

0, comp

[1], sep

Horizontal focus amplitude

[1]

[0]

Detect

refresh

[0], off

Horizontal focus keystone

[1]

[0]

Vramp

0, off

[1], on

Vertical ramp amplitude adjustment

[1]

[0]

Vertical position adjustment

[1]

[0]

S Select

1, on

[0]

S Correction

[1]

[0]

C Select

1, on

[0]

C Correction

[1]

[0]

EW key

0, off

[1]

East/West keystone

[1]

[0]

EW sel

0, off

[1]

East/West amplitude

[1]

[0]

Test H

1, on

[0], off

B+ reference adjustment

[1]

[0]

Test V

1, on

[0], off

Moire 1, on

[0]

Vertical Moire

[0]

SPB sel

0, off

[1]

Side pin balance

[1]

[0]

Parallelo

0, off

[1]

Parallelogrm

[1]

[0]

Vertical dynamic focus amplitude

[1]

[0]

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

[ ] initlal value

OPERATING DESCRIPTION

GENERAL CONSIDERATIONS

Power Supply

The typical values of the power supply voltages Vcc and V

are respectively 12V and 5V. Perfect operation is

obtained if Vcc and V

are maintened in the limits: 10.8 to 13.2V and 4.5 to 5.5V.

In order to avoid erratic operation of the circuit during transient phase of Vcc switching on, or switching off, the
value of Vcc is monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V typically.
In the same manner, V

is monitored and internal set-up is made until V

reaches 4V (see I

C control table for

power on reset).
In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage
references (the unigue typical value of which is 8V). Two of these voltage references are externally accessible, one
for the vertical part and on one for the horizontal one. If needed, these voltage references can be used (until Iload
is less than 5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor
connected to ground, in order to minimize the noise and consequently the

jitter

on vertical and horizontal output

signals.

C Control

KB2511 belongs to the I

C controlled device family, instead of being controlled by DC voltage on dedicated control

pins, each adjustment can be realized through the I

C interface. The I

C bus is a serial bus with a clock and a data

input. The general function and the bus protocol are specified in the philips-bus data sheets.
The interface (data and clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V
(when V

is 5V). Spikes of up to 500ns are filtered by an integrator and maximum clock speed is limited to

400kHz.
The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply informa-
tion (1byte) to the micro-processor.
The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to trans-
mit the IC-address (hexa 8C for write, 8D for read).

Write Mode

In write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect)
and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the
third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in
the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data
bytes without sending the IC address or subaddress. It can be useful so as to reinitialize the whole controls very
quickly (flash manner). This procedure can be finished by a stop condition.
The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the
dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+
reference adjustment.
17 bits are also dedicated to several controls (ON/OFF, horizontal forced frequency, sync priority, detection
refresh and Xray reset).

READ MODE

Hlock

0, on

[1], no

Vlock

0, on

[1], no

Xray

1,on

[0],off

Polarity detection

Synchro detection

H/V pol

[1],negative

V pol

[1], negative

Vext det

[0],no det

H/V det

[0],no det

V det

[0], nodet

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

Read Mode

During read mode the second byte transmits the reply information.
The reply byte contains horizontal and vertical lock/unlock status, Xray activated or not, the horizontal and vertical
polarity detection. It also contains synchro detection status that is useful for

P to assign sync priority.

A stop condition always stops all activities of the bus decoder and switches the data and the clock line (SDA and
SCL) to high impedance.

See I

C subaddress and control tables.

Sync processor

The internal sync processor allows the S1D2511B01 to accept any kind of input synchro signals:

- separated horizontal & vertical TTL-compatible sync signals,
- composite horizontal & vertical TTL-compatible sync signals.

Sync identification Status

The MCU can read (address read mode : 8D) the status register via the I

C bus, and then select the sync priority

depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and(when 12V is sup-
plied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if only
5V is supplied.

In order to choose the right sync priority the MCU may proceed as follows(see I

C Address Table):

- refresh the status register,
- wait at least for 20ms(MAX. vertical period),
- read this status register,

Sync priotity choice should be:

Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present
and that no sync change occured.
Sync processor is also giving sync polarity information.

IC status

The IC can inform the MCU about the 1st horizontal PLL and vertical section status, and about the Xary protection
(activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc supply or directly

resetting it via the I

C interface.

Sync Inputs

Both H/HVin and Vsyncin inputs are TTL compatible trigger with hysterisis to avoid erratic detection.
Both inputs include a pull up register connected to V

Sync Processor Output

The sync processr indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync.
HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of
the status regiser is set to 0. This information is mainly used to trigger safety procedures(like reducing B+ value) as
soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure for

Vext det

H/V det

V det

Sync priority subaddress 03 (D8)

Comment sync type

Yes

Separated H & V

Yes

Composite TTL H & V

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

free running frequency(fo) adjustment.

Sending the desired fo on the sync input and progressively decreasing the free running frequently I

C register

value(address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free run-
ning frequency this way allows to fully exploit the S1D2511B01 horizontal frequency range.

HORIZONTAL PART

Internal input conditions

Horizontal part is internally fed by synchro processor with a digital signal corresponding to horizontal synchro
pulses or to TTL composite input.
concerning the duty cycle of the input signal, the following signals (positive or negative)may be applied to the
circuit.
Using internal integration, both signals are recognized on condition that Z/T < 25%, synchronisation occurs on the
leading edge of the internal sync signal. The minimum value of Z is 0.7

Figure 6.

An other integration is able to extract vertical pulse of composite synchro if duty cycle is more than 25% (typically

d = 35%)

(7)

Figure 7.

The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input
which is intolerent to wrong or missing pulse.

PLL1

The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO).
The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector
avoids locking on false frequencies. It is followed by a charge pump, composed of two current sources sunk and
sourced (I = 1mA typ. when locked, I = 140mA when unlocked). This difference between lock/unlock permits a
smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system
when PLL1 is locked avoiding horizontal too fast frequency change.
The dynamic bahaviour of the PLL is fixed by an external filter which integrates the current of the charge pump.
A CRC filter is generally used (see figure 8 )

TRAMEXT

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

Figure 8.

PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong
pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump
and the filter (see figure 9 ).
The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the
capacitor, by a current proportionnal to the current in the resistor. Typical thresholds of sawtooth are 1.6V and
6.4V.

Figure 9. Block Diagram

PLL1F

1.8K

4.7uF

1uF

INPUT

INTERFACE

COMP1

CHARGE

PUMP

PLL

INHIBITION

VCO

LOCKDET

PHASE
ADJUST

OSC

HPOS

Adj.

Low

High

TRAMEXT

HSYNC

H-LOCKCAP

LOCK/UNLOCK

STATUS

TRAMEXT

SMFE

MODE

PLL1F R0

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Figure 10. Details of VCO

The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 10). The theorical
frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to
clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible
to adjust free running frequency through I

C. This adjustment can be made automatically on the manufacturing line

without manual operation by using hlock/unlodk information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is
the free running frequency at power on reset).
The sync frequency has to be always higher than the free running frequency. As an example for a synchro range
from 24kHz to 100kHz, the suggested free running frequency is 23kHz.
An other feature is the capability for MCU to force horizontal frequency throw I

C to 2xF0 or 3xF0 (for burn in mode

or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is
forced to 2.66V for 2xF0 or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference
obtained by comparism between the sawtooth of the VCO and an internal DC voltage I

C adjustable between

2.65V and 3.75V (corresponding to

10%) (see figure 11)

Figure 11. PLL1 Timing Diagram

4 I

6.4V

FLIP

FLOP

Loop
Filter

(0.80<a<1.30)

C Free running

(1.3V < V

< 6V)

1.6V

6.4V

1.6V

0.84T

Adjustment

H Osc
Sawtooth

7/8T

1/8T

6.4V
2.65V < Vb < 3.75V

1.6V

Phase REF1

H Synchro

Phase REF1 is obtained by compari-
sion between the sawtooth and a DC
voltage adjustable between 2.6V and
3.8V. The PLL1 ensures the exact
coindidence between the signals
phase REF and HSYNS. A

/10

phase adjustment is possible

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

The S1D2511B01 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked
or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync proces-
sor). The block function is described in figure 12.
When PLL1 is unlocked, It forces Hlockout to leave high.
The lock/unlock information is also available throw I

C read.

PLL2

The PLL2 ensures a constant position of the shaped flyback signal in comparism with the sawtooth of the VCO
(figure 12).
The phase comparator of PLL2 (phase type comparator) is followed by a charge pump(typical output cur-
rent:0.5mA).
The flyback input is composed of an NPN transistor. This input must be current driven. The maximum
recommanded input current is 5mA (see figure 13).
The dury cycle is adjustable through I

C from 30% to 60%. For startup safe operation, initial duty cycle (after power

on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor. The
maximum storage time(Ts MAX.) is (0.38T

-T

FLY

/2). Typically, T

FLY

/TH is around 20% which means that Ts max

is around 28% of T

Figure 12. PLL2 Timing Diagram

Figure 13. Flyback Input Electrical Diagram

H Osc
Sawtooth

7/8T

1/8T

6.4V

3.7V

1.6V

Shaped Flyback

H drive

Flyback

Internally

Duty Cycle

HFLY

400

20K

GND 0V

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Output Section

The H-drive signal is transmitted to the output through a shaping block ensuring TS and I

C adjustable duty cycle.

In order to secure scanning power part operation, the output is inhibited in the following circumstances:
- Vcc too low
- Xray protection activated
- During horizontal flyback
- H Drive I

C bit control is off.

The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see figure 14).

Figure 14.

The output NPN is in off-state when the power scanning transistor is also in off-state.
The maximum output current is 30mA, and the corresponding voltage drop of the output V

CEsat

is 0.4V typically.

It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has
to be designed between the circuit and the power transistor which can be of bipolar or MOS type.

X-RAY protection

The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It
inhibits the H-Drive and B+ outputs.
This protection is latched; It may be reset either by Vcc switch off or by I

C(see figure 15).

Horizontal and vertical dynamic focus

The S1D2511B01 delivers and horizontal parabola added on a vertical parabola wavefrom on pin 10. This horizon-
tal parabola is performed from a sawtooth in phase with flyback pulse middle. This sawtooth is present on pin 9
where the horizontal focus capacitor is the same as C0 to obtain a controlled amplitude (from 2 to 4.7V typically).
Symmetry (keystone) and amplitude are I

C adjustable (see figure 16). Vertical dynamic focus is tracked with

VPOS and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal has
to be connected to the CRT focusing grids.

26 H-DRIVE

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

VERTICAL PART

Geometric Corrections

The principle is represented in figure 17.

Figure 17. Geometric Correcitions Principle

Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal
phase control correction, and vertical dynamic focus correction.
The base of the parabola generator is an analog multiplier, the output current of which is equal to:

I = k

( V

OUT

- V

DCMID

)

Where Vout is the vertical output ramp(typically between 2 and 5V) and V

DCMID

is 3.5V(for V

REF-V

=8V). The VOUT

sawtooth is typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by

0.3V.

In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry
tracking.
Due to large output stages voltage range (E/W, FOCUS), the combination of tracking function with maximum verti-
cal amplitude max or min vertical position and maximum gain on the DAC control may lead to the output stages
saturation. This must be avoided by limiting the output voltage by appropriate I

C registers values.

For E/W part and Dynamic Horizontal phase control part, a sawtooth shaped differential current in the following
form is generated:

= k

( V

OUT

- V

DCMID

)

Then

I and

are added together and converted into voltage for the E/W part.

Each of the two E/W components or the two Dynamic horizontal phase control ones may be inhibited by their own
I

C select bit.

The E/W parabola is available on pin 24 by the way of an emitter follower which has to be biased by an external
resistor (10K

). It can be DC coupled with external circuitry.

Vertical dynamic focus is combined with horizontal one on output pin 10. Dynamic horizontal phase control current
drives internally the H-position, moving the Hfly position on the horizontal sawtooth in the

1.4% Th both on side

pin balance and parallelogrm.

Vertical
Ramp V

OUT

DCMID

(3.5V)

AMP

EW amp

keystone

sidepin amp

Parallelogram

To horizontal
phase

Sidepin balance
output current

EW output

Dynamic focus

Parabola

Generator

V.Focus

Horizontal

Dynamic Focus

DCMID

(3.5V)

DCMID

(3.5V)

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

EWOUT = 2.5V + K1 ( V

OUT

- V

DCMID

)

+ K2 ( V

OUT

- V

DCMID

)

K1 is adjustable by EW amplitude I

C register

K2 is adjustable by keystone I

C register

Dynamic horizontal phase control

IOUT = K3 ( V

OUT

- V

DCMID

)

+ K4 ( V

OUT

- V

DCMID

)

K4 is adjustable by side pin balance I

C register

K3 is adjustable by parallelogram I

C register.

Function

When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an
external capacitor, C

OSC

= 150nF, the typical free running frequency is 100Hz.

Typical free running frequency can be calculated by:

A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can syn-
chronise the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor connected on
pin 22. A capacitor in the range [150nF, 220nF]

5% is recommanded for application in the following range: 50Hz

to 165Hz.
Typical maximum and minimum frequency, at 25

C and without any correction (S correction or C correction), can

be calculated by:

(Max.)

= 2.5 x f

and f

(Min.)

= 0.33 x f

If S or C corrections are applied, these values are slighty affected.
If a synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more con-
stant. An internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp pin
22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance ampli-
fier generates the charge current of the capacitor. The ramp amplitude becomes again constant.
The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.
It is recommanded to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.
Good stability of the internal closed loop is reached by a 470nF

5% capacitor value on pin 20 (VAGC)

(Hz)= 1.5

-5

OSC

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Figure 18. AGC Loop Block Diagram

C Control Adjustments

Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are
generated internally. Their amplitude are adjustable by their respective I

C register. They can also be inhibited by

their select bit. Endly, the amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude
control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this
stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I

C register

(vertical position). Its value is VPOS = 7/16

REF

300mV.

Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from
V

REF-V

, the bias voltage sent to the non-inverting input of booster should also derive from V

REF-V

to optimize the

accuracy(see Application Diagram).

Basic Equations

In first approximation, the amplitude of the ramp on pin 23 (Vout) is:
V

OUT

- VPOS = ( V

OSC

- V

DCMID

)

( 1 + 0.25 (V

AMP

) )

with:
- V

DCMID

= 7/16

REF

( typically 3.5V, the middle value of the ramp on pin 22)

- V

OSC

= V22 ( ramp with fixed amplitude)

- VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum
- VPOS is calculated by : VPOS = V

DCMID

+ 0.3Vp with Vp equals -1 for minimum vertical position register value

and +1 for maximum

The current available on Pin 22 is :

SYNCHRO

OSCILLATOR

Switch

Dlech

V-SYNC

POLARITY

DISCH.

OSC

CAP

CHARGE CURRENT

TRANSCONDUCTANCE

AMPLIFIER

REF

SAMP
CAP

SAMPLING

S CORRECTION

VS_AMP
SUB07/8bits

COR-C
SUB08/6bits

C CORRECTION

Vlow

VERT_AMP
SUB05/7BITS
VMOIRE
SUB0C/5BITS
VOSITION
SUB06/7BITS

VOUT

BREATH

OSC

REF

OSC

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2511B01

with C

OSC

: capacitor connected on pin 22

f: synchronisation frequency.

Vertical Moire

By using the vertical moire, VPOS can be modulated from to frame. This function is intended to cancel the fringes
which appear when line to line interval is very close to the CRT vertical pitch. The amplitude pf the modulation is
controlled by register VMOIRE on sub-off via the control bit D7.

DC/DC CONVERTER PART

This unit controls the switch-mode DC/DC con-verter. It converts a DC constant voltage into the B+ voltage

(roughly proportional to the horizontal frequency)necessary for the horizontal scanning. This DC/DC converter can

be configured either in step-up or step-down mode. In both cases it oper-ates very similarly to the well known

UC3842.

Step-up Mode

Operating Description

- The powerMOSisswitched-onduringthe flyback (at the beginning of the positive slope of the horizontal focus

sawtooth).

- The power MOS is switched-off when its current reachesa predeterminedvalue. Forthispurpose, a sense resistor

is inserted in its source. The voltage on this resistor is sent to Pin16 (I

SENSE

- The feedback(coming either from the EHV or from the flyback) is divided to a voltage close to 4.8V and com-

pared pared to the internal 4.8V reference(I

VREF

). The difference is amplified by an error amplifier, the output of

which controls the power MOS switch-off current.

Main Features

- Switching synchronized on the horizontal fre-quency,

- B+ voltage always higher than the DC source, - Current limited on a pulse-by-pulse basis.

Step-down Mode

In step-down mode, the Isense information is not used any more and therefore not sent to the Pin16. This mode is

selected by connecting this Pin16 to a DC voltage higher than 6V (for example V

REF-V

Operating Description

- The powerMOSis switched-onas for thestep-up mode.

- The feedbackto the error amplifier is done as for the step-up mode.

- The power MOS is switched-off when the HFOCUSCAP voltage get higher than the error amplifier output voltage

Main Features

- Switching synchronized on the horizontal fre-quency,

- B+ voltage always lower than the DC source,

- No current limitation.

S1D2511B01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

APPLICATION CIRCUIT

MC14528

VCC=12V

50K

6.8K

12V

HSYNC

VSYNC

22nF 100V

820pF 50V

1% P

1.8K

4.7uF 50V

10nF 100V MP

0.1uF

22K

100uF

1uF

820pF

10K

AFC

4.7uF

0.1uF

33K

3.3K

50K

22K

100

SDA

SCL

100uF

10K

HOUT

22K

10K

AFC

150nF 100V

1% P

470nF 63V P

0.1uF

10K

47uF
50V

50K

SCLK

SCL

SDA

74HCT125

SDAT

ACK

100K

47pF

HOUT

0.1uF

100uF

33pF

10K

AFC

47pF

100K

SDA

VCC

B+OUT

GND

XRAY

EWOUT

VOUT

VSCAP

H_OUT

VAGCCAP

BREATH

V_REF

VGND

COMP

VSYNC_IN

PLL2C

PLL1F

HPOSITION

HFOCUSCAP

H_FOCUS

HGND

HFLY

H_REF

REGIN

SCL

HSYNC_IN

I_SENSE

B+GND

H_LOCKOUT

KB2511B

S1D2511B

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S1D2511C01

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S1D2511C01