S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

DEFLECTION PROCESSOR

The S1D2512X01 is a monolithic integrated circuit assembled in 32 pins
shrunk dual in line plastic package. This IC controls all the functions
related to the horizontal and vertical deflection in multi modes or multi-
frequency computer display monitors.

The internal sync processor, combined with the very powerful geometry
correction block make the S1D2512X01 suitable for very high
performance monitors with very few external components. The horizontal
jitter level is very low. It is particularly well suited for high-end 17

and

monitors.

FUNCTIONS

Deflection processor

C bus control

B+ regulator

Vertical parabola generator

Vertical dynamic focus

FEATURES

(HORIZONTAL)

Self-adaptive

Dual PLL concept

150kHz maximum frequency

X-RAY protection input

C controls: Horizontal duty-cycle, H-position, free

running frequency, frequency generator for burn-in
mode.

(VERTICAL)

Vertical ramp generator

50 to 185Hz AGC loop

Geometry tracking with V-POS & V-AMP

C Controls: V-AMP, V-POS, S-CORR, C-CORR

DC breathing compensation

C GEOMETRY CORRECTIONS)

Vertical parabola generator
(pincushion-E/W, keystone, corner)

32-SDIP-400

Horizontal dynamic phase (side pin balance &
parallelogram)

Vertical dynamic focus (Vertical focus amplitude)

(GENERAL)

Sync processor

12V supply voltage

Hor. & Vert. lock/unlock outputs

Read/Write I

C interface

Horizontal and vertical moire

B+ Regulator
- Internal PWM generator for B+ current mode
step-up converter.

- I

C adjustable B+ reference voltage

- Output pulses synchronized on horizontal

frequency

- Internal maximum current limitation.

- Soft start

Compared with the S1D2511B, S1D2512X HAS:
- Corner correction
- Horizontal moire
- B+ soft start
- Increased max. Vertical frequency
- No horizontal focus
- No step down option for DC/DC converter.

ORDERING INFORMATION

Device

Package

Operating Temperature

S1D2512X01-A0B0

32-SDIP-400

C -- 70

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

BLOCK DIAGRAM

PHASE/

FREQUENCY

COMPARATOR

H-PHASE(7 bits)

LOCK/UNLOCK

IDENTIFICATION

PHASE

COMPARATOR

VCO

SAFETY

PROCESSOR

PHASE

SHIFTER

H-DUTY

(5 bits)

B+

CONTROLLER

I C INTERFACE

GEOMETRY

TRACKING

VACCAP

COMP

PLL1F

HLOCKOUT

HFLY

PLL2C

HOUT

VOUT

V R

Forced

Freq.
2 bits

Free running

5 bits

HOUT

BUFFER

SYNC INPUT

SELECT

(1bit)

SYNC

PROCESSOR

V R

Vcc
XRAY

RESET

GENERATOR

MOIRE

CANCEL

5 BITS+ON/OFF

B+ ADJUST

7 bits

VSYNC

S AND C

CORRECTION

VERTICAL

OSCILLATOR

RAMP GENERATOR

6 bits

8 bits

VPOS

7bits

keyst
6 bits

7 bits

AMPVDF

6 bits

Spin Bal

6 bits

Key Bal

6 bits

VAMP

7 bits

H POSITION

B+ OUT

REGIN

BGND

HMOIRE

FOCUS

ISENSE

EWOUT

VCAP

H/HVIN

HREF

VSYNCIN

VCC

XRAY

VREF

VGND

SDA

SCL

GND

HGND

BREATH

Horizontal

Moire Cancel

5 bits + on/off

HSYNC

Corner

7 bits

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

PIN DESCRIPTION

Table 1. Pin Description

Pin Name

Description

H/HVIN

TTL compatible horizontal sync input (separate or composite)

VSYNCIN

TTL compatible vertical sync input (for separated H&V)

HLOCKOUT

First PLL lock/unlock output (0V unlocked - 5V locked)

PLL2C

Second PLL loop filter

Horizontal oscillator capacitor

Horizontal oscillator resistor

PLL1F

First PLL loop filter

HPOSITION

Horizontal position filter (capacitor to be connected to HGND)

HMOIRE

Horizontal moire output (to be connected to PLL2 C through a resistor divider)

FOCUSOUT

Vertical dynamic focus output

HGND

Horizontal section ground

HFLY

Horizontal Flyback input (positive polarity)

HREF

Horizontal section reference voltage (to be filtered)

COMP

B+ error amplifier output for frequency compensation and gain setting

REGIN

Regulation input of B+ control loop

ISENSE

Sensing of external B+ switching transistor current

B+GND

Ground (related to B+ reference adjustment)

BREATH

DC breathing input control (compensation of vertical amplitude against EHV
variation)

VGND

Vertical section ground

VAGCCAP

Memory capacitor for automatic gain control loop in vertical ramp generator

VREF

Vertical section reference voltage (to be filtered)

VCAP

Vertical sawtooth generator capacitor

VOUT

Vertical ramp output

(with frequency independent amplitude and S or C corrections if any).

It is mixed with vertical position voltage and vertical moire.

EWOUT

Pincushion-East/West correction parabola output

XRAY

X-RAY protection input (with internal latch function)

HOUT

Horizontal drive output (internal transistor, open collector)

GND

General ground (referenced to Vcc)

BOUT

B+ PWM regulator output

Vcc

Supply voltage (12V typ)

SCL

C clock input

SDA

C data input

Supply voltage (5V typ)

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

REFERENCE DATA

Table 2. Reference Data

Parameter

Value

Unit

Horizontal frequency

15 to 150

kHz

Autosynch frequency (for given R0 and C0)

1 to 4.5FO

Horizontal sync polarity input

Yes

Polarity detection (on both horizontal and vertical section)

Yes

TTL composite sync

Yes

Lock/unlock identification (on both horizontal 1st PLL and vertical section)

Yes

C control for H-position

±10

XRAY protection

Yes

C horizontal duty cycle adjust

30 to 60

C free running frequency adjustment

0.8 to 1.3FO

Stand-by function

Yes

Dual polarity H-drive outputs

Supply voltage monitoring

Yes

PLL1 inhibition possibility

Blanking output

Vertical frequency

35 to 200

Vertical Autosync (for 150nf on pin22 and 470nf on pin20)

50 to 185

Vertical S correction

Yes

Vertical C correction

Yes

Vertical amplitude adjustment

Yes

DC breathing control on vertical amplitude

Yes

Corner correction

Yes

East/West parabola output (also known as pin cushion output)

Yes

East/West correction amplitude adjustment

Yes

Keystone adjustment

Yes

Vertical position adjustment

Yes

Internal dynamic horizontal phase control

Yes

Side pin balance amplitude adjustment

Yes

Parallelogram adjustment

Yes

Tracking of geometric corrections with vertical amplitude and position

Yes

Reference voltage (both on horizontal and vertical)

Yes

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

SYNC PROCESSOR

OPERATING CODNITIONS(V

= 5V, Tamb = 25

Table 3. Absolute Maximum Ratings

Item

Symbol

Value

Unit

Supply voltage (Pin 29)

13.5

Supply voltage (Pin 32)

5.7

Maximum voltage on Pin 4

Pin 5

Pin 6, 7, 8, 14, 15, 16, 20, 22

Pin 9, 10, 18, 23, 24, 25, 26, 28

Pin 1, 2, 3, 30, 31

4.0

6.4

8.0

ESD susceptibility

Human body model, 100pF discharge through 1.5K

EIAJ norm, 200pF discharge through 0

VESD

300

Storage temperature

Tstg

- 40, +150

Operating temperature

Topr

0, +70

Table 4. Thermal Characteristics

Item

Symbol

Value

Unit

Junction temperature

+150

Junction-ambient thermal resistance

C/W

Table 5. Sync Processor Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Horizontal sync input voltage

HsVR

Pin 1

Minimum horizontal input pulse duration

MinD

Pin 1

0.7

Maximum horizontal input signal duty cycle

Mduty

Pin 1

Vertical sync input voltage

VsVR

Pin 2

Minimum vertical sync pulse width

VSW

Pin 2

Maximum vertical sync input duty cycle

VSmD

Pin 2

Maximum vertical sync width on TTL H/V composite

VextM

Pin 1

750

Sink and source current

HLOCKOUT

Pin 3

250

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

ELECTRICAL CHARACTERISTICS

= 5V, Tamb = 25

C READ/WRITE

(See also I

C table control and I

C sub address control)

OPERATING CONDITIONS (V

= 5V, Tamb = 25

Table 6. Sync Processor Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Horizontal and vertical input threshold
voltage (pin 1, 2)

VINTH

Low level

High level

2.2

0.8

Horizontal and vertical pull-up resister

RIN

Pins 1,2

200

Falling and rising output CMOS buffer

TfrOut

Pin 3, Cout = 20pF

200

Horizontal 1st PLL lock output status

(pin 3)

VHlock

Locked, I

LOCKOUT

= -250

Unlocked, I

LOCKOUT

= +250

4.4

0.5

Extracted Vsync integration time (% of

(see 9)

) on H/V composite

VoutT

C0 = 820pF

Table 7. I

C Read/Write Operating Conditions

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Input high level voltage

VinH

3.0

5.0

Input low level voltage

VinL

1.5

Hold time before a new
transmission can start

tBUF

1.3

Hold time for start conditions

tHDS

0.6

Set-up time for stop conditions

tSUP

0.6

Hold time data

tHDAT

0.3

Set-up time data

tSUPDAT

0.25

Rise time of SCL

1.0

Fall time of SCL

3.0

Maximum clock frequency

Fscl

Pin 30

400

kHz

Low period of the SCL clock

Tlow

Pin 30

1.3

High period of the SCL clock

Thigh

Pin 30

0.6

SDA and SCL input threshold

Vinth

Pin 30, 31

2.2

Acknowledge output voltage on
SDA input with 3mA

VACK

Pin 31

0.4

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

C Bus Timing Requirement

HORIZONTAL SECTION

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS (V

= 5V, Tamb = 25

Table 8. Horizontal Section Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

VCO

Minimum oscillator resistor

(Min.)

Pin 6

Minimum oscillator capacitor

(Min.)

Pin 5

390

Maximum oscillator frequency

(Max.)

150

kHz

OUTPUT SECTION

Maximum input peak current

I12m

Pin 12

Horizontal drive output maximum

current

HOI

Pin 26, sunk current

Table 9. Horizontal Section Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY AND REFERENCE VOLTAGE

Supply voltage

Vcc

Pin 29

10.8

13.2

Supply voltage

Pin 32

4.5

5.5

Supply current

Pin 29

Supply current

Pin 32

Horizontal reference voltage

REF-H

Pin 13, I = -2mA

7.4

8.6

Vertical reference voltage

REF-V

Pin 21, I = -2mA

7.4

8.6

BUF

SDA

SCL

HDS

SUPDAT

HIGH

SUP

HDAT

LOW

Stop:Clock High

Start:Clock High

Data Change:Clock Low

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

Max. sourced current on V

REF-H

Pin 13

Max. sourced current on V

REF-V

Pin 21

1st PLL SECTION

Polarity integration delay

HpoIT

Pin 1

0.75

VCO control voltage (pin 7)

VCO

REF-H

= 8V

fH (Max.)

1.3

6.2

VCO gain (pin 7)

COG

Ro = 6.49K

Co = 820pF,

dF/dV = 1/11RoCo

kHz/V

Horizontal phase adjustment

(see 11)

Hph

% of horizontal period

Horizontal phase setting value (Pin 8)

(see 11)

Minimum current value

Typical value

Maximum value

Hphmin

Hphtyp

Hphmax

Sub-address 01

Byte x 1111111

Byte x 1000000

Byte x 0000000

2.8

3.4

4.0

PLL1 filter current charge

IPII1U

IPII1L

PLL1 is unlocked

PLL1 is locked

140

Free running frequency

Ro = 6.49K

Co = 820pF,

fo = 0.97/8RoCo

22.8

kHz

Free running frequency thermal drift (no

drift on external components)

(see 7)

dF0/dT

-150

ppm/c

Free running frequency adjustment

Minimum value

Maximum value

fo(Min.)

fo(Max.)

Sub-address 02

Byte x x x 11111

Byte x x x 00000

0.8

1.3

PLL1 capture range

Ro = 6.49K

Co = 820pF,

from fo + 0.5kHz to
4.5Fo (fo:22.8kHz)

fH (min.)

fH (max.)

100

23.5

kHz

Safe forced frequency

SF1 Byte 11 x x x x x x

SF2 Byte 10 x x x x x x

SFF

Sub-address 02

2F0

3F0

2ND PLL SECTION HORIZONTAL OUTPUT SECTION

Flyback input threshold

voltage (pin12)

FBth

0.65

0.75

Horizontal jitter

Hjit

At 31.4kHz

ppm

Table 9. Horizontal Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Horizontal drive output duty-cycle

(pin 26)

(see 1)

Low level

High level

HDmin

HDmax

Sub-address 00

Byte xxx11111

Byte xxx00000

(see 2)

X-RAY protection input threshold

voltage

XRAYth

Pin 25

(see 12)

Internal clamping levels on 2nd PLL
loop filter (pin 4)

Vphi2

Low level

High level

1.6

4.0

Threshold voltage to stop H-out, V-out,

B-out and reset XRAY when V

VSCinh

Pin 29

7.5

Threshold voltage to stop H-out, V-out,
B-out and reset XRAY when V

VSDinh

Pin 32

4.0

Horizontal drive output (low level)

HDvd

Pin 26 I

OUT

= 30mA

0.4

VERTICAL DYNAMIC FOCUS FUNCTION (POSITIVE PARABOLA)

Bottom DC output level

HDFDC

LOAD

= 10K

, Pin 10

DC output voltage thermal drift

(see 17)

TDHDF

200

ppm/C

Vertical dynamic focus parabola
amplitude with VAMP and VPOS typical

Min. Byte 000000

Typ. Byte 100000

Max. Byte 111111

AMPVDF

Sub-address 0F

0.5

Vpp

Parabola amplitude function of VAMP
(tracking between VAMP and VDF) with

VPOS typ. (Figure 1)

(see 3)

VDFAMP

Sub-address 05

Byte 10000000

Byte 11000000

Byte 11111111

0.6

1.5

Vpp

Parabola asymmetry function of VPOS

control (tracking between VPOS and
VDF) with VAMP Max.

VHDFKeyt

Sub-address 06

Byte x0000000

Byte x1111111

0.52

Vpp

Table 9. Horizontal Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

VERTICAL SECTION

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS (V

= 12V, TAMB = 25

Table 10. Vertical Section Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

OUTPUTS SECTION

Maximum EW output voltage

VEWM

Pin 24

6.5

Minimum EW output voltage

VEWm

Pin 24

1.8

Minimum load for less than 1% vertical amplitude
drift

LOAD

Pin 20

Table 11. Vertical Section Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

VERTICAL RAMP SECTION

Voltage at ramp bottom point

VRB

REF-V

= 8V,

Pin 22

Voltage at ramp top point (with sync)

VRT

REF-V

= 8V,

Pin 22

Voltage at ramp top point (without sync)

VRTF

Pin 22

VRT-0.1

Vertical sawtooth discharge time duration
(pin 22)

VSTD

With 150nF cap

Vertical free running frequency see

(see 4)

VFRF

OSC (pin22)

=150nF

measured on
pin 22

100

AUTO -SYNC frequency

(see 13)

ASFR

=150nF

185

Ramp amplitude drift versus frequency at

Maximum vertical amplitude

RAFD

= 150nF

50Hz < f < 185Hz

200

ppm/

Ramp linearity on pin 22 (

I22/I22)

(see 4)

RIin

2.5 < V

< 4.5V

0.5

Vertical position adjustment voltage

(pin 23 - V

OUT

centering)

Vpos

Sub address 06

Byte x0000000

Byte x1000000

Byte x1111111

3.65

3.2

3.5

3.8

3.3

Vertical output voltage

(peak-to-peak on pin 23)

VOR

Sub address 05

Byte x0000000

Byte x1000000

Byte x1111111

3.5

2.25

3.75

2.5

Vertical output maximum current (pin 23)

VOI

±5

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Max vertical S-correction amplitude

(see 14)

XOXXXXXX inhibits S-C

ORR

X1111111 gives max S-C

ORR

dVS

Sub address 07

V/Vpp at TV/4

V/Vpp at 3TV/4

-4

Vertical C-Corr amplitude

XOXXXXXX inhibits C-corr

Ccorr

Sub address 08

V/Vpp at TV/2

Byte X1000000

Byte X1100000

Byte X1111111

-3

EAST/WEST FUNCTION

DC output voltage with typ. Vpos, keystone
and corner inhibited

pin 24,

see figure 2

2.5

DC output voltage thermal drift

TDEW

see note 7

100

ppm/

Parabola amplitude with max. Vamp,

typ. V-Pos, keystone and corner inhibited

EWpara

Sub address 0A

Byte 1111111

Byte 1100000

Byte 1000000

1.7

0.85

Vpp

Parabola amplitude function of V-AMP control

(tracking between V-AMP and E/W) with typ.
Vpos, typ. EW amplitude, keystone and corner

inhibited

(see 8)

EWtrack

Sub address 05

Byte 1000000

Byte 1100000

Byte 1111111

0.30

0.55

0.85

Vpp

Keystone adjustment capability with typ.Vpos,

corner and E/W inhibited and max. vertical

amplitude.

(see 8)

KeyAdj

Sub address 09

Byte 1x000000

Byte 1x111111

0.65

Vpp

Intrinsic keystone function of V-POS control

(tracking between V-pos and EW) max. E/W
and max. vertical amplitude and corner

inhibited.

(see 7)

A/B ratio

B/A ratio

Key-

Track

Sub address 06

Byte x0000000

Byte x1111111

0.52

Corner amplitude with max. VAMP, typ.
VPOS,

keystone and E/W inhibit

Corner

Sub address 0B

Byte 11111111

Byte 11000000

Byte 10000000

1.7

-1.7

Vpp

INTERNAL HORIZONTAL DYNAMIC PHASE CONTROL FUNCTION

Side pin balance parabola amplitude (Figure3)
with max. Vamp, typ. V-POS and

parallelogram inhibited

(see 8, 9)

SPBpara

Sub address 0D

Byte x1111111

Byte x1000000

+1.4

-1.4

Table 11. Vertical Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

Side pin balance parabola amplitude function
of Vamp control (tracking between Vamp and
SPB) with max. SPB, typ. V-POS and

parallelogram inhibited

(see 8, 9)

SPBtrack Sub address 05

Byte 10000000

Byte 11000000

Byte 11111111

0.5

0.9

1.4

Parallelogram adjustment capability with max.

Vamp, typ. V-POS and max. SPB

(see8, 9)

ParAdj

Sub address 0E

Byte x1111111

Byte x1000000

+1.4

-1.4

Intrinsic parallelogram function of Vpos control
(tracking between V-pos and DHPC) with max.
Vamp, max. SPB and parallelogram inhibited

(see 8, 9)

A/B ratio

B/A ratio

Partrack

Sub address 06

Byte x0000000

Byte x1111111

0.52

VERTICAL MOIRE

Vertical moire (measured on V

OUT

) pin 23

VMOIRE

Sub address 0C

Byte 01x11111

BREATHING COMPENSATION

DC breathing control range

(see 15)

BRRANG

V18

Vertical output variation versus DC breathing
control (Pin 23)

BRADj

V18

REF-V

V18 = 4V

-10

Table 11. Vertical Section Electrical Characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

B+ SECTION

OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

= 12V, Tamb = 25

Table 12. B+ Section

Operating Conditions

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Minimum feedback resistor

FeedRes Resistor between pins 15 and 14

Table 13. B+ Section Electrical Characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Error amplifier open loop gain

OLG

At low frequency

(see 10)

Sunk current on error amplifier output
when BOUT is in safety condition

Icomp

Pin 14

(see 12)

0.5

Unity gain band width

UGBW

(see 7)

MHz

Regulation input bias current

IRI

Current sourced by pin 15
(PNP base)

0.2

Maximum guaranteed error amplifier

output current

EAOI

Current sourced by pin 14

Current sunk by pin 14

0.5

Current sense input voltage gain

CSG

Pin 16

Max current sense input threshold

voltage

MCEth

Pin 16

1.2

Current sense input bias current

ISI

Current sourced by pin 16

(PNP base)

Maximum external power transistor on
time

Tonmax

% of H-period

@ fo = 27kHz

(see 6)

100

B+ output saturation voltage

B+OSV

with I

= 10mA

0.25

Internal reference voltage

REF

On error amp positive input
for subaddress 0B

Byte 1000000

4.8

Internal reference voltage adjustment
range

REFADJ

Byte 111111

Byte 000000

+20

-20

Falling time

FB+

Pin 28

100

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

NOTES:

Duty cycle is the ratio of power transistor off time period. Power transistor is off when output transistor is off.

Initial condition for safe operation start up.

S and C correction are inhibited so the output sawtooth has a linear shape.

With register 07 at byte x0xxxxxx (s-correction is inhibited) then the S correction is inhibited, and with register 08 at byte
x0xxxxxx (C-Correction is inhibited) consequently the sawtooth has a linear shape.

These parameters are not tested on each unit. They are measured during our internal qualification.

The external power transistor is OFF during 400ns.

These parameters are not tested on each unit. They are measured during out internal qualification.

Refers to notes 4.

TH is the Horizontal period.

10. These parameters are not tested on each unit. They are measured during our internal qualification procedure which

includes characterization on batches coming from corners of our processes and also temperature characterization.

11. See Figure 7 for explanation of reference phase.
12. See Figure 11.
13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on

Pin 22 and with a constant ramp amplitude.

14. TV is the vertical period.
15. When not used the DC breathing control pin must be connected to 12V.

CAUTIONS:

The ICS near CDT can be latched up by EHT. Therefore, in order to minimize the impact of the EHT, it is necessary to place
ICs far from CDT.

If you have not applied below recommendation, a parasitic effect of ionizing field induced by CDT EHT (Extremely

High Tension) make stock charges between resin and chip surface. In this case, abnormal leakage is increased.

And may cause no operation failure. For protecting CDT's EHT interference, it is necessary to add metal-sheet for

isolating or locate ICs far from CDT.

Photo#1: Isolation used by metal sheet

Photo#2: Not locate near-by CDT

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Table 15. Geometry Output Wave forms

Function

Sub

address

Pin

Byte

Specification

Picture Image

Key stone

(trapezoid)

control

E/W + corner

inhibited

1x000000

1x111111

E/W

(pin cushion)

control

Keystone +

corner Inhibited

10000000

1111111

Corner control

Keystone + E/W

inhibited

11111111

10000000

Parallelogram

control

Internal

SPB

Inhibited

1x000000

1x111111

Side pin

balance

control

Internal

Parallelogram

Inhibited

1x000000

1x111111

Vertical

dynamic

focus

0.65V

2.5V

1.7V

2.5V

1.7V

3.7V

1.4% T

3.7V

1.4% T

3.7V

1.4% T

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

C BUS ADDRESS TABLE

Slave address (8C): Write mode

Sub address definition

Slave address (8D): Read mode

No sub address needed

Table 16. I

C Bus Address Table

Horizontal drive selection/horizontal duty cycle

Horizontal position

Forced Frequency/free running frequency

Synchro priority/horizontal moire amplitude

Refresh/B+ reference adjustment

Vertical ramp amplitude

Vertical position adjustment

S correction

C correction

E/W keystone

E/W amplitude

E/W corner adjustment

Vertical moire amplitude

Side pin balance

Parallelogram

Vertical dynamic focus amplitude

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

[ ] initial value

Set the unspecified bit to [0] in order to assure the compatibility with future devices.

Table 17. I

C Bus Address Table (continued)

WRITE MODE

HDrive

0: off

[1]: on

Horizontal duty cycle

[0]

Xray

1: reset

[0]

Horizontal phase adjustment

[1]

[0]

Forced frequency

Free running frequency

1: on

[0]: off

1: F0x2

[0]: F0x3

[0]

Sync

0: comp

[1]: sep

HMoire

1: on

[0]

Horizontal moire amplitude

[

]

[0]

Detect

refresh

[0]: off

B+ reference adjustment

[1]

[0]

Vramp

0: off

[1]: on

Vertical ramp amplitude adjustment

[1]

[0]

Vertical position adjustment

[1]

[0]

S Select

1: on

[0]

S correction

[1]

[0]

C Select

1: on

[0]

C correction

[1]

[0]

EW key

0: off

[1]

East/west keystone

[1]

[0]

East/west amplitude

[1]

[0]

E/W cor

0: off

[1]

East/west corner adjustment

[1]

[0]

Test V

1: on

[0]: off

Vmoire

1: on

[0]

Vertical moire

[0]

SPB sel

0: off

[1]

Side pin balance

[1]

[0]

Parallelogram

0: off

[1]

Parallelogram

[1]

[0]

Test H

1: on

[0]: off

Vertical dynamic focus amplitude

[1]

[0]

READ MODE

Hlock

0: on

[1]: no

Vlock

0: on

[1]: no

Xray

1: on

[0]: off

Polarity detection

Synchro detection

H/V pol

[1], negative

V pol

[1], negative

Vext det

[0], no det

H/V det

[0], no det

V det

[0], no det

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

OPERATING DESCRIPTION

GENERAL CONSIDERATIONS

Power Supply

The typical values of the power supply voltages Vcc and V

are respectively 12V and 5V. Optimum operation is

obtained if Vcc and V

are maintained in the limits: 10.8 to 13.2V and 4.5 to 5.5V.

In order to avoid erratic operation of the circuit during the transient phase of Vcc and V

switching on, or switching

off, the value of Vcc and V

are monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V

typically.
In the same manner, V

is monitored and internal set-up is made until V

reaches 4V (see I

C control table for

power on reset).

In order to have a very good power supply rejection, the circuit is internally supplied by several internal voltage
references (the typical value is 8V). Two of these voltage references are externally accessible, one for the vertical
part and one for the horizontal part. If needed, these voltage references can be used (until I

load

is less than 5mA).

Furthermore it is necessary to filter the voltage references by the use of external capacitor connected to ground, in
order to minimize the noise and consequently the

jitter

on vertical and horizontal output signals.

C Control

S1D2512X01 belongs to the I

C controlled device family, instead of being controlled by DC voltage on dedicated

control pins, each adjustment can be realized through the I

C interface. The I

C bus is a serial bus with a clock and

a data input. The general function and the bus protocol are specified in the Phillips-bus data sheets.

The interface (data and clock) is TTL-level compatible. The internal threshold levels of the input comparator are
2.2V on rising edge and 0.8V on falling edge (when V

is 5V). Spikes of up to 50ns are filtered by an integrator

and maximum clock speed is limited to 400kHz.

The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply
information (1byte) to the micro-processor.
The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to
transmit the IC-address (hexa 8C for write, 8D for read).

Write Mode

In write mode the second byte sent contains the sub address of the selected function to adjust (or controls to affect)
and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the
third byte no stop or start condition is detected, the circuit increments automatically the momentary sub address in
the sub address counter by one (auto-increment mode). So it is possible to transmit immediately the next data
bytes without sending the IC address or sub address. It can be useful so as to reinitialize the whole controls very
quickly (flash manner). This procedure can be finished by a stop condition.

The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the
dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+
reference adjustment.
17 bits are also dedicated to several controls (on/off, horizontal forced frequency, sync priority, detection refresh
and XRAY reset).

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Read Mode

During read mode the second byte transmits the reply information.
The reply byte contains horizontal and vertical lock/unlock status, the XRAY activated or not, the horizontal and
vertical polarity detection. It also contains the Synchro detection status which is used by the MCU to assign sync
priority.
A stop condition always stops all the activities of the bus decoder and switches to high impedance both the data
and the clock line (SDA and SCL) .
See I

C sub address and control tables.

Sync processor

The internal sync processor allows the S1D2512X01 to accept any kind of input Synchro signals:

Separated horizontal & vertical TTL-compatible sync signals,

Composite horizontal & vertical TTL-compatible sync signals.

Sync identification Status

The MCU can read (address read mode: 8D) the status register via the I

C bus, and then select the sync priority

depending on this status.
Among other data this register indicates the presence of sync pulses on H/HVIN, VSYNCIN and (when 12V is
supplied) whether a Vext has been extracted from H/HVIN. Both horizontal and vertical sync are detected even if
only 5V is supplied.

In order to choose the right sync priority the MCU may proceed as follows (see I

C address Table):

Refresh the status register,

Wait at least for 20ms(max. vertical period),

Read this status register,

Sync priority choice should be:

Of course, when choice is made, one can refresh the sync detections and verify that extracted Vsync is present
and that no sync change occurred.
The Sync processor is also giving sync polarity information.

IC status

The IC can inform the MCU about the 1st horizontal PLL and vertical section status(locked or not), and about the
XARY protection (activated or not). Resetting the XRAY internal latch can be done either by decreasing the Vcc or
V

supply or directly resetting it via the I

C interface.

Vext Det

H/V Det

V Det

Sync Priority Subaddress 03 (D8)

Comment Sync Type

Yes

Separated H & V

Yes

Composite TTL H & V

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

Sync Inputs

Both H/HVin and Vsyncin inputs are TTL compatible trigger with Hysteresis to avoid erratic detection.
Both inputs include a pull up register connected to V

Sync Processor Output

The sync processor indicates on the HLOCKOUT Pin whether 1st PLL is locked to an incoming horizontal sync.
HLOCKOUT is a TTL compatible CMOS output. Its level goes to high when locked. In the same time the D8 bit of
the status register is set to 0. This information is mainly used to trigger safety procedures (like reducing B+ value)
as soon as a change is detected on the incoming sync. Further to this, it may be used in an automatic procedure
for free running frequency(fo) adjustment.

Sending the desired fo on the sync input and progressively decreasing the free running frequent I

C register value

(address 02), the HLOCKOUT Pin will go high as soon as the proper setting is reached. Setting the free running
frequency this way allows to fully exploit the S1D2512X01 horizontal frequency range.

HORIZONTAL PART

Internal input conditions

Horizontal part is internally fed by Synchro processor with a digital signal corresponding to horizontal Synchro
pulses or to TTL composite input.
concerning the duty cycle of the input signal, the following signals (positive or negative) may be applied to the
circuit.

Using internal integration, both signals are recognized on condition that Z/T < 25%, Synchronization occurs on the
leading edge of the internal sync signal. The minimum value of Z is 0.7

An other integration is able to extract vertical pulse of composite Synchro if duty cycle is more than 25% (typically
d = 35%)

(see 7)

The last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input
which is intolerant to wrong or missing pulse.

TRAMEXT

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

PLL1

The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO).
The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector
avoids locking on wrong frequencies. It is followed by a charge pump, composed of two current sources sunk and
sourced (I = 1mA typ. when locked, I = 140

A when unlocked). This difference between lock/unlock permits a

smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system
when PLL1 is locked avoiding horizontal too fast frequency change.

The dynamic behavior of the PLL is fixed by an external filter which integrates the current of the charge pump.
A CRC filter is generally used (see Figure 4)

PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong
pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump
and the filter (see Figure 5).

The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the
capacitor, by a current proportional to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.

Figure 4. PLL1

Figure 5. Block Diagram

PLL1F

1.8K

4.7uF

1uF

Input

Interface

Comp1

Charge

PUMP

PLL

Inhibition

VCO

Lockdet

Phase
Adjust

OSC

Hpos

Adj.

Low

High

Tramext

HSYNC

H-LOCKOUT

Lock/Unlock

Status

Tramext

Forced

Frequency

PLL1F R0

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 6). The theoretical
frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to
clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible
to adjust free running frequency through I

C. This adjustment can be made automatically on the manufacturing line

without manual operation by using lock/unlock information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is
the free running frequency at power on reset).

The sync frequency has to be always higher than the free running frequency. As an example for a Synchro range
from 24kHz to 100kHz, the suggested free running frequency is 23kHz.
Another feature is the capability for MCU to force horizontal frequency through I

C to 2xF0 or 3xF0 (for burn in

mode or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is
forced to 2.66V for 2xF0 or 4.0V for 3xF0.

The PLL1 ensures the coincidence between the leading edge of the Synchro signal and a phase reference
obtained by comparison between the sawtooth of the VCO and an internal DC voltage I

C adjustable between

2.8V and 4.0V (corresponding to

10%) (see Figure 7)

Figure 6. Details of VCO

Figure 7. PLL1 Timing Diagram

4 I

6.4V

Flip

Flop

Loop
Filter

(0.80<a<1.30)

C Free running

(1.3V < V

< 6V)

1.6V

6.4V

1.6V

0.875T

Adjustment

H osc
Sawtooth

7/8T

1/8T

6.4V
2.8V < Vb < 4.0V

1.6V

Phase REF1

H Synchro

Phase REF1 is obtained by compari-
son between the sawtooth and a DC
voltage adjustable between 2.8V and
4.0V. The PLL1 ensures the exact
coincidence between the signals
phase REF and Hsyns. A

/10

phase adjustment is possible

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

The S1D2512X01 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked
or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync
processor). The block function is described in figure 5.
When PLL1 is unlocked, It forces Hlockout to leave high.
The lock/unlock information is also available through I

C read.

PLL2

The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO
(Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output
current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The
maximum recommended input current is 5mA (see Figure 9).

The duty cycle is adjustable through I

C from 30% to 60%. For start up safe operation, initial duty cycle (after

power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor.
The maximum storage time (Ts max.) is (0.44T

-T

FLY

/2). Typically, T

FLY

/TH is around 20% which means that Ts

max is around 34% of T

Figure 8. PLL2 Timing Diagram

Figure 9. Flyback Input Electrical Diagram

H osc
Sawtooth

7/8T

1/8T

6.4V

4.0V

1.6V

Shaped Flyback

H drive

Flyback

Internally

Duty Cycle

HFLY

400

20K

GND 0V

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

Output Section

The H-drive signal is sent to the output through a shaping stage which also controls the H-drive duty cycle (I

adjustable). In order to secure scanning power part operation, the output is inhibited in the following circumstances:

Vcc and V

too low

XRAY protection activated

During horizontal Flyback

H Drive I

C bit control is off.

The output stage is composed of a NPN bipolar transistor. Only the collector is accessible (see Figure 10).

The output stage is intended for reverse base control, where setting the output NPN in off-state will control the
power scanning transistor in off-state.
The maximum output current is 30mA, and the corresponding voltage drop of the output V

CEsat

is 0.4V Max.

It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has
to be designed between the circuit and the power transistor which can be of bipolar or MOS type.

X-RAY Protection

The activation of the X-ray protection is obtained by application of a high level on the X-ray input (8V on pin 25). It
inhibits the H-drive and B+ outputs.
This protection is latched; It may be reset either by Vcc or V

switch off or by I

C (see Figure 11).

Vertical Dynamic Focus

The S1D2512X01 delivers a vertical parabola wave from on pin 10. Vertical dynamic focus is tracked with VPOS
and VAMP. Its amplitude can be adjusted. It is also affected by S and C corrections. This positive signal once
amplified has to be connected to the CRT focusing grids.

Figure 10. Output Section

26 H-DRIVE

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

VERTICAL PART

Geometric Corrections

The principle is represented in Figure 12.

Figure 11. Safety Functions Block Diagram

Figure 12. Geometric Corrections Principle

C Drive on/off

Checking

VSCinh

XRAY

or V

off

Horizontal Flyback

0.7V

C Ramp on/off

Horizontal
Output
Inhibition

Vertical
Output
Inhibition

Bout

Checking

or I

C Reset

VSDinh

XRAY Protection

Vertical Ramp V

OUT

DCMID

(3.5V)

EW + amp

To Horizontal

Phase

Side pin Balance

Output Current

EW Output

Dynamic Focus

V.Focus amp

DCMID

(3.5V)

DCMID

(3.5V)

Corner

Keystone

Side pin amp

Parallelogram

Parabola

Generator

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

Starting from the vertical ramp, a parabola shaped current is generated for E/W correction, dynamic horizontal
phase control correction, and vertical dynamic focus correction.
The base of the parabola generator is an analog multiplier, the output current of which is equal to:

I = k

OUT

- V

DCMID

)

Where Vout is the vertical output ramp (typically between 2 and 5V) and V

DCMID

is 3.5V (for V

REF-V

= 8V). One

more multiplier provides a current proportional to (Vout - V

DCMID

)

for corner correction The VOUT sawtooth is

typically centered on 3.5V. By changing the vertical position, the sawtooth shifts by

0.3V.

In order to keep a good screen geometry for any end user preference adjustment we implemented the geometry
tracking.

Due to large output stages voltage range (E/W, keystone, corner), the combination of tracking function with
maximum vertical amplitude, max or min vertical position and maximum gain on the DAC control may lead to the
output stages saturation. This must be avoided by limiting the output voltage by appropriate I

C registers values.

For E/W part and dynamic horizontal phase control part, a sawtooth shaped differential current in the following
form is generated:

= k

OUT

- V

DCMID

)

Then

I and

are added together and converted into voltage for the E/W part.

Each of the three E/W components, and the two dynamic horizontal phase control ones may be inhibited by their
own I

C select bit.

The E/W parabola is available on pin 24 via an emitter follower which has to be biased by an external resistor
(10K

). Since stable in temperature, the device can be DC coupled with an external circuitry.

The vertical dynamic focus is available on output pin 10. Dynamic horizontal phase control current drives internally
the H-position, moving the Hfly position on the horizontal sawtooth in the

1.4% T

both on side pin balance and

parallelogram.

EWOUT = 2.5V + K1 (V

OUT

- V

DCMID

)

+ K2 (V

OUT

- V

DCMID

)

+ K3 (Vout - V

DCMID

)

K1 is adjustable by the keystone I

C register

K2 is adjustable by the EW amplitude I

C register

K3 is adjustable by the corner I

C register

Dynamic Horizontal Phase Control

IOUT = K4 (V

OUT

- V

DCMID

)

+ K5 (V

OUT

- V

DCMID

)

K4 is adjustable by side pin balance I

C register

K5 is adjustable by parallelogram I

C register.

Function

When the Synchronization pulse is not present, an internal current source sets the free running frequency. For an
external capacitor, C

OSC

= 150nF, the typical free running frequency is 100Hz.

Typical free running frequency can be calculated by:

fo Hz

(

)

1.5 10

OSC

--------------

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

A negative or positive TTL level pulse applied on pin 2 (VSYNC) as well as a TTL composite sync on pin 1 can
Synchronize the ramp in the range [fmin, fmax]. This frequency range depends on the external capacitor
connected on pin 22. A capacitor in the range [150nF,

5%] is recommended for application in the following range:

50Hz to 185Hz.
Typical maximum and minimum frequency, at 25

C and without any correction (S correction or C correction), can

be calculated by:

(Max.)

= 3.5

fo and f

(Min.)

= 0.33

If S or C corrections are applied, these values are slightly affected.
If a Synchronization pulse is applied, the internal oscillator is synchronized immediately but the amplitude changes.
An internal correction is activated to adjust it in less than a half a second: the highest voltage of the ramp pin 22 is
sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance amplifier
generates the charge current of the capacitor. The ramp amplitude becomes again constant.

The read status register enables to have the vertical lock-unlock and the vertical sync polarity informations.
It is recommended to use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory.
A good stability of the internal closed loop is reached by a 470nF

5% capacitor value on pin 20 (VAGC)

Figure 13. AGC Loop Block Diagram

SYNCHRO

OSCILLATOR

Switch

Disch

V-SYNC

POLARITY

DISCH.

OSC
CAP

CHARGE CURRENT

TRANSCONDUCTANCE

AMPLIFIER

REF

SAMP
CAP

SAMPLING

S CORRECTION

VS_AMP
SUB07/6bits

COR-C
SUB08/6bits

C CORRECTION

Vlow

VERT_AMP

SUB05/7BITS

VMOIRE

SUB0C/5BITS

VOSITION

SUB06/7BITS

BREATH

VOUT

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

S1D2512X01

C Control Adjustments

Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are
generated internally. Their amplitude are adjustable by their respective I

C register. They can also be inhibited by

their select bit. The amplitude of this S and C corrected ramp can be adjusted by the vertical ramp amplitude
control register. The adjusted ramp is available on pin 23 (VOUT) to drive an external power stage. The gain of this
stage is typically 25% depending on its register value. The mean value of this ramp is driven by its own I

C register

(vertical position). Its value is VPOS = 7/16

REF

300mV.

Usually VOUT is sent through a resistive divider to the inverting input of the booster. Since VPOS derives from
V

REF-V

, the bias voltage sent to the non-inverting input of booster should also derive from V

REF-V

to optimize the

accuracy (see application diagram).

Basic Equations

In first approximation, the amplitude of the ramp on pin 23 (Vout) is:
V

OUT

- VPOS = (V

OSC

- V

DCMID

)

(1 + 0.25 (V

AMP

) )

with:
·

DCMID

= 7/16

REF

(typically 3.5V, the middle value of the ramp on pin 22)

OSC

= V22 (ramp with fixed amplitude)

VAMP = - 1 for minimum vertical amplitude register value and +1 for maximum

VPOS is calculated by: VPOS = V

DCMID

+ 0.3Vp with Vp equals -1 for minimum vertical position register value

and +1 for maximum

The current available on pin 22 is:

with C

OSC

: capacitor connected on pin 22

f: synchronization frequency.

Vertical Moire

By using the vertical moire, VPOS can be modulated from frame to frame. This function is intended to cancel the
fringes which appear when line to line interval is very close to the CRT vertical pitch. The amplitude of the
modulation is controlled by register VMOIRE on address OC and can be switched - off via the control bit D7.

OSC

REF

OSC

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

DC/DC CONVERTER PART

This unit controls the switch-mode DC/DC converter. It converts a DC constant voltage into the B+ voltage(roughly
proportional to the horizontal frequency) necessary for the horizontal scanning. This DC/DC converter must be
configured in step-up mode. It operates very similarly to the well known UC3842.

Step-up Mode

Operating description

The power MOS is switched-on at the middle of the horizontal Flyback.

The power MOS is switched-off when its current reaches predetermined value. For this purpose, a sense
resistor is inserted in its source. The voltage on this resistor is sent to pin16 (I

SENSE

The feedback (coming either from the EHV or from the Flyback) is divided to a voltage close to 4.8V and com-
pared to the internal 4.8V reference (I

VREF

). The difference is amplified by an error amplifier, the output of

which controls the power MOS switch-off current.

Main Features

Switching synchronized on the horizontal frequency

B+ voltage always higher than the DC source

Current limited on a pulse-by-pulse basis

The DC/DC converter is disabled:
- When V

or V

are too low,

- When X-Ray protection is latched,
- Directly through I

C bus.

When disabled, BOUT is driven to GND by a 0.5mA current source. This feature allows to implement externally
a soft start circuit.

S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

APPLICATION BOARD CIRCUIT

Figure 15. Application Circuit

MC14528

VCC=12V

50K

6.8K

12V

HSYNC

VSYNC

22nF 100V

820pF 50V

1% P

1.8K

4.7uF 50V

10nF 100V MP

0.1uF

22K

100uF

1uF

10K

AFC

4.7uF

0.1uF

33K

3.3K

50K

22K

100

SDA

SCL

100uF

10K

HOUT

22K

10K

AFC

150nF 100V

1% P

470nF 63V P

0.1uF

10K

47uF
50V

50K

SCLK

SCL

SDA

74HCT125

SDAT

ACK

100K

47pF

HOUT

0.1uF

100uF

33pF

10K

AFC

47pF

100K

SDA

VCC

B+OUT

GND

XRAY

EWOUT

VOUT

VSCAP

H_OUT

VAGCCAP

HBLKOUT

V_REF

VGND

COMP

VSYNC_IN

PLL2C

PLL1F

H_LOCKCAP

H MOIRE

FOCUS

HGND

HFLY

H_REF

REGIN

SCL

HSYNC_IN

I_SENSE

B+GND

H_LOCKOUT

KB2512

S1D2512X

H-POSITION

BREATH

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