INTERGER RF/IF DUAL PLL

S1M8821/22/23

INTRODUCTION

The S1M8821/22/23 is a high performance dual frequency
synthesizer with integrated prescalers designed for RF operation up
to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The S1M8821/22/23 contains dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or a 128/129 prescaler(32/33 or 64/65 for
the S1M8823) and the IF synthesizer adopts an 8/9 or a 16/17
prescaler.
Using a proprietary digital phase-locked-loop technique, the
S1M8821/22/23 has linear phase detector characteristic and can be
used for very stable, low noise local oscillator signal. Supply voltage
can range from 2.7V to 4.0V. The S1M8821/22/23 is now available

20-TSSOP/24-QFN package.

FEATURES

High operating frequency dual synthesizer

-- S1M8821 : 0.1 to 1.2GHz (RF)/ 45 to 520MHz (IF)

-- S1M8822 : 0.2 to 2.0GHz (RF)/ 45 to 520MHz (IF)

-- S1M8823 : 0.5 to 2.5GHz (RF)/ 45 to 520MHz (IF)

Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA)

Operating voltage range : 2.7 to 4.0V

Selectable power saving mode(Icc=1uA typical @3V)

Dual modulus prescaler :
S1M8821/22 (RF) 64/65 or 128/129
S1M8823 (RF) 32/33 or 64/65
S1M8821/22/23 (IF) 8/9 or 16/17

Programmability via serial bus interface

No dead-zone PFD

Variable charge pump output current

High speed lock mode

APPLICATIONS

Cellular telephone systems : S1M8821

Portable wireless communications : S1M8822 (PCS/PCN, cordless)

Wireless Local Area Networks (W-LANs) : S1M8823

Other wireless communication systems

20-TSSOP-BD44

24-QFN-3.5

4.5

INTERGER RF/IF DUAL PLL

S1M8821/22/23

BLOCK DIAGRAM

NOTE: The pin numbers above are for 20-TSSOP package.

foLD

Data Out

Multiplexer

Phase

Detector

Charge

Pump

Phase

Detector

Charge

Pump

RF Prescaler

Prescaler

Control

Programmable

Counter

RF N-Latch

RF R-Latch

RF Reference

Counter

IF Reference

Counter

20-bit Shift Register

IF R-Latch

IF N-Latch

2-bit

Control

IF Prescaler

Prescaler

Control

Counter

Programmable

CPoRF

GND

OSCin

GND

foLD

CPoIF

GND

DATA

CLOCK

S1M8821/22/23

INTERGER RF/IF DUAL PLL

PIN CONFIGURATION

NOTES:
1. pin #9 = pin #17(internally connected).
2.

Do not tie up Vp and VDD
: Vp is the source of digital noises. The power for analog part is supplied by VDD.

If Vp and VDD are tied together, noisy Vp corrupts the power source for the analog part.

Vp1

CPoRF

GND

finRF

GND

OSCin

GND

foLD

Vp2

CPoIF

GND

finIF

GND

DATA

CLOCK

20-Lead(0.173 Wide) Thin Shrink Small

Outline Package(20-TSSOP)

S1M8821

S1M8822

S1M8823

20-TSSOP

(Digital)

(Analog)

(Digital)

(Analog)

INTERGER RF/IF DUAL PLL

S1M8821/22/23

PIN CONFIGURATION(24-QFN, NOT TO SCALE)

NOTES:
1

pin #10 = pin #19(internally connected).

Do not tie up Vp and V

Vp is the source of digital noises. The power for analog part is supplied by V

DD.

If Vp and V

are tied together,

noisy Vp corrupts the power source for the analog part.

Vp1

CPoRF

GND

finRF

GND

OSCin

GND

foLD

2 Vp2

CPoIF

GND

finIF

GND

DATA

CLOCK

N/C

S1M8822

S1M8823

S1M8821

(24-QFN) Package

24-QFN

24 PIN Quad Flat Non-leaded

(Digital)

(Analog)

* N/C pins must be connected
to GND(to Analog GND if
possible).

S1M8821/22/23

INTERGER RF/IF DUAL PLL

PIN DESCRIPTION

Pin No

(20TSSOP)

Pin No

(24QFN)

Symbol

I / O

Description

Power supply voltage input for the RF PLL part. V

1 must

equal V

2. In order to reject supply noise, bypass capacitors

must be placed as close as possible to this pin and be
connected directly to the ground plane.

N/C

No connection.

Vp1

Power supply voltage input for RF charge pump(

1).

CPoRF

Internal RF charge pump output for connection to an external
loop filter whose filtered output drives an external VCO.

GND

Ground for RF digital blocks.

finRF

RF prescaler input. The signal comes from the external VCO.

finRF

The complementary input of the RF prescaler. A bypass
capacitor must be placed as close as possible to this pin and
be connected directly to the ground plane. The bypass
capacitor is optional with some loss of sensitivity.

GND

Ground for RF analog blocks.

OSCin

Reference counter input. TCXO is connected via a coupling
capacitor.

N/C

No connection.

GND

Ground for IF digital blocks.

oLD

Multiplexed output of the RF/IF programmable counters, the
reference counters, the lock detect signals and the shift
registers. The output level is CMOS level. (see f

out

Programmable Truth Table)

CLOCK

CMOS clock input. Serial data for the various counters is
transferred into the 22-bit shift register on the rising edge of
the clock signal.

N/C

No connection.

DATA

Binary serial data input. The MSB of CMOS input data is
entered first. The control bits are on the last two bits. CMOS
input.

Load enable CMOS input. When LE becomes high, the data
in the shift register is loaded into one of the four latches (by
the control bits).

GND

Ground for IF analog blocks.

INTERGER RF/IF DUAL PLL

S1M8821/22/23

PIN DESCRIPTION (Continued)

Pin No

(20TSSOP)

Pin No

(24QFN)

Symbol

I / O

Description

finIF

The complementary input of the IF prescaler. A bypass
capacitor must be placed as close as possible to this pin and
be connected directly to the ground plane. The bypass
capacitor is optional with some loss of sensitivity.

finIF

IF prescaler input. The signal comes from the external VCO.

GND

Ground for IF digital blocks.

CPoIF

Internal IF charge pump output for connection to an external
loop filter whose filtered output drives an external VCO.

N/C

No connection.

Vp2

Power supply voltage input for IF charge pump(

Power supply voltage input for the IF PLL part. V

1 must

equal V

2. In order to reject supply noise, bypass capacitors

must be placed as close as possible to this pin and be
connected directly to the ground plane.

INTERGER RF/IF DUAL PLL

S1M8821/22/23

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC CHARACTERISTICS

These devices are ESD sensitive. These devices must be handled in the ESD protected environment.

Characteristic

Symbol

Value

Unit

Power Supply Voltage

0 to 4.0

Power Dissipation

600

Operating Temperature

-40 to +85

Storage Temperature

STG

-65 to +150

Characteristic

Pin No.

ESD level

Unit

Human Body Model

All

< ±

2000

Machine Model

All

< ±

300

Charged Device Model

All

< ±

800

S1M8821/22/23

INTERGER RF/IF DUAL PLL

ELECTRICAL CHARACTERISTICS

=3.0V, V

=3.0V, Ta

C, Unless otherwise specified)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Power Supply Voltage

2.7

3.0

4.0

3.0

4.0

Power
Supply
Current

S1M8823 RF + IF

=2.7V to 4.0V

5.5

S1M8823 RF Only

4.0

S1M8822 RF + IF

4.5

S1M8822 RF Only

3.0

S1M8821 RF + IF

3.5

S1M8821 RF Only

2.0

S1M882x IF Only

1.5

Power down Current

PWDN

=3.0V

1.0

Digital inputs : CLOCK, DATA and LE

High-Level Input Voltage

=2.7V to 4.0V

0.7V

Low-Level Input Voltage

=2.7V to 4.0V

0.3V

High-Level Input Current

= V

=4.0V

-1.0

+1.0

Low-Level Input Current

=0V, V

=4.0V

-1.0

+1.0

Reference Oscillator Input : OSCin

Input Current

IHR

= V

=4.0V

+100

ILR

=0V, V

=4.0V

-100

Digital Output : foLD

High Level Output Voltage

Iout = -500

-0.4

Low Level Output Voltage

Iout = +500

0.4

INTERGER RF/IF DUAL PLL

S1M8821/22/23

ELECTRICAL CHARACTERISTICS (Continued)

=3.0V, V

=3.0V, Ta

C, Unless otherwise specified)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Charge Pump Outputs : CPoRF, CPoIF

Charge Pump Output
Current

CP-SRC

/2, I

CPo

=Low

-1.0

CP-SINK

/2, I

CPo

=Low

+1.0

CP-SRC

/2, I

CPo

=High

-4.0

CP-SINK

/2, I

CPo

=High

+4.0

Charge Pump Leakage
Current

CPL

0.5V

-0.5V

-2.5

+2.5

Output Current Sink vs.
Source Mismatch*

CP-SINK

vs I

CP-SRC

Output Current Magnitude
Variation vs. Temperature**

vs T

Output Current Magnitude
Variation vs. Voltage***

vs V

0.5V

-0.5V

Programmable Divider

Operating
Frequency

S1M8823

finRF

=2.7V to 4.0V

0.5

2.5

GHz

S1M8822

0.2

2.0

S1M8821

0.1

1.2

Operating Frequency

finIF

=3.0V

520

MHz

RF Input Sensitivity

fin

=3.0V

-15

dBm

=4.0V

-10

IF Input Sensitivity

fin

=2.7V to 4.0V

-10

dBm

Phase Detector Frequency

MHz

Reference Divider

Operating Frequency

OSCin

MHz

Input Sensitivity

OSCin

0.5

S1M8821/22/23

INTERGER RF/IF DUAL PLL

ELECTRICAL CHARACTERISTICS (Continued)

=3.0V, V

=3.0V, Ta

C, Unless otherwise specified )

<For Charge Pump items>
Ia=Charge pump sink current at Vcp=Vp-

V, Ib=Charge pump sink current at Vcp=Vp/2,

Ic=Charge pump sink current at Vcp=

Id=Charge pump source current at Vcp=Vp-

V, Ie=Charge pump source current at Vcp=Vp/2,

If=Charge pump source current at Vcp=

V=Voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents

become flat.

* Output Current Sink vs. Source Mismatch = [| Ib|-|Ie|] / [0.5 * {| Ib|+|Ie|}] * 100 (%)

** Output Current Magnitude Variation vs. Temperature =
[| Ib @any temp.| - |Ib @ 25

C|] / | Ib @ 25

C| * 100 (%) and [|Ie @any temp.| - |Ie @ 25

C|] / |Ie @ 25

C| * 100 (%)

*** Output Current Magnitude Variation vs. Voltage =
[0.5 * {|Ia|-|Ic|}] / [0.5 * {|Ia|+|Ic|}] * 100 (%) and [0.5 * {|Id|-|If|}] / [0.5 * {|Id|+|If|}] * 100 (%)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Serial Data Control

CLOCK Frequency

CLOCK

MHz

CLOCK Pulse Width High

CWH

CLOCK Pulse Width Low

CWL

DATA Set Up Time to CLOCK
Risng Edge

DATA Hold Time after CLOCK
Rising Edge

LE Pulse Width

LEW

CLOCK Rising Edge to LE Rising
Edge

CLE

INTERGER RF/IF DUAL PLL

S1M8821/22/23

FUNCTIONAL DESCRIPTION

The Samsung S1M8821/22/23 are dual PLL frequency synthesizer ICs. S1M8821/22/23 combined with external
LPFs and external VCOs form PLL frequency synthesizers. They include serial data control, R counter, N counter,
prescaler, phase detector, charge pump, and etc.

Serial data is moved into 20-bit shift register on the rising edge of the clock. These data enters MSB first. When LE
becomes HIGH, data in the shift register is moved into one of the 4 latches(by the 2-bit control). The divide ratios of
the prescaler and the counters are determined by the data stored in the latches. The external VCO output signal is
divided by the prescaler and the N counter. External reference signal is divided by the R counter. These two signals
are the two input signals to the phase detector. The phase detector drives the charge pump by comparing
frequencies and phases of the above two signals. The charge pump and the external LPF make the control voltage
for the external VCO and finally the VCO generates the appropriate frequency signal.

Serial Data Input Timing

MSB

LSB

N20(R20)

N19(R19)

N10(R10)

N9(R9)

CWL

CWH

LEW

DATA

CLOCK

CLE

S1M8821/22/23

INTERGER RF/IF DUAL PLL

PROGRAMMING DESCRIPTION

Control Bits

Programmable Reference Counter(IF / RF R Counter)

If the Control Bits are 00(IF) or 01(RF), data is moved from the 20-bit shift register into the R-latch which sets the
reference counter. Serial data format is shown in the table below.

15-Bit Programmable Reference Counter Ratio

Division ratio : 3 to 32767

Data are shifted in MSB first

Control Bits

DATA Location

IF R Counter

RF R Counter

IF N Counter

RF N Counter

Division

Ratio

32767

C1 C2

LSB

MSB

Program Modes

Division Ratio of the R Counter, R

Control Bits

INTERGER RF/IF DUAL PLL

S1M8821/22/23

Programmable Counter(N Counter)

If the Control Bits are 10(IF) or 11(RF), data is transferred from the 20-bit shift register into the N-latch. N Counter
consists of 7-bit swallow counter(A counter) and 11-bit main counter(B counter). Serial data format is shown below.

7-Bit Swallow Counter Division Ratio(A Counter)

11-Bit Main Counter Division Ratio(B Counter)

Division ratio : 3 to 2047

Division

Ratio(A)

Division

Ratio(A)

127

Division ratio : 0 to 127
B

Division ratio : 0 to 15
B > A
X = DON'T CARE condition

Division

Ratio

2047

C1 C2

LSB

MSB

Program Modes

Division Ratio of the N Counter, N

Control Bits

S1M8821/22/23

INTERGER RF/IF DUAL PLL

Pulse Swallow Function

VCO

=[ ( P X B ) + A ] x f

OSCin

/ R

VCO

: External VCO output frequency

P : Preset modulus of dual modulus prescaler

(for S1M8821/22 RF:P=64 or 128, for S1M8823 RF:P=32 or 64, for IF: P=8 or 16)

B : 11-bit main counter division ratio (3

2047)

A : 7-bit swallow counter division ratio

(for RF: 0

127, for IF: 0

15, A

OSCin

: External reference frequency(from external oscillator)

R : 15-bit reference counter division ratio (3

32767)

Program Mode

Mode Select Truth Table

* The charge pump output current of I

CPo

LOW = 1/4

CPo

HIGH.

R16

R17

R18

R19

R20

IF Phase

Detector Polarity

IF I

CPo

IF CPoIF

High Impedance

RF Phase

Detector Polarity

RF I

CPo

RF CPoIF

High Impedance

N19

N20

IF Prescaler

Pwdn IF

RF Prescaler

Pwdn RF

Phase Detector Polarity

CPoIF High Impedance

CPo

IF Prescaler

RF Prescaler

S1M8821/22

(S1M8823)

Pwdn

Negative

Normal Operation

Low

8/9

64/65 (32/33)

Pwr Up

Positive

High Impedance

High

16/17

128/129 (64/65)

Pwr Dn

INTERGER RF/IF DUAL PLL

S1M8821/22/23

Phase Detector Polarity

Depending on VCO characteristics, R16 bit should be set as follows :

VCO characteristics are positive like (1) : R16 HIGH

VCO characteristics are negative like (2) : R16 LOW

foLD (Pin10) Output Truth Table

-- When the PLL is locked and a lock detect mode is selected, the foLD output is HIGH, with narrow pulses

LOW.

-- Counter Reset mode resets R & N counters.

-- The high speed lock mode sets the foLD output pin to be connected to ground with a low impedance

(

110

RF R19

(RF LD)

IF R19

(IF LD)

RF R20

(RF fo)

IF R20

(IF fo)

foLD Output State

Disabled (default LOW)

IF Lock Detect

RF Lock Detect

RF and IF Lock Detect

IF Reference Divider Output

RF Reference Divider Output

IF Programmable Divider Output

RF Programmable Divider Output

High Speed Lock mode

IF Counter Reset

RF Counter Reset

RF and IF Counter Reset

(1)

(2)

VCO Input Voltage

t
put

Freq

uen

c
y

VCO Characteristics

S1M8821/22/23

INTERGER RF/IF DUAL PLL

FUNCTIONAL DESCRIPTION

(Continued)

Powerdown mode operation

There are synchronous and asynchronous powerdown modes for S1M8821/22/23.
Synchronous powerdown mode occurs if R18 bit is LOW, N20 bit is HIGH and charge pump output is in high
impedance state. In the synchronous power down mode, the powerdown function is activated by the charge pump
to diminish unwanted frequency jumps. Asynchronous powerdown mode occurs if R18 bit is HIGH and N20 bit is
HIGH.
When the PLL goes to either synchronous or asynchronous powerdown mode, preamp becomes debiased, R & N
counters keeps their load conditions and the charge pump becomes high impedance state. The oscillator circuitry
function becomes disabled only when both IF and RF powerdown bits are activated, i.e. N20 HIGH.
The PLL returns to an active powerup mode when N20 bit becomes LOW(either in synchronous or asynchronous
modes).

Phase Detector and Charge pump Characteristics

Phase difference detection range : -2

to +2

When R16 = HIGH

R18

N20

Powerdown mode status

PLL active

PLL active, only charge pump high impedance

Synchronous powerdown

Asynchronous powerdown

fr>fp

fr=fp

fr<fp

CPo

INTERGER RF/IF DUAL PLL

S1M8821/22/23

RF SENSITIVITY MEASUREMENT CIRCUIT

Signal

Generator

Frequency

Counter

Parallel

Port

Microstrip

100pF

12k

39k

OSC

foLD

2.7V to 4.0V

LE
DATA
CLOCK

100pF

2.2

** N=10,000 R=50 P=64
** Sensitivity limit is determined when the error of the divided RF output( foLD) becomes

1 Hz.

10dB ATTN

S1M8821/22/23

INTERGER RF/IF DUAL PLL

TYPICAL APPLICATION CIRCUIT

** The role of Rin : Rin makes VCO output power go to the load rather than the PLL.
The value of Rin depends on the VCO power level.

foLD

GND

OSCin

GND

finRF

GND

CPoRF

CLOCK DATA

GND

CPoIF

VCO

From
Controller

IF out

100pF

10pF

100pF

0.01

100pF

0.01

100pF

0.01

100pF

0.01

10pF

100pF

RF out

1000pF

foLD

Reference
Input

S1M8821/22/23

<RF VCO Module: ALPS Part No>
. CDMA : UCVA4X103A
. K-PCS : UCVW4X102A
. US-PCS : UCVA3X120A

INTERGER RF/IF DUAL PLL

S1M8821/22/23

PACKAGE DIMENSIONS

#20

#11

#10

6.4

3
0

0.2

0.0

1
2

6.40 ¡¾ 0.20

0.252 ¡¾ 0.008

6.90

0.272 MAX

0.2

0.0

0
8

1
0

0
7

0.30

0.012

0.22 ¡¾ 0.10

0.009 ¡¾ 0.004

0.65

0.026

0
5

0
0

0.10MAX

0.004MAX

4.40 ¡¾ 0.20

0.173 ¡¾ 0.008

5.72

0.225

0.50 ¡¾ 0.20

0.020 ¡¾ 0.008

15 x

-0

.
0

006

-
0

.
002

+0
.
1

+0
.0

0 ~

8

20-Lead TSSOP Package
(Samsung 20-TSSOP-BD44)

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S1M8821X01-R0T0

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S1M8821X01-R0T0