ENHANCED-1 CHIP CT0 RF IC

S1T8528

INTRODUCTION

S1T8528 is a 1 CHIP RF IC which can be used in high performance
CTO CLP systems at max. 60MHz. S1T8528 is designed to include a
receiver, PLL and COMPANDER to minimize PCB space
requirements. Improved RX characteristics such as inter-modulation,
spurious response and adjacent channel interface have been
included to satisfy the universal standards.

The 1 CHIP RF IC has considerably reduced the cost by including a
build-in 1

st mixer, low battery detector, fMCU, RSSI, RF regulator

and speaker amp. Also, it fulfills carrier detector threshold control,
speaker volume control, operating mode selection and MUTE function
using S/W, thus making external application easier.

FEATURES

Operating voltage range: 2.0V ~ 5.5V

Typical supply current: 8.9mA at 3.6V

Built-in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V )

Built-in speaker volume control and speaker amplifier

Built-in splatter filter

Support mode selection ( Active, Rx, Standby and Inactive mode )

FM Receiver

-- Excellent Receiver characteristics

-- RSSI ( Linear ) and Carrier detector output ( Digital ) function

Compander

-- Easy gain control and application using external component

-- -Included ALC (Automatic Level Control) circuit

Universal PLL

-- RX (TX) divided counter range : 1/16 ~ 1/16383

-- Reference frequency divided counter range : 1/16 ~ 1/4095

-- Lock detector signal output

-- Serial interface with MICOM for controlling each block

-- Clock Output for MICOM oscillator substitution. ( X-tal divided clock by 2, 3, 4 and 5 )

ORDERING INFORMATION

< 10.7MHz crystal filter used >

Input sensitivity

Adjacent channel

rejection

Spurious rejection

(image of the second IF)

Intermodulation

rejection

0.7

Vrms at 12dB

SINAD

> 55dB

> 60dB

> 50dB

Device

Package

Operating Temperature

+ S1T8528X01-Q0R0

QFP

1010E

20C to + 70C

+ : New product

QFP

1010E

S1T8528

ENHANCED-1 CHIP CT0 RF IC

BLOCK DIAGRAM

Limiting
IF AMP

RSSI

Carrier
Detector

Rectifier

Gain Cell

Regulator
(Vcc/2)

Limiter

Gain Cell

Rectifier

IF AMP

(455KHz)

Quadrature

Detector

FSK
COMP

ALC

RX
VCO

IF AMP
(10.7MHz)

1st

MIX

PLL Regulator

( 2.05 V )

Programmable Counter ( REF )

RX Phase
Detector

TX Phase
Detector

fMCU

4_25 CNT

CONTROL

Buffer

SUM
AMP

MIC
AMP

SPK
AMP2

SUM
AMP

PRE AMP

AMP

Compander
mute

X-tal
OSC

Low
Battery
Detector

2nd
MIX

VREF

CRC

SFI

SFO

CDO/LDT

CLKO

CLK

DATA

LBD

AGIC

PDT

EPI

ERC

SAI

SAO1

SAO2

VCC

(COMP)

GND

(COMP)

CPI

CPO

ALC

REF

(COMP)

2MO

VCC

(RX)

GND

(RX)

QCI

RAO

DSCI

DSCO

RSSI

2LOI

GND

(PLL)

REF

(RF)

2MI

1LOI

1MI

TIF

1MI

1MO

REF

(PLL)

VCO

PDR

Splatter
Filter

VREF

Programmable Counter ( RX )

Programmable Counter ( TX )

Internal

cap.

SPK
AMP1

Volume control

VCC

(RX)

ENHANCED-1 CHIP CT0 RF IC

S1T8528

PIN CONFIGURATION

EPI

ERC

SAI

SAO1

SAO2

VCC

(COMP)

GND

(COMP)

CPI

CPO

CRC

2MI

VCC

(RX)

GND

(RX)

QCI

RAO

DSCI

DSCO

RSSI

REF(COMP)

ALC

KB8528

SFI

SFO

CDO/LDT

CLKO

CLK

DATA

LBD

AGIC

GND

(PLL)

REF(RF)

2MO

2LOI

1LOI

1MI

TIF

1MI

1MO

REF(PLL)

PDT

VCO

PDR

S1T8528

S1T8528

ENHANCED-1 CHIP CT0 RF IC

PIN DESCRIPTION

Pin No

Symbol

Description

PDT

Phase detector output terminal of the transmitter at PLL.
If f

> f

REF

or f

is leading

the output is negative pulse

If f

< f

REF

or f

is lagging

the output is positive pulse

If f

= f

REF

and the same phase

the output is High Impedance

Compressor output terminal of compander: connected to the splatter filter amp input
terminal.

SFI

Input terminal of Splatter filter amp.

SFO

Output terminal of Splatter filter amp.

LDT/CDO

LDT: Output terminal of transmitter lock detector in PLL block. Output is low if PLL is in

lock state and is high if PLL is in unlock state.

CDO: As an output terminal of the carrier detector buffer, connected to (RSSI ) terminal

of MICOM. This pin outputs the contents of Meter Driver buffer which is turned
on/off, according to the signal level detected by Meter Driver.

MCU

Clock output terminal for MCU crystal.
This pin provides the clock source for MCU or other system as an output of
X-tal osc.

5. Which can be controlled by the bit of the control register.

Clock ON/OFF control is possible by MCU

7
8
9

CLK
DATA
EN

These pins are serial interface terminals for programming reference counter, auxiliary
reference counter, TX channel counter, RX channel counter and control block that
controls internal each block with 4 mode selection.

LBD

Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ).
During the normal operation, output level is low, but it is high at low battery detection.
As this pin is an open collector type, it requires a pull-up resister.

AGIC

This pin bypasses AC elements at the feedback loop which come from the SUM amp
block of COMPRESSOR. A capacitor should be connected between this terminal and
GND. ( C = 2.2uF )

CRC

Converts waveform from the full wave rectifier to DC element at the rectifier block of
Compressor. ( RC = 33 msec at C = 3.3uF)

CPO-

Pre-amp output terminal of Compressor.
Used as an input terminal for voice signals.

CPI

Inverting type Pre-amp input terminal of Compressor.

GND

(COMP

)

Ground.
Ground of Compander.

Vcc

(COMP)

Supply voltage.
Power supply terminal of Compander.

SAO 2

Output terminal of speaker amp 2.
This signal is the same as SAO1 output, but phase difference is 180

for SAO1 DC

voltage level is Vcc / 2.

ENHANCED-1 CHIP CT0 RF IC

S1T8528

SAO 1

Output terminal of Speaker amp 1.
DC voltage level is Vcc/ 2.

SAI

Speaker Amp 1 input terminal.
Between this terminal and Expander output terminal, apply DC coupled capacitor.

Output terminal of Expander

ERC

Converts waveform from the full wave rectifier to DC element at the rectifier block of
Expander. ( RC = 33 msec at C = 3.3uF )

EPI

Pre-amp inverting input terminal of Expander.
Adjusts the negative feedback loop gain. ( in application, gain is 5 )

ALC

Reference current input terminal of Automatic Level Control ( ALC); Adjusts THD of
compressor output voltage to less than 3% or limits the frequency deviation of TX if the
input is higher than a certain level. The ALC circuit may be turned off depending on the
ALC reference current or the magnitude of output voltage may be limited if it is higher
than a certain level.

REF(COMP)

Reference voltage ( VREF= 1/2 VCC ). Supplies a regulator voltage to the Compressor
and Expander of COMPANDER.

RSSI

Received Signal Strength Indicator terminal ( Analog type )

DSCO

Output terminal of Data Slicing comparator.
Separates Frequency Shift Keying ( FSK ) serial data and executes data shaping and
limiting.

DSCI

Input terminal of Data slicing comparator.
Non-inverting type with the negative input terminal biased to 1/2 Vcc.

RAO

Recovered Audio Output terminal. Voice signals detected by the Quadrature Detector
are amplified and then output through this terminal.

QCI

Quadrature coil input terminal.
The 455kHz oscillator circuit is an Lp = 680uH, Cp = 180pF valued LC tank circuit.
Voice signals are detected by mixture of 455kHz ( by phase difference ) which is
converted from mixer 2.

GND

Ground .
Ground for Receiver.

Limiter input and decoupling terminal.
Limiter block removes amplitude modulation elements caused by fading or FM signal
noise. Limiting IF stage makes the second intermediate frequency amplify and limit.
The input impedance of the limiting IF amplifier is set to 1.5k

While FM waves are transmitted with constant magnitude, their magnitudes are slightly
modulated due to reflection from obstacles, fading phenomenon, noise wave and
mixing with AM wave elements before entering the receiver

s antenna.

The limiter makes amplitude uniform by removing these AM wave elements.

CC(RX)

Supply voltage.
Supplies power to the Receiver.

PIN DESCRIPTION (Continued)

Pin No

Symbol

Description

S1T8528

ENHANCED-1 CHIP CT0 RF IC

2MI

Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via
10.7MHz ceramic filter. Second mixer converts frequency to second intermediate
frequency ( 455kHz: AM IF ).

2MO

Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by
mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output.

36
37

2LOI
2LOI

Input terminal of second local oscillator. These pins generate 2

nd local oscillation

frequency and are designed as colpitt type oscillator.
10.24MHz or 10.245MHz can be applied as for 2

nd local oscillator.

1MO

Output terminal of mixer 1.
The signal from mixer 1 and the frequency of the first local oscillator are mixed to
produce the first intermediate frequency, which is the output through this terminal. The
output terminal is an emitter follower with an output impedance of 330

to match the

330

input / output impedance of the 10.7MHz ceramic filter.

39
40

1LOI
1LOI

Input terminal of the first local oscillator.
The local oscillator is a voltage controlled oscillator. Local oscillation frequency and
received frequency are mixed at mixer 1 and then converted to the first intermediate
frequency of 10.7MHz or 10.695MHz.

VCO

The terminal which variable capacitor is included in the chip. Used as an input terminal
where 1st local oscillation frequency is changed by varying the capacitor connected
between 1st local oscillator terminals.
The internal variable capacitor has the value of 18.73 ~ 15.86 pF depending on the
applied voltage. ( 1.0 ~ 2.0V )

42
43

1MI
1MI

Input terminal of Mixer1. This mixer is made of doubly balanced multiplier.
The received signal amplified at RF AMP is input to this terminal.

GND

(PLL)

Ground.
Ground for analog at PLL.

PDR

Phase detector output terminal of the receiver at PLL.
If f

> f

REF

or f

is Leading

The output is negative pulse

If f

< f

REF

or f

is Lagging

The output is positive pulse

If f

= f

REF

and the same phase

The output is high impedance

REF(RF)

An internal PMOS pass transistor provides power supplier for the RF pre amplifier.
PMOS pass transistor is on in Active/Rx mode and off in Standby/Inactive mode.

REF(PLL)

PLL voltage reference output pin.
An internal voltage regulator provides a stable power supply voltage for the RX and TX
PLLs. (2.05V)

TIF

Input terminal of TX channel counter.
AC coupling with TX VCO.
Minimum input level is 300 mVp-p ( at 60MHz ).

PIN DESCRIPTION (Continued)

Pin No

Symbol

Description

ENHANCED-1 CHIP CT0 RF IC

S1T8528

ABSOLUTE MAXIMUM RATINGS

CURRENT CONSUMPTION AT EACH MODE ( VCC = 3.6V )

CURRENT CONSUMPTION IN EACH BLOCK ( VCC = 3.6V )

Characteristic

Symbol

Value

Unit

Maximum Supply Voltage

Vcc

5.5

Power Dissipation

600

Operating Temperature

OPR

20 -- + 70

Storage Temperature

SCG

55 -- + 150

Modes

Min.

Typ.

Max.

Active mode (Communication mode )

8.9mA

RX mode

4.8mA

Stand-by mode

700uA

Inactive mode (Battery Saving Mode)

50uA

70uA

Modes

Min.

Typ.

Max.

Receiver part

3.5mA

4.6mA

Expander part

0.8mA

1.1mA

Speaker part

1.0mA

1.4mA

compressor part

1.7mA

2.1mA

PLL

RX part

1.2mA

1.6mA

TX part

0.7mA

1.1mA

Total

8.9mA

11.9mA

S1T8528

ENHANCED-1 CHIP CT0 RF IC

ELECTRICAL CHARACTERISTICS

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Operating Voltage

Vcc

2.0

5.5

RECEIVER

( V

= 3.6V, f

= 49.7MHz, f

DEV

3kHz, f

MOD

= 1kHz,Ta = 25°C, unless otherwise specified )

Sensitivity
(input for 12dB SINAD)

SEN

MIX1 Matched Impedance
Input

0.7

2.0

Vrms

Input for -3dB Limiting

LIM

MIX1 Matched Impedance
Input

0.7

2.0

Vrms

S/N Ratio

S/N

RFin = 1mVrms

Recovered Audio Output

O(RA)

RFin = 1mVrms,
After 2nd stage LPF

147

177

207

mVrms

Recovered Audio Output
Voltage Drop

O(RAD

)

Vcc = 5.5V

2.0V

RFin = 1mVrms

3.0

1.5

Detector Output Resistance

O(DET)

RFin = 1mVrms

1.2

Detect Output Voltage

O(DET)

RFin = 1mVrms

1.0

1.5

2.0

Detector Output Distortion

THD

DET

RFin = 1mVrms
(with CCITT Filter)

1.0

2.5

Comparator Threshold
Voltage Difference

COMP

= 360mVp-p

HYS

= 180K

110

150

Comparator Output Voltage 1 V

COMP

=360mVp-p

HYS

= 180k

Vcc-0.4

Comparator Output Voltage 2 V

COMP

= 360mVp-p

HYS

= 180k

0.1

0.4

First Mixer Conversion
Voltage Gain

V(1M)

MIX1 1/2

= 1mVrms

= 330k

Second Mixer Conversion
Voltage Gain

V(2M)

MIX2

= 1mVrms

= 1.5k

Demodulator Bandwidth

DBW

RFin = 1mVrms

kHz

Limiter Input Sensitivity

I(LIM)

Fc = 455kHz ,

3dB Limiting

uVrms

AM Rejection Ratio

AMRR

RFin = 1mVrms
AM MOD = 30% @1kHz

First Mixer 3rd Order
Intercept Point

IMD3

MIX1 Input 50

Termination

dBm

First Mixer Input Impedance

I(1M)

Fc = 50MHz

690

7.2

First Mixer output Impedance Ro

(1M)

Fc = 10.7MHz

330

ENHANCED-1 CHIP CT0 RF IC

S1T8528

Second Mixer input
Impedance

I(2M)

Fc = 10.7MHz

Second Mixer output
Impedance

(2M)

Fc = 455kHz

1.5

Carrier Detector Threshold

MIX1 Single-Ended
Matching,

Default Threshold=1010

dBm

Low Battery Detector

LBD

LBD0 ~ LBD3 = 0 ( Default )
Only LBD2 = 0
Only LBD1 = 0
Only LBD3 = 0
LBD0 ~ LBD3 = 1

0.15

3.45

3.3
3.0

0.1

2.2
2.1

0.075

RSSI Slope

RSSI

MIX1 Single-Ended
Matching

mV/dB

RSSI Output Voltage
Dynamic Range

RSSI

MIX1 Single-Ended
Matching

Carrier Detect
Output High Voltage

RFin = 1

Vrms

Default Threshold = 1010

Vcc-0.4

Carrier Detect
Output Low Voltage

RFin = 10

Vrms

Default Threshold = 1010

0.4

COMPRESSOR

( Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified )

Standard Output Voltage

Vo(com)

Vinc = 63.2mVrms

0dB

ALC disabled (pin 13)

269

316

363

mVrms

Compressor Gain
Difference

V1(COM)

Vinc =

20dB

1.0

V2(COM)

Vinc =

40dB

1.5

Compressor Output
Distortion

THD

COM

Vinc = 63.2mVrms

0dB

0.5

1.0

Mute Attenuation Ratio

ATT

MUTE

Vinc = 0dB

Compressor Limiting Voltage

LIM(COM)

Vinc = Variable

1.05

1.35

1.65

Vp-p

ALC

VALC

ALC

= 150k

Vinc = 10dB

310

390

450

mVrms

Splatter filter

Vo(SF)

INC

= 63.2mVrms

0 dB

269

316

363

mVrms

Maximum Output Voltage

OMIC(MAX)

RL = 10K

2.8

Vp-p

EXPANDER

(Vcc = 3.6V, fc = 1kHz, Ta = 25°C, unless otherwise specified)

Standard Output Voltage

O(EXP)

Vin

= 63.2mVrms

0dB

309

356

403

mVrms

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

S1T8528

ENHANCED-1 CHIP CT0 RF IC

Expander Gain Difference

V1(EXP)

Vin

10dB

1.0

V2(EXP)

Vin

20dB

1.5

V3(EXP)

Vin

30dB

2.0

Expander Output Distortion

THD

EXP

Vin

= 63.2mVrms

0dB

0.5

1.0

Mute Attenuation Ratio

ATT

MUTE

Vin

= 63.2mVrms

0dB

Expander Maximum Output
Voltage

OEXP(MAX)

Vin

= Variable

THD = 10%

800

mVrms

Maximum Output Voltage

OSPK(MAX)

= 150

2.2

Vp-p

RL = 600

3.0

Vp-p

Input Current

Vin = Vcc

Vin = 0V

Input Voltage

Vcc-0.3

0.3

Output Current

Vout = Vcc

0.3

Vout = 0V

0.3

Output Voltage

OH1

PDT,PDR: Io = -0.3mA
( Sourcing )

Vcc-0.4

OL1

PDT,PDR: Io = 0.3mA
( Sinking )

0.4

OH2

LD,f

MCU

: Io =

0.1mA

( Sourcing )

Vcc-0.5

OL2

LD,f

MCU

: Io = 0.1mA

( Sinking )

0.5

PLL regulator voltage

PLLREG

1.90

2.05

2.20

Regulator Load Current

REG

Vout = V

REG

(OPEN)-0.05V

3.0

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

ENHANCED-1 CHIP CT0 RF IC

S1T8528

PLL PROGRAM SUMMARY

MCU ( MICOM ) Serial Interface ( MSB : 1st INPUT )
Use CLK (Pin 7 ), DATA (Pin 8 ) , and EN (Pin 9 ) terminals for program.
DATA and CLK terminals are used for loading data to internal Shift - Register. When EN terminal is

Low

, It is possible to program TX-Channel Counter, RX - Channel Counter and various control

functions of PLL. When EN terminal is

High

, Program 1st Local Oscillator Capacitor Selection in

receiver for U.S.A - 25 CH function

-- TX - Register, RX-Register, Control Register

Figure 1.

-- Reference - Register

Figure 2.

DATA

CLK

MSB

LSB

PMC0 PMC1

14Bit DATA

DATA

CLK

MSB

LSB

PMC

UK_

12Bit DATA

UK_

S1T8528

ENHANCED-1 CHIP CT0 RF IC

-- Auxiliary - Register(16bits)

Figure 3.

Programmable Counter

-- RX - counter: Setting frequency for RX.VCO ( 14 Bits --> 1/16 ~ 1/16383 )

[ Default_CH. = USA_#21 ( REMOTE ) : 36.075MHz ( Div._NO = 7215 )]

< RX. Register (16bits) >

-- TX - counter: Setting frequency for TX.VCO ( 14 Bits --> 1/16 ~ 1/16383 )

[ Default_CH. = USA_#21 ( REMOTE ) : 49.830MHz ( Div._NO = 9966 )]

< TX. Register (16 bits) >

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Name

PMC0

PMC1

D13

D12

D11

D10

Default value

7215

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Default value

7215

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Name

PMC0

PMC1

D13

D12

D11

D10

Default value

9966

DATA

CLK

MSB

LSB

PMC

CD_TH(4bits)

LBD(3bits)

TEST(2bits)

CLO(6bits)

ENHANCED-1 CHIP CT0 RF IC

S1T8528

* Program Latch Assignl

-- Ref - counter: Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 )

[ Default_Divider = 2048, X-tal_OSC = 10.240 MHz -->Fref = 5KHz ]< Ref. Register (16bits) >

< Ref. Register (16bits) >

-- UK_Selection

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

Default value

9966

PMC0 (Bit15)

PMC1 (Bit14)

Register Assign

Control

UPLL_Rx

UPLL_Ref

UPLL_Tx

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Name

PMC0

PMC1

UK_S1

UK_S0

D11

D10

Default value

2048

Ref.freq. selection

for United Kingdom

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

fMCU_M

FMCU1

FMCU0

Default value

2048

MPU CLK

Mute

MPU CLK

CNTl_1

MPU CLK

CNTL_0

UK_S0

UK_S1

FR1

FR2

FrefTX

FrefRX

fREF (A)

fREF/4 (B)

fREF/25 (C)

fREF/4 (B)

fREF/25 (C)

fREF/4 (B)

fREF/25 (C)

fREF/4 (B)

S1T8528

ENHANCED-1 CHIP CT0 RF IC

Figure 4. Reference frequency selection

Control program

Control register (16 Bits)

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Name

PMC0

PMC1

BS1

BS0

LBD_BS

CO_M

EX_M

SPK_M

Description

Program
Mode
Control_0

Program
Mode
Control_1

Power
Save
Control_1

Power
Save
Control_0

Low
Battery
Detector
Battery
Save

Compressor
Mute

Expander
Mute

Speaker
Mute

Function

Program Latch

Assign

Power Save Mode

0:Normal
(LBD-On)
1:LBD-Part
Power-Off

0: Normal

1: Mute

0:Normal

1:Mute

0:Nomal

1:Mute

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

SPK3

SPK2

SPK1

SPK0

LDT/CDO

fMCU_M

fMCUS1

fMCUS0

Description

SPK
Control_3

SPK
Control_2

SPK
Control_1

SPK
Conrol_
0

LDT/CDO
Select

MCU
Clock
Mute

MCU
Clock
Control_1

MCU
Clock
Control_0

Function

Speaker Volume Control

0: CDO
1: LDT

0: Normal
1: Mute

***

MCU Clock Output

12 Bits Reference
program divider.

¡ À

PD_TX

PD_RX

PDT

PDR

fREF

(A)

fREF

¡ À

(B)

fREF

¡ À

(C)

FR1

FR2

ENHANCED-1 CHIP CT0 RF IC

S1T8528

** Power Save Mode Assign

*** MCU Clock Output Control & Frequency

*** Speaker Amplifier Volume Control

BS1 (Bit13)

BS0 (Bit12)

Power Save Mode

Default

Active

STD_By

Inactive

fMCU_M

fMCUS1

fMCUS0

Clock Output

Divider

X-tal 10.24MHz 11.15MHz

12.0MHz

Don

t Care

Don

t Care

Low

Divider

5.120MHz 5.575MHz

6.0MHz

3.413MHz 3.717MHz

4.0MHz

2.560MHz 2.788MHz

3.0MHz

5 (Default)

2.048MHz 2.230MHz

2.4MHz

DATA

Gain/Attenuation

Output Level [SAO1-SAO2]

SPK3

SPK2

SPK1

SPK0

18dB

25mVrms

16dB

14dB

12dB

50mVrms

10dB

8dB

6dB

100mVrms

4dB

2dB

0dB

200mVrms

+2dB

+4dB

+6dB

400mVrms

+8dB

+10dB

+12dB

800mVrms

S1T8528

ENHANCED-1 CHIP CT0 RF IC

Auxiliary Register (16 Bits)

Auxiliary Register Function

**** TEST Mode & LDT-CDO Mode

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Name

PMC

CLO5

CLO4

CLO3

CLO2

CLO1

CLO0

CD_TH3

Description Auxiliary

Cap=5.9p

Cap=4.8p

Cap=3.2p

Cap=1.6p

Cap=1.3p

Cap=0.8p

CD_TH
Control_3

Function

*****
Program
Mode
Control

st LO Cap Select

CD
Control_3

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

CD_TH2

CD_TH1

CD_TH0

LBD3

LBD2

LBD1

TEST2

TEST1

Description CD_TH

Control_2

CD_TH
Control_1

CD_TH
Control_0

LBD
Control_3

LBD
Control_2

LBD
Control_1

TEST
Mode2

TEST
Mode1

Function

Carrier Detector
Threshold Control

Low Battery Detector
Voltage Control

**** TEST Mode &

LDT-CDO Mode

LDT/CDO

TEST1

TEST2

LDT / CDO

Remark

Rx block CDO

Default

Rx block CDO

4_25cnt block FR2

PLL block LDT

Test PLL_RX

Test PLL_TX

S1T8528

ENHANCED-1 CHIP CT0 RF IC

Operating internal circuit blocks in each mode

Auxiliary Register(CLO_LBD Program)
[ Rx - 1st local oscillation internal cap. for U.S.A - 25CH & low battery detecting voltage ]

-- CLO register ( 6 bits ) : Receiver 1st local oscillator internal capacitor selection

Mode ( state )

Operating circuit blocks

Active state
( Communication mode )

PLL regulator / MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver/ 1st
local oscillator/ RX PLL/ Carrier detector / FSK comparator / Low battery detector
/ TX PLL / Expander & speaker amp / Compressor /Splatter filter amp, Clock
Output

Receiving mode

PLL regulator / MICOM I/F( Data, CLK, EN ) / 2nd local oscillator / Receiver/ 1st
local oscillator/ RX PLL/ Carrier detector / FSK comparator / Low battery
detector, Clock Output

Stand-by mode
(Battery Save Mode#2)

PLL regulator, MICOM I/F ( Data, CLK, EN ), 2nd local oscillator, Clock Output

Inactive state
(Battery Saving Mode#1)

Interrupt

Bit

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Name

PMC

CLO5

CLO4

CLO3

CLO2

CLO1

CLO0

Default
Value 0

1
*****

Function