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Электронный компонент: S1T8536X01

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2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
1
INTRODUCTION
The S1T8536 is a single chip RF transceiver optimized for use in ISM
2.45GHz wireless systems. It is fabricated using Samsung's ASP5HB
0.5um advanced BiCMOS process.
The S1T8536 contains receiver, transmitter, frequency doubler,
voltage controlled oscillator (VCO), phase locked loop(PLL) and
crystal oscillator.
The receiver consists of a 2.4 - 2.5GHz high frequency mixer, an
intermediate frequency (IF) amplifier, a FM quadrature demodulator, a
received signal strength indicator (RSSI), a baseband filter buffer
amplifier and a high speed data slicer with sample & hold function.
The transmitter consists of 2.4 - 2.5GHz high frequency buffer
amplifier.
The PLL operates upto 1.3GHz with 32/33 prescaler and selectable charge pump current. S1T8536 contains on-
chip PLL regulator to minimize switching noise.
The VCO operates 1.15 - 1.3GHz and requires only external tank circuit and loop filter.
S1T8536 contains on-chip VCO regulator to minimize VCO frequency variation due to supply pushing.
The frequency doubler receives 1.15 - 1.3GHz signal from VCO and outputs 2.3 - 2.6GHz signal to receiver and
transmitter.
The crystal oscillator operates 5 - 40MHz and can accept external clock signal.
Two additional voltage regulators provide a stable supply source to external discrete stages in the Rx and Tx
chains.
FEATURES
2.4GHz - 2.5GHz Single-Chip RF Transceiver
Samsung ASP5HB 0.5um Advanced BiCMOS Process
3.0V to 5.5V Operation (RX / TX mode supply current of 75mA / 50mA)
Single Conversion Receiver with 110MHz IF Frequency
Quadrature Demodulator with Greater than 1MHz Bandwidth
Wideband Buffer Amplifier for Baseband Filtering
High Speed Data Slicer Operating Upto 2Mbps with Sample & Hold
1.3GHz PLL with VCO and Frequency Doubler
PLL, VCO, RX and TX Voltage Regulator Included (2.85V)
APPLICATION
2.45GHz ISM Band Wireless Communication Systems
ORDERING INFORMATION
Device
Package
Operating Temperature
S1T8536X01-T0R0
48-LQFP-0707
- 10 to + 70
C
48
-
LQFP
-
0707
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
2
BLOCK DIAGRAM
GND
MIX
VCC
MIX
VCC
IF
MOP
MON
GND
IF
GND
QUAD
IFP
IFN
QUAD
IN
GND
BB
QUAD
OUT
BUF
IN
BUF
OUT
DS
INN
SHEN
DS OUT
OSCO
OSCI
LE
DATA
CLK
LD
CP
VCC
VCO
GND
VCO
VREG
VCO
MIN
MIP
VREG
TX
GND
PLL
VCC
MIX
GND
MIX
GND
IF
TX
OUT
GND
FD
VCOP
VCC
FD
RSSI
VCC
QUAD
CE
VCON
VCC
PLL
VREG
PLL
GND
FD
VREG
RX
SHO
13
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
DS
INP
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Regulator
(2.85V)
Frequency
Doubler
Regulator
(2.85V)
Regulator
(2.85V)
Regulator
(2.85V)
Charge
Pump
Lock
Detector
CONTROL
RF Counter
PFD
REF Counter
RSSI
A
1
Sample
Hold
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
3
PIN CONFIGURATION
GND
MIX
VCC
MIX
VCC
IF
MOP MON
GND
IF
GND
QUAD
IFP
IFN
QUAD
IN
GND
BB
QUAD
OUT
BUF
IN
BUF
OUT
DS
INN
SHEN
DS OUT
OSCO
OSCI
LE
DATA
CLK
LD
CP
VCC
VCO
GND
VCO
VREG
VCO
MIN
MIP
VREG
TX
GND
PLL
VCC
MIX
GND
MIX
GND
IF
TX
OUT
GND
FD
VCOP
VCC
FD
RSSI
VCC
QUAD
CE
VCON
VCC
PLL
VREG
PLL
GND
FD
VREG
RX
SHO
13
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
DS
INP
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
S1T8536
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
4
PIN DESCRIPTION
Pin
Name
Schematic
Description
1
VREGVCO
VCO regulator output (2.85V). Requires external
bypass capacitor.
2
3
VCOP
VCON
These differential ports are used to supply DC
voltage to the VCO as well as tune the center
frequency of the VCO.
4
GNDPLL
Ground of PLL section (Note 1).
5
VCCPLL
Supply of PLL section.
6
VREGPLL
PLL regulator output (2.85V).
Requires external bypass capacitor.
VCCVCO
1
2
3
VCCPLL
6
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
5
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
7
CP
Charge pump output.
8
LD
Lock detector open drain output.
9
10
11
CLK
DATA
LE
Programming clock input.
Programming data input.
Programming load enable input.
12
13
OSCO
OSCI
Crystal oscillator input.
Crystal oscillator output.
14
CE
Chip enable input. Logic high input enables the chip
and logic low input disables the chip.
VCCPLL
7
8
VCCPLL
9, 10, 11
VREGPLL(2.85V)
13
12
VCCPLL
14
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
6
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
15
RSSI
Received signal strength indicator output.
16
SHEN
Sample and hold enable input.
High signal input enable sample and hold function
and low signal input disable sample and hold
function .
17
DSOUT
Data slicer output.
18
SHO
Sample and hold output.
19
20
DSINN
DSINP
Data slicer negative input.
Data slicer positive input.
21
22
BUFOUT
BUFIN
Baseband filter buffer amplifier output.
Baseband filter buffer amplifier input.
VCCIF
15
VCCIF
16
VCCIF
17
18
VCCIF
20
19
VCCIF
21
22
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
7
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
23
QUADOUT
Quadrature demodulator output.
24
GNDBB
Ground of baseband section (Note 1).
25
QUADIN
Quadrature demodulator tank input.
26
VCCQUAD
Supply of quadrature detector section.
27
GNDQUAD
Ground of quadrature detector section (Note 1).
28
29
GNDIF
GNDIF
Ground of IF amplifier section (Note 1).
Pin28 and Pin29 are connected internally.
30
31
IFN
IFP
IF amplifier differential inputs.
DC blocking is required.
32
VCCIF
Supply of IF amplifier section.
33
34
VCCMIX
VCCMIX
Supply of mixer section.
Pin33 and Pin34 are connected internally.
VCCQUAD
23
VCCQUAD
25
VCCIF
30
31
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
8
PIN DESCRIPTION (Continued)
Pin
Name
Schematic
Description
35
36
MON
MOP
RF mixer differential IF outputs.
37
VREGRX
RX regulator output (2.85V).
Requires external bypass capacitor.
38
39
GNDMIX
GNDMIX
Ground of mixer section (Note 1).
Pin38 and Pin39 are connected internally.
40
41
MIP
MIN
RF mixer differential inputs.
DC blocking is required.
42
GNDFD
Ground of frequency doubler section (Note 1).
VCCMIX
36
35
VCCMIX
37
VCCMIX
40
41
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
9
PIN DESCRIPTION (Continued)
NOTE: All ground pads of the chip are down bonded to package ground paddle and each ground pin of the IC is connected to
that package ground paddle.
So all the ground pins are connected together through the exposed ground paddle of the IC package. Proper
connection of package ground to board ground is essential and highly required.
Pin
Name
Schematic
Description
43
VREGTX
TX regulator output (2.85V).
Requires external bypass capacitor.
44
GNDFD
Ground of frequency doubler section (Note 1).
45
VCCFD
Supply of frequency doubler section.
46
TXOUT
TX buffer amplifier output.
47
GNDVCO
Ground of VCO section (Note 1).
48
VCCVCO
Supply of VCO section.
VCCFD
43
VCCFD
46
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
10
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Caution : S1T8536 is a high performance RF integrated circuit and is ESD sensitive.
Handling and assembly of this device should be done at ESD work stations.
Characteristics
Symbol
Value
Unit
Power Supply Voltage
V
CC
6.0
V
Voltage applied to any pin
V
IN
VCC + 0.3
V
Storage Temperature Range
T
STG
-65 to +150
C
Characteristics
Symbol
Value
Unit
Power Supply Voltage
V
CC
3.6
V
Operating Temperature
T
a
-10 to +70
C
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
11
DC ELECTRICAL CHARACTERISTICS
(Ta = 25



C, V
CC
= 3.6V, unless otherwise noted.)
RECEIVER / TRANSMITTER ELECTRICAL CHARACTERISTICS
(Ta=25



C, V
CC
=3.6V, unless otherwise noted. RF=2.45GHz/-47dBm, LO=1.17GHz/-15dBm, IF=110.592MHz
Data = 1Mbps pseudo random sequence with BTb = 0.5 GFSK modulation. Modulation index = 0.5)
NOTES:
1.
Not 100% AC tested but guaranteed by design and characterization.
2.
Measured result on evaluation board with proper impedance matching.
Characteristics
Symbol
Test condition
Min
Typ
Max
Unit
RX Mode Supply Current
(Receiver + Frequency Doubler + PLL + VCO)
ICC-RX
-
-
75
100
mA
TX Mode Supply Current
(Transmitter+Frequency Doubler+PLL+VCO)
ICC-TX
-
-
50
70
mA
Locking Mode Supply Current (PLL + VCO)
ICC-
LOCK
-
-
20
30
mA
Power Down Mode Supply Current (All Off)
ICC-PD
CE(PIN14)=LOW
-
10
100
uA
Characteristics
Symbol
Test condition
Min
Typ
Max
Unit
Mixer Input RF Frequency
RF In Freq.
50ohm
matching
2.4
-
2.5
GHz
Mixer Output IF Frequency
IF Out Freq
SAW matching
50
110.6
200
MHz
1E-3 BER Sensitivity (Notes 1 and 2)
SENS
data out
-
-82
-76
dBm
IF Amplifier Bandwidth
IFAmp BW
-
50
-
200
MHz
IF Amplifier Voltage Gain
IFAmp Gain
-
70
75
-
dB
Quadrature Demodulator Output Voltage
DET Out
External load
variable
100
150
200
mVrms
Quadrature Demodulator Bandwidth
DET BW
-
0.6
1
-
MHz
Baseband Filter Buffer Amplifier Bandwidth
BB Amp BW
External load
variable
1
2
-
MHz
Baseband Filter Buffer Amplifier Voltage Gain
BB Amp
Gain
-
-3
0
+3
dB
Data Slicer Maximum Operating Frequency
DS BW
-
1
2
-
Mbps
RSSI Dynamic Range (110MHz IF Amp Input)
RSSI DR
-
50
60
-
dB
RSSI Output Level (110MHz IF Amp Input)
RSSI Out
IF
input(110MHz)
0.5
-
2.0
V
TX Output Power (Notes 1 and 2)
TX Out
50ohm
matching
-
-15
-
dBm
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
12
VCO / PLL ELECTRICAL CHARACTERISTICS
(Ta = 25



C, V
CC
= 3.6V, unless otherwise noted)
NOTE: Not 100% AC tested but guaranteed by design and characterization.
REGULATOR ELECTRICAL CHARACTERISTICS
(Ta = 25



C, V
CC
= 3.6V, unless otherwise noted.)
NOTES:
1.
Voltage regulation operates under the condition of supply voltage greater than 3.3V.
2.
RX and TX regulator are tested with load current of 10mA.
DIGITAL I / O ELECTRICAL CHARACTERISTICS
(Ta = 25



C, V
CC
= 3.6V, unless otherwise noted)
Characteristics
Symbol
Test condition
Min
Typ
Max
Unit
VCO Operating Frequency (Note 1)
VCO Freq.
-
1150
-
1300
MHz
PLL Operating Frequency
RF In Freq
-
1150
-
1300
MHz
PLL Input Sensitivity (external VCO Input)
RF In Power
-
-15
-
5
dBm
OSC Operating Frequency
OSC In Freq.
-
5
-
40
MHz
OSC Input Sensitivity
OSC In Power
-
100
500
2000
mVpp
Charge Pump Output Current
CPI = Low
-
1.1
1.5
2.0
mA
CPI = High
-
2.1
3.0
4.0
mA
Characteristics
Symbol
Test condition
Min
Typ
Max
Unit
PLL Regulator Voltage (Note 1)
VREG-PLL
load regulated
2.7
2.85
3.0
V
VCO Regulator Voltage (Note 1)
VREG-VCO
load regulated
2.7
2.85
3.0
V
RX Regulator Voltage (Notes 1 and 2)
VREG-RX
load regulated
2.7
2.85
3.0
V
TX Regulator Voltage (Notes 1 and 2)
VREG-TX
load regulated
2.7
2.85
3.0
V
Characteristics
Symbol
Test condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
-
VCC-0.4
-
VCC
V
Low Level Input Voltage
VIL
-
0
-
0.4
V
High Level Output Voltage
VOH
-
VCC-0.4
-
VCC
V
Low Level Output Voltage
VOL
-
0
-
0.4
V
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
13
RECEIVER FUNCTIONAL DESCRIPTION
General
The S1T8536's receiver is a single conversion wideband FM / FSK receiver. This device is designed for use as the
receiver in analog and digital FM systems such as 2.4GHz ISM band cordless phones and wideband data links with
data rates up to 2Mbps. It contains high frequency mixer, IF amplifier, quadrature detector, baseband filter amplifier
and data slicer with sample and hold function.
Mixer
The mixer is a double-balanced with fully differential RF inputs and fully differential IF outputs. Following figure
shows the external components required for wideband 110.592MHz IF operation.
Quadrature Demodulator
The quadrature demodulator requires tank circuit with loaded Q depending on detection bandwidth. Following
figure shows external components required for 110.592 MHz IF operation.
Baseband Filter Buffer Amplifier
Baseband filter amplifier is a wideband buffer and it can be configured as a second-order sallen-key low pass filter.
Following figure shows the external components required.
Cutoff frequency = 1 / [2
*SQRT(R1R2C1C2)]
Quality factor = SQRT(R1R2C1C2) / (R1C2 + R2C2)
The component value of R1 should contain the quadrature detector output resistance.
VCC
MOP MON
IFP IFN
110.592MHz
SAW
36
36
31
30
VCC
QUAD IN
10pF
56nH
22pF
QUAD OUT
25
23
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
14
RECEIVER FUNCTIONAL DESCRIPTION
Data Slicer with Sample and Hold
The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the
baseband filter output can be DC coupled to the data slicer DS-INP(Pin 20). The S1T8536's data slicer
incorporates an sample and hold used to derive the data slicer reference voltage by means of an external
integration circuit. The sample and hold is 'ON' during reception of the preamble data pattern, and is otherwise
`OFF' in TDD (Time Division Duplex) system. The external integration circuit is formed by an RC low pass circuit
placed between SHO (Pin 18) and ground.
The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer
shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a
change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift
close to the threshold voltage, the time constant is longer.
The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the
settling time. When the sample and hold is `OFF' the output (SHO) is in high impedance state with extremely low
leakage current.
Following figure shows the internal block diagram.
The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommended that an
external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of
ground and supply currents in the S1T8536 which might desensitize the chip.
BUF IN
BUF OUT
R1
R2
C2
C1
Vin
Vout
21
22
DS INP
DS INN
SHEN
DS OUT
SHO
20
19
18
16
17
+1
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
15
PLL / VCO FUNCTIONAL DESCRIPTION
GENERAL
The S1T8536's PLL / VCO is a high performance frequency synthesizer with high frequency voltage controlled
oscillator and integrated high frequency prescalers for RF operation upto 1.3GHz. It contains two voltage regulator
of VCO and PLL, dual modulus prescalers providing 32/33 division, no dead-zone PFD, selectable charge pump
current, lock detector output and crystal oscillator.
VCO / PLL VOLTAGE REGULATOR
The S1T8536's PLL / VCO incorporates one on-chip 2.85V voltage regulators for stable VCO operation and
another on-chip 2.85V voltage regulators for minimizing ECL and CMOS switching noise eliminating the need for
an external regulator. They insures stable high frequency operation at 3.0V through 5.5V supply voltage .
VCO regulated voltage is used only for VCO. PLL regulated voltage is used for ECL-prescaler, CMOS-counter,
internal logic circuits and crystal oscillator. All digital input / output pins are referenced to supply voltage rather than
regulated voltage.
CRYSTAL OSCILLATOR
S1T8536 has a oscillator circuit composed of CMOS inverter amplifier. In case of inputting the external reference
frequency directly, use OSCI terminal (Pin 13).
.
LOOP FILTER
Following figure shows third order passive loop filter
OSCO
OSCI
OSCO
OSCI
external
13
12
13
12
CP
VCO tuning
7
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
16
LOCK DETECTOR OPERATION
When the situation that E(error) is less than one period of reference frequency, 1/OSC, continues more than three
cycles of reference counter output, 1/(OSC/R), lock detector outputs `High'.
E
High
1/OSC
1/(OSC / R)
fREF
fPLL
CP
LD
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
17
PLL / VCO FUNCTIONAL DESCRIPTION
VOLTAGE CONTROLLED OSCILLATOR
S1T8536's voltage controlled oscillator (VCO) uses a fully differential topology, with L-C resonant tank circuit off-
chip.
Following figure shows external components for VCO operation.
Following figure shows external components in case of using external VCO.
charge
pump
1
REGULATOR
2
3
LOOP
FILTER
1
2
3
REGULATOR
VCO
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
18
PROGRAMMING DESCRIPTION
SERIAL DATA PROGRAMMING TIMING
Every bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable (LE)
pin goes to high, stored data is latched according to the group code. The three terminals, CLK, DATA and LE,
contain schmitt trigger circuits to keep the programming from errors caused by noise and etc.
SERIAL DATA PROGRAMMING GROUP
S1T8536 can be controlled through 3 kinds of program group. Each group is identified by selective 2 bits group
codes given below.
MSB-1
MSB
Group Selection
GC1
GC0
0
0
Control Latch
0
1
N-Counter Latch
1
0
R-Counter Latch
1
1
Not Allowed
>100 ns
LSB
LSB+1
LSB+2
>50 ns
>50 ns
MSB-2
MSB-1
MSB
>100 ns
>50 ns
LSB
>50 ns
CLK
DATA
LE
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
19
PROGRAMMING DESCRIPTION
CONTROL DATA PROGRAMMING (Data should be shifted in LSB first)
Charge Pump Polarity
Depending upon VCO characteristics, phase detector polarity should be set accordingly.
When VCO characteristics are like (1), phase detector polarity bit (PDP) should be set low (`0').
When VCO characteristics are like (2), phase detector polarity bit (PDP) should be set high (`1').
Bit
Name
Description
Setting to `0'
Setting to `1'
D0
PDP
Phase detector polarity select.
Negative VCO
Positive VCO
D1
CPI
Charge pump output current select.
+ 1.5mA
+ 4.5mA
D2
CPZ
Charge pump output state select.
Normal operation
High Impedance
D3
RXPD
Receiver power down control.
Receiver `ON'
Receiver `OFF'
D4
TXPD
Transmitter power down control.
Transmitter 'ON'
Transmitter `OFF'
D5
VCOPD
VCO power down control.
VCO `ON'
VCO `OFF'
D6
PLLPD
PLL power down control.
PLL `ON'
PLL `OFF'
D7
OSCPD
Crystal oscillator power down control
Oscillator `ON'
Oscillator `OFF'
D8
TEST0
Test mode control.
See below.
D9
TEST1
Test mode control.
LSB
MSB
group-code
0 0
`
control data
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
G1
G0
VCO
Frequency
VCO
Tuning
Voltage
(1)
negative
(2)
positive
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
20
PROGRAMMING DESCRIPTION
Charge Pump Output State Control
CPZ bit is provided for open loop modulation during TX time slot in TDD (Time Division Duplex) system.
Power Mode Control
Test Mode Control
D2
CPZ
Charge pump output state
VCO operation
0
Normal Closed
loop
1
High impedance
Open Loop
D3
D4
D5
D6
D7
Power down state
RX
PD
TX
PD
VCO
PD
PLL
PD
OSC
PD
Frequency
Doubler
VCO
Regulator
PLL
Regulator
RX
Regulator
TX
Regulator
0
1
0
0
0
ON
ON
ON
ON
OFF
1
0
0
0
0
ON
ON
ON
OFF
ON
1
1
0
0
0
OFF
ON
ON
OFF
OFF
1
1
0
1
0
OFF
ON
ON
OFF
OFF
1
1
1
1
0
OFF
OFF
ON
OFF
OFF
1
1
1
1
1
OFF
OFF
OFF
OFF
OFF
D9
D8
LD Output
TEST1
TEST0
0
0
Lock Detect
0
1
fPLL (VCO / N)
1
0
fREF (OSC / R)
1
1
High
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
21
PROGRAMMING DESCRIPTION
N-COUNTER DIVISION RATIO DATA PROGRAMMING (Data should be shifted in LSB first)
The N-counter consists of the 5-bit swallow counter (A-counter), 8-bit programmable main counter (B-counter) and
dual-modulus prescaler providing 32 / 33 division.
5-Bit Swallow Counter (A-Counter) Division Ratio
A = A4*2^4 + A3*2^3 + A2*2^2 + A1*2^1 + A0*2^0
Division ratio : 0 to 31, A < B
8-Bit Main Counter (B-Counter) Division Ratio
B = B7*2^7 + B6*2^6 + B5*2^5 + B4*2^4 + B3*2^3 + B2*2^2 + B1*2^1 + B0*2^0
Division ratio : 3 to 255, B > A
N-Counter Division Ratio
N = (PXB) + A
P : Modulus of dual modulus prescaler which is 32
B : Division ratio of 8-bit main counter
A : Division ratio of 5-bit swallow counter
Division Ratio (A-Counter)
A4
A3
A2
A1
A0
0
0
0
0
0
0
1
1
0
0
0
0
31
1
1
1
1
1
Division Ratio (B-Counter)
B7
B6
B5
B4
B3
B2
B1
B0
3
1
1
0
0
0
0
0
0
4
0
0
1
0
0
0
0
0
255
1
1
1
1
1
1
1
1
LSB
MSB
group-code
1 0
`
A0
A1
A2
A3
A4
B0
B1
B2
B3
B4
B5
B6
Swallow-counter
B7
G1
G0
(A-counter)
Main-counter
(B-counter)
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
22
PROGRAMMING DESCRIPTION
REFERENCE-COUNTER DIVISION RATIO DATA PROGRAMMING (Data should be shifted in LSB first)
The R-counter consists of the 6-bit reference counter.
6-Bit Reference Counter Division Ratio
R = R5*2^5 + R4*2^4 + R3*2^3 + R2*2^2 + R1*2^1 + R0*2^0
Division ratio : 3 to 63
Example) If a 19.2MHz oscillator is connected, the internal PLL reference frequency is 400KHz,and the VCO
frequency is 1.2GHz,then equation is as follows.
R = X-tal / Reference Frequency
R = 19.2MHz / 400KHz = 48(d) = 110000(b)
The R register setting is 00001101(b).
N = Fvco / Freference
N =1.2GHz / 400KHz = 3000
N = 3000 / 32 = 93.75 , The B(main counter) is 93(d) = 1011101(b)
S = 0.75 * 32 = 24 , The S(swallow counter) is 24(d) = 11000(b)
The N register setting is 000111011101010(b).
Division Ratio
R5
R4
R3
R2
R1
R0
3
1
1
0
0
0
0
4
0
0
1
0
0
0
63
1
1
1
1
1
1
LSB
MSB
group-code
0 1
R0
R1
R2
R3
R4
R5
G1
G0
R-counter
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
S1T8536
23
TEST CIRCUIT
VREGRX
GNDMIX
GNDMIX
MIP
MIN
GNDFD
VREGTX
GNDFD
VCCFD
TXOUT
GNDVCO
VCCVCO
MOP
MON
VCCMIX
VCCMIX
VCCIF
IFP
IFN
GNDIF
GNDIF
GNDQUAD
VCCQUAD
QUADIN
GNDBB
QUADOUT
BUFOUT
DSINN
BUFIN
DSINP
SHO
DSOUT
SHEN
RSSI
CE
OSCI
VREGVCO
VCOP
VCON
GNDPLL
VCCPLL
VREGPLL
CP
LD
CLK
DATA
LE
OSCO
S1T8536X01
24
23
C25
8p
R18
R19
15k
C30
12p
11k
22
21
R15
20
19
C26 15n
R14
12k
18
17
16
C23
10n
TP2
RSSI
15
14
13
12
11
R8 1K
R9 1K
R10 1K
100p
C5
C8
10n
C7
18
R3
VCC
VCC
GND
OUT
GND
VCC
CONT
GND
GND
GND
VSW
MOD
GND
GND
SW SPDT
10
9
8
7
6
5
4
3
2
1
1
3
4
5
2
11
10
9
8
7
12
6
C59
47p
C52
VCC
48
47
46
SMA7
C57
N.C
C54
0.5p
45
L7
660nH
VCC
47p
4.7p
C55
C56
C53
C52
47p
10n
44
43
42
41
C50
47p
C51
4.7p
40
C61
C48
1.2p
SMA
39
38
C46
47p
10n
C47
C32
47p
VCC
C33
4.7p
L3
56n
C31
22p
VC1
10p
25
26
27
28
29
30
31
32
33
34
35
36
VCC
C44
4.7p
47p
C49
C49
U2
VC0-1300GHz
SW1
37
R24
18
4.7p
R20
R1
L1
R5
3.9k
C6
10n
47p
R6
15k
39p
C13
560p
C14
1.2k
R7
15n
C15
?
C60
47p
C9
4.7p
C10
5k
R11
C16
47p
C17
47p
C18
47p
19.2MHz
C21
30pF
C22
20pF
1
2
3
4
5
6
7
1
2
3
4
5
6
7
CNT1
JP1
14
13
12
11
10
9
8
VCC
C19
100p
C20
10p
R12
56k
0
R3
220
C24
47p
C25
4.7n
R16
33k
R17
33k
C27
47p
C28
4.7n
R25
22
R22
33
470nH
C34
27p
C35
27p
C36
0.5p
R21
18
VCC
C37
47p
C38
4.7n
R23
18
4
5
SAFU110.6MSA40T
6
7
8
9
10
3
2
1
C39
0.5p
C40 7p
C41 7p
L5
270nH
L6
270nH
C42
47p
C43
4.7p
VCC
R4
1k
C11
1n
C12
100n
C4
1n
C2
47p
C1
10n
50
330n
L2
330n
R2
50
L2
330n
1.5p
18
S1T8536
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
24
APPLICATION CIRCUIT
VREGRX
GNDMIX
GNDMIX
MIP
MIN
GNDFD
VREGTX
GNDFD
VCCFD
TXOUT
GNDVCO
VCCVCO
MOP
MON
VCCMIX
VCCMIX
VCCIF
IFP
IFN
GNDIF
GNDIF
GNDQUAD
VCCQUAD
QUADIN
GNDBB
QUADOUT
BUFOUT
DSINN
BUFIN
DSINP
SHO
DSOUT
SHEN
RSSI
CE
OSCI
VREGVCO
VCOP
VCON
GNDPLL
VCCPLL
VREGPLL
CP
LD
CLK
DATA
LE
OSCO
S1T8536X01
24
23
C29
8p
R18
R19
15k
C30
12p
11k
22
21
R15
20
19
C26 15n
R14
12k
18
17
16
C23
10n
TP2
RSSI
15
14
13
12
11
R8 1K
R9 1K
R10 1K
100p
C5
C8
10n
C7
18
R3
VCC
10
9
8
7
6
5
4
3
2
1
C59
47p
C52
VCC
48
47
46
SMA
C54
5p
45
L7
660nH
VCC
47p
4.7p
C55
C56
C53
C52
47p
10n
44
43
42
41
C50
47p
C51
4.7p
40
C61
C48
1p
SMA
39
38
C46
47p
10n
C47
C32
47p
VCC
C33
4.7n
L3
56n
C31
22p
VC1
10p
25
26
27
28
29
30
31
32
33
34
35
36
VCC
C44
4.7p
47p
C49
C49
37
R24
18
4.7p
R20
18
R1
10
R4
10
HVC355B
D1
C2
47p
C1
103
C6
10n
47p
R6
5.6k
N.C
C13
680p
C14
4.7k
R7
4.7n
C15
?
C60
5k
R11
C16
47p
C17
47p
C18
47p
19.2MHz
C21
30pF
C22
10pF
1
2
3
4
5
6
7
CNT1
JP1
14
13
12
11
10
9
8
VCC
C19
100p
C20
10n
R12
56k
0
R3
220
C24
47p
C25
4.7n
R16
33k
R17
33k
C27
47p
C28
4.7n
R25
18
R22
33
470nH
C34
27p
C35
27p
C36
0.5p
R21
18
VCC
C37
47p
C38
4.7n
R23
18
4
5
SAFU110.6MSA40T
6
7
8
9
10
3
2
1
C39
0.5p
C40
7p
C41
7p
L5
270nH
C42
47p
C43
4.7p
L12
N.C
L13 1.2nH
Q2
HPFB0420
C68
100p
L15
N.C
RFIN
RFIN
R35
18k
L14
1.2nH
VCC
R34
100
C3
10p
1.8p
C63
L8
N.C
L9
N.C
C11
200p
R32
18k
TxVcc
L10
3.9nH
C57
10p
2.2nH
L11
C62
33p
TxOUT
TxOUT
VC
1 - 3p
L2
1nH
R31
0
C4
2.2p
D2
DIODE
C26
2.2p
L1
1nH
VCO
100p
C12
VREGRX
R28
4.7K
C67
150p
R2
10k
R27
68
TP1
MOD
R5
3.9k
47p
C9
4.7p
C10
TP3
CP
TxVcc
VC2
10p
LE
DATA
CLK
LD
GND
MOD
TxVcc
AFO
SHEN
CE
RXD
GND
RSSI
RxVcc
TP4
RxDATA
VCC
L6
270nH
2.7p
Q1
HPFB0420
R31
100
R2
2k