S3C7044/C7048/P7048
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
The S3C7044/C7048 single-chip CMOS microcontroller has been designed for very high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P7048 is the microcontroller which has 8K-bytes one-time-programmable ROM and the functions are
same to S3C7044/C7048.
With two 8-bit timer/counters, an 8-bit serial I/O interface, and eight software n-channel open-drain I/O pins, the
S3C7044/C7048 offers an excellent design solution for a wide variety of general-purpose applications.
Up to 36 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts
provide fast response to internal and external events.
In addition, the S3C7044/C7048's advanced CMOS technology provides for low power consumption and a wide
operating voltage range.
PRODUCT OVERVIEW
S3C7044/C7048/P7048
1-2
FEATURES SUMMARY
Memory
512
4-bit RAM
4096
8-bit ROM: S3C7044
8192
8-bit ROM: S3C7048
36 I/O Pins
Input only: 4 pins
I/O: 24 pins
N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
Data memory bank 15
8-Bit Basic Timer
4 interval timer functions
Two 8-Bit Timer/Counters
Programmable interval timer
External event counter function
Timer/counters clock outputs to TCLO0 and
TCLO1 pins
Watch Timer
Time interval generation: 0.5 s, 3.9 ms at
4.19 MHz
4 frequency outputs to the BUZ pin
8-Bit Serial I/O Interface
8-bit transmit/receive mode
8-bit receive mode
LSB-first or MSB-first transmission selectable
Bit Sequential Carrier
Supports 16-bit serial data transfer in arbitrary
format
Interrupts
3 external interrupt vectors
4 internal interrupt vectors
2 quasi-interrupts
Power-Down Modes
Idle: Only CPU clock stops
Stop: System clock stops
Oscillation Sources
Crystal or Ceramic for system clock
Oscillation frequency : 0.4 6.0MHz
CPU clock divider circuit (by 4. 8, or 64)
Instruction Execution Times
0.95, 1.91, 15.3
s at 4.19 MHz
0.67, 1.33, 10.7
s at 6.0 MHz
Operating Temperature
- 40
C to 85
C
Operating Voltage Range
1.8 V to 5.5 V (Main)
2.0 V to 5.5 V (OTP)
Package Types
42-pin SDIP, 44-pin QFP
S3C7044/C7048/P7048
PRODUCT OVERVIEW
1-3
FUNCTION OVERVIEW
SAM47 CPU
All S3C7-series microcontrollers have the advanced SAM47 CPU core. The SAM47 CPU can directly address up
to 32K-byte of program memory. The arithmetic logic unit(ALU) performs 4-bit addition, subtraction, logical, and
shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles.
CPU REGISTERS
program counter
A 12-bit program counter (PC) stores addresses for instruction fetches during program execution. Usually, the PC
is incremented by the number of bytes of the fetched instruction. The one instruction fetch that does not
increment the PC is the 1-byte REF instruction which references instruction stored in a look-up table in the ROM.
Whenever a reset operation or an interrupt occurs, bits PC12 though PC0 are set to the vector address.
Stack pointer
An 8-bit stack pointer (SP) stores addresses for stack operation. The stack area is located in general-purpose
data memory bank 0. The SP is 8-bit read/writeable and SP bit 0 must always be logic zero.
During an interrupt or a subroutine call, the PC value and the PSW are written to the stack area. When the
service routine has completed, the values referenced by the stack pointer are restored. Then, the next instruction
is executed.
The stack pointer can access the stack despite data memory access enable flag status. Since the reset value of
the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00H. This sets
the first register of the stack area to data memory location 0FFH.
PROGRAM MEMORY
In its standard configuration, the 4096 x 8-bit (S3C7404), 8192 x 8-bit (S3C7408) ROM is divided into four areas:
16-byte area for vector addresses
96-byte instruction reference area
16-byte general-purpose area (0010 001FH)
3968-byte area for general-purpose program memory (S3C7404)
8064-byte area for general-purpose program memory (S3C7408)
The vector address area is used mostly during reset operation and interrupts. These 16 bytes can alternately be
used as general-purpose ROM.
The REF instruction references 2x1-byte or 2-byte instruction stored in reference area location 0020H 007FH.
REF can also reference three-byte instruction such as JP or CALL. So that a REF instruction can reference these
instruction, however, the JP or CALL must be shortened to a 2-byte format. To do this, JP or CALL is written to
the reference area with the format TJP or TCALL instead of the normal instruction name. Unused location in the
REF instruction look-up area can be allocated to general-purpose use.
PRODUCT OVERVIEW
S3C7044/C7048/P7048
1-4
DATA MEMORY
Overview
The 512 x 4bit data memory has five areas:
32 x 4-bit working register area
224 x 4-bit general-purpose area in bank 0 which is also used as the stack area
256 x 4-bit general-purpose area in bank 1
128 x 4-bit area in bank 15 for memory-mapped I/O addresses
The data memory area is also organized as three memory banks
bank0, bank1, and bank15. You use the
select memory bank instruction (SMB) to select one of the banks as working data memory.
Data stored in RAM location are 1-, 4-, and 8-bit addressable. After a hardware reset, data memory initialization
values must be defined by program code.
Data Memory addressing modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1, or 15. When the
EMB flag is logic zero, only location 00H7FH of bank 0 and bank 15 can be accessed. When the EMB flag is
set to logic one, all three data memory banks can be accessed based on the current SMB value.
Working registers
The RAM's working register area in data memory bank 0 is also divided into four register banks. Each register
bank has eight 4-bit registers. Paired 4-bit registers are 8-bit addressable.
Register A can be used as a 4-bit accumulator and double register EA as an 8-bit extended accumulator; double
registers WX, WL, and HL are used as address pointers for indirect addressing.
To limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for
main programs and banks 1, 2, and 3 for interrupt service routines.
Bit sequential carrier
The bit sequential carrier (BSC) mapped in data memory bank 15 is a 16-bit general register that you can
manipulate using 1-, 4-, and 8-bit RAM control instructions.
Using the BSC register, addresses and bit location can be specified sequentially using 1-bit indirect addressing
instructions. In this way, a program can generate 16-bit data output by moving the bit location sequentially,
incrementing or decrementing the value of the L register. You can also use direct addressing to manipulate data
in the BSC.
S3C7044/C7048/P7048
PRODUCT OVERVIEW
1-5
CONTROL REGISTERS
Program Status Word
The 8-bit program status word (PSW) controls ALU operation and instruction execution sequencing. It is also
used to restore a program's execution environment when an interrupt has been serviced. Program instructions
can always address the PSW regardless of the current value of data memory access enable flags.
Before an interrupt is processed, the PSW is pushed onto the stack in data memory bank 0. When the routine is
completed, PSW values are restored.
IS1
IS0
EMB
ERB
C
SC2
SC1
SC0
Interrupt status flags (IS1, IS0), the enable memory bank and enable register bank flags (EMB, ERB), and the
carry flag ( C ) are 1- and 4-bit read/write or 8-bit read-only addressable. Skip condition flags (SC0SC2) can be
addressed using 8-bit read instructions only.
Select Bank (SB) Register
Two 4-bit location called the SB register store address values used to access specific memory and register
banks: the select memory bank register, SMB, and the select register bank register, SRB.
'SMB n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data
memory address in the SMB register. The 'SMB n' instruction is used to select register bank 0, 1, 2, or 3, and to
store the address data in the SRB.
The instructions 'PUSH SB' and 'POP SB' move SMB and SRB values to and from the stack for interrupts and
subroutines.
CLOCK CIRCUITS
System oscillation circuit generates the internal clock signals for the CPU and peripheral hardwares. The system
clock can use a crystal, ceramic, or RC oscillation source, or an externally-generated clock signal. To drive
S3C7044/C7048 using an external clock source, the external clock signal should be input to Xin, and its inverted
signal to Xout.
A 4-bit power control register is used to enable or disable oscillation, and to select the CPU clock. The internal
system clock signal (fx) can be divided internally to produce three CPU clock frequencies
fx/4, fx/8, or fx/64.
INTERRUPTS
Interrupt requests can be generated internally by on-chip processes (INTB, INTT0, INTT1, and INTS) or
externally by peripheral devices (INT0, INT1, and INT4). There are two quasi-interrupts: INT2 and INTW.
INT2/KS0KS7 detects rising/falling edges of incoming signals and INTW detects time intervals of 0.5 seconds
of 3.91 milliseconds at 4.19MHz. The following components support interrupt processing:
Interrupt enable flags
Interrupt request flags
Interrupt priority registers
Power-down termination circuit
PDF 
ZIP