S3C72K8/P72K8
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to-
320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an
excellent design solution for a wide variety of applications which require LCD functions.
Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C72K8's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The S3C72K8 microcontroller is also available is OTP (one time programmable) version, S3P72K8.
S3P72K8 microcontroller has an one-chop 8 Kbyte one time programmable EPROM instead of masked ROM.
The S3P72K8 is comparable to S3C72K8, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C72K8/P72K8
1-
2
FEATURES
Memory
-- 8 K
8-bit RAM
-- 1,024
4-bit ROM
27 I/O Pins
-- Input only: 4 pins
-- I/O: 15 pins
-- Output: maximum 8 pins for 1-bit level output
(sharing with segment driver outputs)
Comparator
-- Two channel mode: internal reference
(4-bit resolution)
-- One channel mode: external reference
LCD Controller/Driver
-- 40 segments and 8 common terminals
-- 3, 4 and 8 common selectable
-- Internal resistor circuit for LCD bias
-- All dot can be switched on/off
8-Bit Basic Timer
-- 4 interval timer functions
-- Watchdog timer
8-Bit Timer/Counter
-- Programmable 8-bit timer
-- External event counter
-- Arbitrary clock frequency output
-- External clock signal divider
-- Serial I/O interface clock generator
8-Bit Serial I/O Interface
-- 8-bit transmit/receive mode
-- 8-bit receive only mode
-- LSB-first or MSB-first transmission selectable
-- Internal or external clock source
Bit Sequential Carrier
-- Support 16-bit serial data transfer in arbitrary
format
Watch Timer
-- Timer interval generation:
0.5 s, 3.9 ms at 32,768 Hz
-- Four frequency outputs to BUZ pin
-- Clock source generation for LCD
Interrupts
-- Three internal vectored interrupts:
INTB, INTT0, INTS
-- Four external vectored interrupts:
INT0, INT1, INT4, INTK
-- Two quasi-interrupts: INT2, INTW
Memory-Mapped I/O Structure
-- Data memory bank 15
Two Power-Down Modes
-- Idle mode (only CPU clock stops)
-- Stop mode (main system oscillation stops)
-- Subsystem clock stop mode
Oscillation Sources
-- Crystal, ceramic, or External RC for system clock
-- Main system clock frequency: 0.4 MHz6 MHz
-- Subsystem clock frequency: 32,768 kHz
-- CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
-- 0.67 us at 6 MHz (minimum)
-- 0.95
s at 4.19 MHz (minimum)
-- 122
s at 32,768 kHz (minimum)
Operating Temperature
-- 40
C to 85
C
Operating Voltage Range
-- 2.0 V to 5.5 V
Package Type
-- 80-pin QFP
S3C72K8/P72K8
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Program
Status Word
Arithmetic
and
Logic Unit
Instruction Decoder
Internal
Interrupts
RESET
Interrupt
Control
Block
Stack
Pointer
Clock
8 Kbyte
Program
Memory
1024 x 4-Bit
Data Memory
X
IN
XT
IN
Program
Counter
Flags
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
X
OUT
XT
OUT
Watchdog
Timer
Input Port 1
Comparator
I/O Port 0
Watch
Timer
Basic
Timer
SIO
P1.0/INT0/CIN0
P1.1/INT1/CIN1
P1.2/INT2
P1.3/INT4
LCD Driver/
Controller
I/O Port 4
8-Bit
Timer/
Counter
I/O Port 2
I/O Port 3
V
LC1
-V
LC5
COM0-COM7
SEG0-SEG31
P5.0/SEG32-
P5.7/SEG39
P2.0-P2.3
P3.0
P3.1
P3.2/LCDSY
P3.3/CLDCK
P4.0/CLO
P4.1/TCL0
P4.2/TCLO0
Figure 1-1. S3C72K8 Simplified Block Diagram
PRODUCT OVERVIEW
S3C72K8/P72K8
1-
4
PIN ASSIGNMENTS
S3C72K8
(80-QFP-1420C)
P5.6/SEG38
P5.7/SEG39
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
P0.0/
SCK
/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
V
DD
V
SS
X
OUT
X
IN
TEST
XT
IN
XT
OUT
RESET
P1.0/INT0/CIN0
P1.1/INT1/CIN1
P1.2/INT2
P1.3/INT4
P2.0
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM7
COM6
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
COM5
COM4
COM3
COM2
COM1
COM0
TCLO0/P4.2
TCL0/P4.1
CLO/P4.0
LCDCK/P3.3
LCDSY/P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32/P5.0
SEG33/P5.1
SEG34/P5.2
SEG35/P5.3
SEG36/P5.4
SEG37/P5.5
Figure 1-2. S3C72K8 80-QFP Pin Assignment
S3C72K8/P72K8
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C72K8 Pin Descriptions
Pin Name
Pin
Type
Description
Circuit
Type
Pin
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
E2
8
9
10
11
K0/
SCK
K1/SO
K2/SI
K3/BUZ
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit or 4-bit read and test are possible.
The 1-bit unit pull-up resistors are assigned to input
pins by software.
An interrupt is generated by digital input at P1.0,
P1.1.
F4
F4
A3
A3
20
21
22
23
INT0/CIN0
INT1/CIN1
INT2
INT4
P2.0P2.3
I/O
Same as port 0 except that 8-bit read/write and test is
possible.
E2
2427
P3.0
P3.1
P3.2
P3.3
28
29
30
31
LCDSY
LCDCK
P4.0
P4.1
P4.2
I/O
Same as port 0 except that port 4 is 3-bit I/O port.
E2
32
33
34
CLO
TCL0
TCLO0
P5.0P5.7
O
Output port for 1-bit data
H11
75
80,1,2
SEG32
SEG39
SCK
I/O
Serial I/O interface clock signal
E2
8
P0.0/K0
SO
I/O
Serial data output
E2
9
P0.1/K1
SI
I/O
Serial data input
E2
10
P0.2/K2
BUZ
I/O
2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output at
the watch timer clock frequency of 32.768 kHz.
E2
11
P0.3/K3
K0K3
I/O
External interrupt. The triggering edge is selectable.
E2
811
P0.0P0.3
INT0
INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
F4
20
21
P1.0/CIN0
P1.1/CIN1
INT2
I
Quasi-interrupt with detection of rising or falling
edges
A3
22
P1.2
INT4
I
External interrupts with detection of rising and falling
edges
A3
23
P1.3
PRODUCT OVERVIEW
S3C72K8/P72K8
1-
6
Table 1-1. S3C72K8 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Circuit
Type
Pin
Number
Share Pin
CIN0
CIN1
I
2-channel comparator input.
CIN0: comparator input or external reference input
CIN1: comparator input only.
F4
20
21
P1.0/INT0
P1.1/INT1
LCDSY
I/O
LCD synchronization clock output for display
expansion
E2
30
P3.2
LCDCK
I/O
LCD clock output for display expansion
E2
31
P3.3
CLO
I/O
Clock output
E2
32
P4.0
TCL0
I/O
External clock input for timer/counter 0
E2
33
P4.1
TCLO0
I/O
Timer/counter 0 clock output
E2
34
P4.2
SEG32
SEG39
O
LCD segment signal output
H11
75
80,1,2
P5.0P5.7
SEG0
SEG31
O
LCD segment signal output
H6
4374
COM0
COM7
O
LCD common signal output
H6
3542
V
LC1
V
LC5
LCD power supply. Voltage dividing resistors are
assignable by mask option.
37
X
IN
,
X
OUT
Crystal, ceramic or RC oscillator pins for system
clock.
15, 14
XT
IN
,
XT
OUT
Crystal oscillator pins for subsystem clock.
17, 18
V
DD
Main power supply
12
V
SS
Ground
13
RESET
I
Chip reset signal input
B
19
TEST
I
Chip test signal input (must be connected to V
SS
)
16
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode
S3C72K8/P72K8
PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
P-Channel
N-Channel
In
V
DD
Figure 1-3. Pin Circuit Type A
In
V
DD
Pull-Up
Resistor
Enable
P-Channel
Pull-Up
Resistor
Schmitt Trigger
Figure 1-4. Pin Circuit Type A-3
Schmitt Trigger
In
V
DD
Pull-Up
Resistor
Figure 1-5. Pin Circuit Type B
P-Channel
N-Channel
V
DD
Out
Output
Disable
Data
Figure 1-6. Pin Circuit Type 7
PRODUCT OVERVIEW
S3C72K8/P72K8
1-
8
Schmitt Trigger
N-CH
V
DD
Resistor
Enable
V
DD
I/O
PNE
Pull-up
Resistor
P-CH
Output
Disable
Data
Figure 1-7. Pin Circuit Type E-2
I/O
Schmitt Trigger
Resistor Enable
V
DD
Pull-up
Resistor
+
-
EXT-REF
(P1.0 only)
Analog In
Digital In
Comparator
INT-REF
Digital or Analog Selectable
by Software (P1MOD)
Figure 1-8. Pin Circuit Type F-4
S3C72K8/P72K8
PRODUCT OVERVIEW
1-9
Out
V
LC3
SEG/COM Data
V
LC2
Output Disable
V
DD
V
LC1
V
LC4
V
LC5
Figure 1-9. Pin Circuit Type H-5
PRODUCT OVERVIEW
S3C72K8/P72K8
1-
10
Out
SEG/COM
V
LC1
V
LC2
V
DD
V
LC4
V
LC3
V
LC5
Figure 1-10. Pin Circuit Type H-6
P-CH
N-CH
V
DD
Out
Output Disable 1
Data
Circuit
Type H-5
N-CH
SEG
Output Disable 2
Figure 1-11. Pin Circuit Type H-11
S3C72K8/P72K8
ELECTRICAL DATA
15-1
15
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72K8 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- Main system clock oscillator characteristics
-- Subsystem clock oscillator characteristics
-- I/O capacitance
-- Comparator electrical characteristics
-- A.C. electrical characteristics
-- Operating voltage range
Stop Mode Characteristics and Timing Waveforms
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
-- A.C timing measurement points
-- Clock timing measurement at X
IN
-- Clock timing measurement at XT
IN
-- TCL timing
-- Input timing for
RESET
signal
-- Input timing for external interrupts
-- Serial data transfer timing
ELECTRICAL DATA
S3C72K8/P72K8
15-2
Table 15-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
I1
All I/O pins active
0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
0.3 to V
DD
+ 0.3
V
Output Current High
I
OH
One I/O pin active
15
mA
All I/O pins active
35
Output Current Low
I
OL
One I/O pin active
+ 30 (Peak value)
mA
+ 15
(note)
All I/O port, total
+ 100 (Peak value)
+ 60
(note)
Operating Temperature
T
A
40 to + 85
C
Storage Temperature
T
stg
65 to + 150
C
NOTE: The values for Output Current Low ( I
OL
) are calculated as Peak Value
Duty .
S3C72K8/P72K8
ELECTRICAL DATA
15-3
Table 15-2. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
V
IH1
Ports 2, 3, P4.0 and P4.2
0.7 V
DD
V
DD
V
V
IH2
Ports 0, 1, P4.1 and
RESET
0.8 V
DD
V
DD
V
IH3
X
IN
, X
OUT
and
XT
IN
V
DD
0.1
V
DD
Input Low
Voltage
V
IL1
Ports 2, 3, P4.0 and P4.2
0.3 V
DD
V
V
IL2
Ports 0, 1, P4.1 and
RESET
0.2 V
DD
V
IL3
X
IN
, X
OUT
and
XT
IN
0.1
Output High
Voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 3 mA
Ports 0, 2, 3 and 4
V
DD
2.0
V
DD
0.4
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 100
A
Ports 5
V
DD
2.0
Output Low
Voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA
Ports 0, 2, 3 and 4
0.4
2
V
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OH
= 100
A
Ports 5
1
Input High
Leakage
Current
I
LIH1
V
IN
= V
DD
All input pins except those specified
below for I
LIH2
3
A
I
LIH2
V
IN
= V
DD
X
IN
, X
OUT
and
XT
IN
20
Input Low
Leakage
Current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
, XT
IN
,
and
RESET
3
A
I
LIL2
V
IN
= 0 V
X
IN
, X
OUT
and XT
IN
20
Output High
Leakage
Current
I
LOH
V
O
= V
DD
All output pins
3
A
Output Low
Leakage
Current
I
LOL
V
O
= 0 V
All output pins
3
A
ELECTRICAL DATA
S3C72K8/P72K8
15-4
Table 15-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Pull-Up
Resistor
R
LI
V
IN
= 0 V; V
DD
= 5 V
10 %
Ports 0-4
15
40
80
k
V
DD
= 3 V
10 %
30
80
200
R
L2
V
IN
= 0 V; V
DD
= 5 V
10 %
RESET
150
220
350
V
DD
= 3 V
10 %
300
400
800
LCD Voltage
Dividing
Resistor
R
LCD
40
60
90
k
|V
DD
-COM
i
|
Voltage Drop
(i = 0-7)
V
DC
V
DD
= 2.7 V to 5.5 V
15
A per common pin
120
mV
|V
DD
-SEGx|
Voltage Drop
(x = 0-39)
V
DS
V
DD
= 2.7 V to 5.5 V
15
A per segment pin
120
V
LC1
Output
Voltage
V
LC2
V
DD
= 2.0 V to 5.5 V
(1)
LCD clock = 0 Hz, V
LC5
=
0 V
0.8 V
DD
0.2
0.8 V
DD
0.8 V
DD
+ 0.2
V
V
LC2
Output
Voltage
V
LC3
0.6 V
DD
0.2
0.6 V
DD
0.6 V
DD
+ 0.2
V
LC3
Output
Voltage
V
LC4
0.4 V
DD
0.2
0.4 V
DD
0.4 V
DD
+ 0.2
V
LC4
Output
Voltage
V
LC5
0.2 V
DD
0.2
0.2 V
DD
0.2 V
DD
+ 0.2
S3C72K8/P72K8
ELECTRICAL DATA
15-5
Table 15-2. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
C to + 85
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
(1)
I
DD1
(2)
V
DD
= 5 V
10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
3.5
2.5
8.0
5.5
mA
V
DD
= 3 V
10%
6.0 MHz
4.19 MHz
1.8
1.3
4.0
3.0
I
DD2
(2)
Idle mode
V
DD
= 5 V
10%
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1.3
1.2
2.5
1.8
V
DD
= 3 V
10%
6.0 MHz
4.19 MHz
0.5
0.4
1.5
1.0
I
DD3
(3)
V
DD
= 3 V
10%
32 kHz crystal oscillator
15
30
I
DD4
(3)
Idle mode; V
DD
= 3 V
10%
32 kHz crystal oscillator
6
15
I
DD5
Stop mode;
V
DD
= 5 V
10%
SCMOD =
0000B
XT
IN
= 0V
2.5
5
Stop mode;
V
DD
= 3 V
10%
0.5
3
V
DD
= 5 V
10%
SCMOD =
0100B
0.2
3
V
DD
= 3 V
10%
0.1
2
NOTES:
1.
Currents in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
output port drive currents, comparator.
2.
Data includes power consumption for subsystem clock oscillation.
3.
When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
4.
Every values in this table is measured when the power control register (PCON) is set to "0011B".
ELECTRICAL DATA
S3C72K8/P72K8
15-6
Table 15-3. Main System Clock Oscillator Characteristics
(T
A
= 40
C + 85
C, V
DD
= 2.0 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
X
IN
C1
C2
X
OUT
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
Stabilization occurs
when V
DD
is equal to
the minimum
oscillator voltage
range.
4
ms
Crystal
Oscillator
X
IN
C1
C2
X
OUT
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
V
DD
= 4.5 V to 5.5 V
10
ms
V
DD
= 2.7 V to 4.5 V
30
External
Clock
X
IN
X
OUT
X
IN
input frequency
(1)
0.4
6.0
MHz
X
IN
input high and low
level width (t
XH
, t
XL
)
83.3
1250
ns
RC
Oscillator
X
IN
X
OUT
R
Frequency
R = 10 k
,
V
DD
= 5 V
2
MHz
R = 30 k
,
V
DD
= 3 V
1
NOTES:
1.
Oscillation frequency and X
IN i
nput frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
S3C72K8/P72K8
ELECTRICAL DATA
15-7
Table 15-4. Subsystem Clock Oscillator Characteristics
(T
A
= 40
C + 85
C, V
DD
= 2.0 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XT
IN
C1
C2
XT
OUT
Oscillation frequency
(1)
32
32.768
35
kHz
Stabilization time
(2)
V
DD
= 4.5 V to 5.5 V
1.0
2
s
V
DD
= 2.0 V to 4.5 V
10
External
Clock
XT
IN
XT
OUT
XT
IN
input frequency
(1)
32
100
kHz
XT
IN
input high and low
level width (t
XTL
, t
XTH
)
5
15
s
NOTES:
1.
Oscillation frequency and XT
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
ELECTRICAL DATA
S3C72K8/P72K8
15-8
Table 15-5. Input/Output Capacitance
(T
A
= 25
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured
pins are returned to V
SS
15
pF
Output
Capacitance
C
OUT
15
pF
I/O Capacitance
C
IO
15
pF
Table 15-6. Comparator Electrical Characteristics
(T
A
= 40
C + 85
C, V
DD
= 4.0 V to 5.5 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input Voltage Range
0
V
DD
V
Reference Voltage Range
V
REF
0
V
DD
V
Input Voltage Accuracy
V
CIN
150
mV
Input Leakage Current
I
CIN
, I
REF
3
3
A
S3C72K8/P72K8
ELECTRICAL DATA
15-9
Table 15-7. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
(note)
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
s
V
DD
= 2.0 V to 5.5 V
0.95
64
With subsystem clock (fxt)
114
122
125
TCL0 Input
Frequency
f
TI0
,
f
TI1
V
DD
= 2.7 V to 5.5 V
0
1.5
MHz
V
DD
= 2.0 V to 5.5 V
1
TCL0 Input High,
Low Width
t
TIH0
,
t
TIL0
t
TIH1
, t
TIL1
V
DD
= 2.7 V to 5.5 V
0.48
s
V
DD
= 2.0 V to 5.5 V
1.8
SCK
Cycle Time
t
KCY
V
DD
= 2.7 V to 5.5 V
External
SCK
source
800
ns
Internal
SCK
source
650
V
DD
= 2.0 V to 5.5 V
External
SCK
source
3200
Internal
SCK
source
3800
SCK
High, Low
Width
t
KH
, t
KL
V
DD
= 2.7 V to 5.5 V
External
SCK
source
325
ns
Internal
SCK
source
t
KCY
/2 50
V
DD
= 2.0 V to 5.5 V
External
SCK
source
1600
Internal
SCK
source
t
KCY
/
2 150
SI Setup Time to
SCK
High
t
SIK
V
DD
= 2.7 V to 5.5 V
External
SCK
source
100
ns
Internal
SCK
source
150
V
DD
= 2.0 V to 5.5 V
External
SCK
source
150
Internal
SCK
source
500
SI Hold Time to
SCK
High
t
KSI
V
DD
= 2.7 V to 5.5 V
External
SCK
source
400
ns
Internal
SCK
source
400
V
DD
= 2.0 V to 5.5 V
External
SCK
source
600
Internal
SCK
source
500
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
ELECTRICAL DATA
S3C72K8/P72K8
15-10
Table 15-7. A.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Delay for
SCK
to SO
t
KSO
V
DD
= 2.7 V to 5.5 V
External
SCK
source
300
ns
Internal
SCK
source
250
V
DD
= 2.0 V to 5.5 V
External
SCK
source
1000
Internal
SCK
source
1000
Interrupt Input
High, Low Width
t
INTH
, t
INTL
INT0, INT1, INT2, INT4,
K0K3
10
s
RESET
Input Low
Width
t
RSL
Input
10
s
1.5 MHz
CPU Clock
1.05 MHz
15.6 kHz
Main Oscillator Frequency
(Divided by 4)
4.2 MHz
6 MHz
1
2
3
4
5
6
7
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
2.0 V 2.7 V
Figure 15-1. Standard Operating Voltage Range
S3C72K8/P72K8
ELECTRICAL DATA
15-11
Table 15-8. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
2.0
5.5
V
Data retention supply current
I
DDDR
V
DDDR
= 2.0 V
0.1
10
A
Release signal set time
t
SREL
0
s
Oscillator stabilization wait
time
(1)
t
WAIT
Released by
RESET
2
17
/ fx
ms
Released by interrupt
(2)
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
ELECTRICAL DATA
S3C72K8/P72K8
15-12
TIMING WAVEFORMS
Execution of
STOP Instrction
Internal
RESET
Operation
~ ~
V
DDDR
~ ~
Stop Mode
Idle Mode
Normal Mode
Data Retention Mode
t
SREL
t
WAIT
RESET
V
DD
Figure 15-2. Stop Mode Release Timing When Initiated By
RESET
RESET
Execution of
STOP Instrction
V
DDDR
~ ~
Data Retention Mode
V
DD
Normal Mode
~ ~
Stop Mode
Idle Mode
t
SREL
t
WAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 15-3. Stop Mode Release Timing When Initiated By Interrupt Request
S3C72K8/P72K8
ELECTRICAL DATA
15-13
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Measurement
Points
Figure 15-4. A.C. Timing Measurement Points (Except for X
IN
and XT
IN
)
X
IN
t
XH
t
XL
1/fx
V
DD
- 0.1 V
0.1 V
Figure 15-5. Clock Timing Measurement at X
IN
XT
IN
t
XTH
t
XTL
1/fxt
V
DD
- 0.1 V
0.1 V
Figure 15-6. Clock Timing Measurement at XT
IN
ELECTRICAL DATA
S3C72K8/P72K8
15-14
TCL0
t
TIH
t
TIL
1/f
TI
0.8 V
DD
0.2 V
DD
Figure 15-7. TCL Timing
RESET
t
RSL
0.2 V
DD
Figure 15-8. Input Timing for
RESET
RESET
Signal
INT0, 1, 2, 4,
K0 to K3
t
INTH
t
INTL
0.8 V
DD
0.2 V
DD
Figure 15-9. Input Timing for External Interrupts and Quasi-Interrupts
S3C72K8/P72K8
ELECTRICAL DATA
15-15
Output Data
Input Data
SCK
t
KH
t
KCY
t
KL
0.8 V
DD
0.2 V
DD
t
KSO
t
SIK
t
KSI
0.8 V
DD
0.2 V
DD
SI
SO
Figure 15-10. Serial Data Transfer Timing
S3C72K8/P72K8
MECHANICAL DATA
16-1
16
MECHANICAL DATA
OVERVIEW
The S3C72K8 microcontroller is currently available in a 80-pin QFP package.
80-QFP-1420C
#80
20.00
0.20
23.90
0.30
14.00
0.20
17.90
0.30
#1
0.80
0.35
+ 0.10
NOTE: Dimensions are in millimeters.
0.15 MAX
(0.80)
0.15
+ 0.10
- 0.05
0-8
0.10 MAX
0.80
0.20
0.05 MIN
2.65
0.10
3.00 MAX
0.80
0.20
Figure 16-1. 80-QFP-1420C Package Dimensions
S3C72K8/P72K8
S3P72K8 OTP
17-1
17
S3P72K8 OTP
OVERVIEW
The S3P72K8 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the S3C72K8
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P72K8 is fully compatible with the S3C72K8, both in function and in pin configuration except ROM size.
Because of its simple programming requirements, the S3P72K8 is ideal for use as an evaluation chip for the
S3C72K8.
S3P72K8 OTP
S3C72K8/P72K8
17-2
S3P72K8
(80-QFP-1420C)
P5.6/SEG38
P5.7/SEG39
V
LC1
V
LC2
V
LC3
V
LC4
V
LC5
P0.0/
SCK
/K0
P0.1/SO/K1
SDAT/P0.2/SI/K2
SCLK/P0.3/BUZ/K3
V
DD
/V
DD
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST
XT
IN
XT
OUT
RESET
RESET/RESET
P1.0/INT0/CIN0
P1.1/INT1/CIN1
P1.1/INT2
P1.3/INT4
P2.0
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM7
COM6
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
COM5
COM4
COM3
COM2
COM1
COM0
TCLO0/P4.2
TCL0/P4.1
CLO/P4.0
LCDCK/P3.3
LCDSY/P3.2
P3.1
P3.0
P2.3
P2.2
P2.1
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32/P5.0
SEG33/P5.1
SEG34/P5.2
SEG35/P5.3
SEG36/P5.4
SEG37/P5.5
Figure 17-1. S3P72K8 Pin Assignments (80-QFP Package)
S3C72K8/P72K8
S3P72K8 OTP
17-3
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.2
SDAT
10
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P0.3
SCLK
11
I
Serial clock pin. Input only pin.
TEST
V
PP
16
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET
RESET
19
I
Chip Initialization
V
DD
/V
SS
V
DD
/V
SS
12/13
I
Logic power supply pin. V
DD
should be tied to +5
V during programming.
Table 17-2. Comparison of S3P72K8 and S3C72K8 Features
Characteristic
S3P72K8
S3C72K8
Program Memory
8-Kbyte EPROM
8-Kbyte mask ROM
Operating Voltage (V
DD
)
2.0 V to 5.5 V
2.0 V to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5V
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P72K8, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 17-3 below.
Table 17-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3P72K8 OTP
S3C72K8/P72K8
17-4
NOTES
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