S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
OVERVIEW
The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C72N2/C72N4
offers an excellent design solution for a wide variety of applications that require LCD functions.
Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast
response to internal and external events. In addition, the S3C72N2/C72N4 's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.
OTP
The S3C72N2/C72N4 microcontroller is also available in OTP (One Time Programmable) version, S3P72N4 .
The S3P72N4 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM.
The S3P72N4 is comparable to S3C72N2/C72N4, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
1-
2
FEATURES
Memory
-- 288
4-bit RAM
-- 2048
8-bit ROM (S3C72N2)
-- 4096
8-bit ROM (S3C72N4)
I/O Pins
-- Input only: 4 pins
-- I/O: 12 pins
-- Output: 8 pins sharing with segment driver
outputs
LCD Controller/Driver
-- Maximum 16-digit LCD direct drive capability
-- 32 segment, 4 common pins
-- Display modes: Static, 1/2 duty (1/2 bias)
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
8-Bit Basic Timer
-- Programmable interval timer
-- Watchdog timer
8-Bit Timer/Counter
-- Programmable 8-bit timer
-- External event counter
-- Arbitrary clock frequency output
Watch Timer
-- Real-time and interval time measurement
-- Four frequency outputs to BUZ pin
-- Clock source generation for LCD
Bit Sequential Carrier
-- Support 16-bit serial data transfer in arbitrary
format
Interrupts
-- Two internal vectored interrupts
-- Two external vectored interrupts
-- Two quasi-interrupts
Memory-Mapped I/O Structure
-- Data memory bank 15
Two Power-Down Modes
-- Idle mode (only CPU clock stops)
-- Stop mode (main or sub system oscillation stops)
Oscillation Sources
-- Crystal, ceramic, or RC for main system clock
-- Crystal or external oscillator for subsystem clock
-- Main system clock frequency: 4.19 MHz (typical)
-- Subsystem clock frequency: 32.768 kHz
-- CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
-- 0.95, 1.91, 15.3 s at 4.19 MHz (main)
-- 122 s at 32.768 kHz (subsystem)
Operating Temperature
-- 40
C to 85
C
Operating Voltage Range
-- 2.0 V to 5.5 V at 4.19 MHz
-- 1.8 V to 5.5 V at 3 MHz
Package Type
-- 64-pin QFP
S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Arithmetic
and
Logic Unit
8-Bit Timer/
Counter0
I/O Port 6
INT0, INT1, INT2
P2.0/TCLO0
P6.0-P6.3/
KS0-KS3
Output Port 8
Instruction Decoder
Interrupt
Control
Block
Interrupt
Control
Block
Program
Counter
Instruction
Register
Program
Status
Word
Stack
Pointer
RESET
Xin
XTin
Xout
XTout
288 x 4-Bit
Data Memory
2/4 KByte
Program
Memory
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
I/O Port 3
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
I/O Port 2
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0
Input
Port 1
BIAS
LCD
Driver/
Controller
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23
P8.0-P8.7/
SEG24-SEG31
P1.3/TCL0
P8.0-P8.7
SEG24-SEG31
Watch
Timer
P2.3/BUZ
Basic
Timer
Watchdog
Timer
Internal
Interrupts
Figure 1-1. S3C72N2/C72N4 Simplified Block Diagram
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
1-
4
PIN ASSIGNMENTS
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
V
DD
V
SS
Xout
Xin
TEST
XTin
XTout
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
S3C72N2
S3C72N4
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
64
63
62
61
60
59
58
57
56
55
54
53
52
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
20
21
22
23
24
25
26
27
28
29
30
31
32
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7
Figure 1-2. S3C72N2/C72N4 64-QFP Pin Assignment
S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C72N2/C72N4 Pin Descriptions
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit or 4-bit read and test is possible.
4-bit pull-up resistors are software
assignable.
17
18
19
20
INT0
INT1
INT2
TCL0
Input
A-4
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is
possible.
4-bit pull-up resistors are software
assignable.
21
22
23
24
TCLO0
CLO
BUZ
Input
D
P3.0
P3.1
P3.2
P3.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test is
possible.
Each individual pin can be specified as
input or output. 4-bit pull-up resistors are
software assignable.
25
26
27
28
LCDCK
LCDSY
Input
D
P6.0P6.3
I/O
4-bit I/O ports. Pins are individually
software configurable as input or output.
1-bit and 4-bit read/write and test is
possible. 4-bit pull-up resistors are
software assignable.
2932
KS0KS3
Input
D
P8.0P8.7
O
Output port for 1-bit data (for use as
CMOS driver only)
4033
SEG24
SEG31
Output
H-1
SEG0SEG23
O
LCD segment signal output
6441
Output
H
SEG24SEG31
O
LCD segment signal output
4033
P8.0P8.7
Output
H-1
COM0COM3
O
LCD common signal output
14
Output
H
V
LC0
V
LC2
LCD power supply.
Built-in voltage dividing resistors
68
BIAS
LCD power control
5
LCDCK
I/O
LCD clock output for display expansion
25
P3.0
Input
D
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
1-
6
Table 1-1. S3C72N2/C72N4 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Number
Share
Pin
Reset
Value
Circuit
Type
LCDSY
I/O
LCD synchronization clock output for
LCD display expansion
26
P3.1
Input
D
TCL0
I
External clock input for timer/counter 0
20
P1.3
Input
A-4
TCLO0
I/O
Timer/counter 0 clock output
21
P2.0
Input
D
INT0
INT1
I
External interrupt. The triggering edge for
INT0 and INT1 is selectable. Only INT0 is
synchronized with the system clock.
17
18
P1.0
P1.1
Input
A-4
INT2
I
Quasi-interrupt with detection of rising
edge signals.
19
P1.2
Input
A-4
KS0KS3
I/O
Quasi-interrupt input with falling edge
detection.
2932
P6.0P6.3
Input
D
CLO
I/O
CPU clock output
23
P2.2
Input
D
BUZ
I/O
2, 4, 8 or 16 kHz frequency output for
buzzer sound with 4.19 MHz main system
clock or 32.768 kHz subsystem clock.
24
P2.3
Input
D
X
IN
,
X
OUT
Crystal, ceramic or RC oscillator pins for
main system clock. (For external clock
input, use X
IN
and input X
IN
's reverse
phase to X
OUT
)
12,11
XT
IN
,
XT
OUT
Crystal oscillator pins for subsystem
clock. (For external clock input, use XT
IN
and input XT
IN
's reverse phase to XT
OUT
)
14,15
V
DD
Main power supply
9
V
SS
Ground
10
RESET
Reset signal
16
Input
B
TEST
Test signal input (must be connected to
V
SS
)
13
NOTE: Pull-up resistors for all I/O ports automatically disabled if they are configured to output mode.
S3C72N2/C72N4/P72N4
PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
V
DD
P-CHANNEL
IN
N-CHNNEL
Figure 1-3. Pin Circuit Type A
SCHMITT TRIGGER
V
DD
IN
P-CHANNEL
PULL-UP
RESISTOR
RESISTOR
ENABLE
Figure 1-4. Pin Circuit Type A-4 (P1)
V
DD
P-CHANNEL
DATA
OUTPUT
DISABLE
N-CHANNEL
OUT
Figure 1-5. Pin Circuit Type C
P-CHANNEL
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
CIRCUIT TYPE A
I/O
V
DD
CIRCUIT
TYPE C
Figure 1-6. Pin Circuit Type D (P2, P3, and P6)
PRODUCT OVERVIEW
S3C72N2/C72N4/P72N4
1-
8
V
LC0
V
LC1
LCD SEGMENT/
COMMON DATA
V
LC2
OUT
Figure 1-7. Pin Circuit Type H (SEG/COM)
V
LC0
V
LC1
LCD SEGMENT/
& PORT 8 DATA
V
LC2
V
DD
OUT
Figure 1-8. Pin Circuit Type H-1 (P8)
IN
SCHMITT TRIGGER
V
DD
Figure 1-9. Pin Circuit Type B (
RESET
)
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
13-1
13
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C72N2/C72N4 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
STANDARD ELECTRICAL CHARACTERISTICS
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- Main system clock oscillator characteristics
-- Subsystem clock oscillator characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Operating voltage range
MISCELLANEOUS TIMING WAVEFORMS
-- A.C timing measurement point
-- Clock timing measurement at X
IN
-- Clock timing measurement at XT
IN
-- TCL0 timing
-- Input timing for
RESET
-- Input timing for external interrupts
STOP MODE CHARACTERISTICS AND TIMING WAVEFORMS
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
13-2
Table 13-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
I1
All I/O ports
0.3 to V
DD
+ 0.3
Output Voltage
V
O
0.3 to V
DD
+ 0.3
Output Current High
I
OH
One I/O port active
15
mA
All I/O ports active
30
Output Current Low
I
OL
One I/O port active
+ 30 (Peak value)
+ 15
(note)
Total value for ports 2 and 3
+ 60 (Peak value)
+ 20
(note)
Total value for port 6
+ 50
+ 20
(note)
Operating Temperature
T
A
40 to + 85
C
Storage Temperature
T
stg
65 to + 150
NOTE: The values for Output Current Low ( I
OL
) are calculated as Peak Value
Duty .
Table 13-2. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input high
voltage
V
IH1
All input pins except those
specified below for V
IH2
, V
IH3
0.7 V
DD
V
DD
V
V
IH2
Ports 1, 6, and
RESET
0.8 V
DD
V
DD
V
IH3
X
IN
, X
OUT
, and XT
IN
V
DD
0.1
V
DD
Input low
V
IL1
Ports 2 and 3
0.3 V
DD
V
voltage
V
IL2
Ports 1, 6 and
RESET
0.2 V
DD
V
IL3
X
IN
, X
OUT,
and XT
IN
0.1
Output high
voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
Ports 2, 3, 6 and BIAS
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 100 A Port 8 only
V
DD
2.0
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
13-3
Table 13-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output low
voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA, Ports 2, 3, 6
0.4
2
V
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OL
= 100 A; Port 8 only
1
Input high
leakage
current
I
LIH1
V
IN
= V
DD
All input pins except those
specified below for I
LIH2
3
A
I
LIH2
V
IN
= V
DD
X
IN
, X
OUT
and XT
IN
20
Input low
leakage
current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
,
and XT
IN
3
I
LIL2
V
IN
= 0 V
X
IN
, X
OUT
, and XT
IN
20
Output high
leakage
current
I
LOH1
V
OUT
= V
DD
All output pins
3
A
Output low
leakage
current
I
LOL
V
OUT
= 0 V
All output pins
3
Pull-up
resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Ports 1, 2, 3, 6
25
50
100
K
V
DD
= 3 V
50
100
200
R
L2
V
IN
= 0 V; V
DD
= 5 V
RESET
100
250
400
V
DD
= 3 V
200
500
800
LCD voltage
dividing
resistor
R
LCD
T
A =
25
C
120
170
220
COM output
R
COM
V
DD
= 5 V
-
3
6
impedance
V
DD
= 3 V
5
15
SEG output
R
SEG
V
DD
= 5 V
3
6
impedance
V
DD
= 3 V
5
15
COM output
voltage
deviation
V
DC
V
DD
= 5 V (V
LC0
-COMi)
Io =
15uA (i= 0-3)
45
90
mV
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
13-4
Table 13-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
SEG output
voltage
deviation
V
DS
V
DD
= 5 V (V
LC0
-SEGi)
Io =
15uA (i= 0-31)
45
90
mV
VLC0 Output
voltage
V
LC0
T
A =
25
C
0.6V
DD
0.2
0.6VDD
0.6V
DD
+ 0.2
V
VLC1 Output
voltage
V
LC1
T
A =
25
C
0.4V
DD
0.2
0.4VDD
0.4V
DD
+ 0.2
VLC2 Output
voltage
V
LC2
T
A =
25
C
0.2V
DD
0.2
0.2VDD
0.2V
DD
+ 0.2
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
13-5
Table 13-2. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
(1)
I
DD1
(2)
Main operating:
V
DD
= 5 V
10%
CPU = fx/4
SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
3.5
2.5
8
5.5
mA
V
DD
= 3 V
10%
6.0 MHz
4.19 MHz
1.6
1.2
4
3
I
DD2
(2)
Main idle mode;
V
DD
= 5 V
10%
CPU = fx/4
SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1
0.9
2.5
2
V
DD
= 3 V
10%
6.0 MHz
4.19 MHz
0.5
0.4
1.0
0.8
I
DD3
Sub operating:
V
DD
= 3 V
10%
CPU = fxt/4,
SCMOD = 1001B
32 kHz crystal oscillator
15
30
A
I
DD4
Sub idle mode:
V
DD
= 3 V
10%
CPU = fxt/4, SCMOD = 1001B
32 kHz crystal oscillator
6
15
I
DD5
Stop mode:
VDD = 5V
10%
CPU=fxt/4, SCMOD = 1101B
I
DD6
(3)
Stop mode:
V
DD
= 5 V
10%
CPU = fx/4, SCMOD = 0100B
0.5
3
NOTES:
1.
D.C. electrical values for supply current (I
DD1
to I
DD6
) do not include current drawn through internal pull-up resistors
and through LCD voltage dividing resistors.
2.
Data includes the power consumption for sub-system clock oscillation.
3.
When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The main-
system clock oscillation stops by the STOP instruction.
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
13-6
Table 13-3. Main System Clock Oscillator Characteristics
(T
A
= 40
C + 85
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
X
IN
X
OUT
C1
C2
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
Stabilization occurs
when V
DD
is equal to
the minimum oscillator
voltage range.
4
ms
Crystal
Oscillator
C1
C2
X
IN
X
OUT
Oscillation frequency
(1)
0.4
6.0
MHz
Stabilization time
(2)
V
DD
= 4.5 V to 5.5 V
10
ms
V
DD
= 1.8 V to 4.5 V
30
External
Clock
X
IN
X
OUT
X
IN
input frequency
(1)
0.4
6.0
MHz
X
IN
input high and low
level width (t
XH
, t
XL
)
83.3
ns
RC
Oscillator
R
X
IN
X
OUT
Frequency
(1)
V
DD
= 5 V
R = 20 K
, V
DD
= 5 V
R = 39 K
, V
DD
= 3 V
0.4
-
2.0
1.0
2
MHz
NOTES:
1.
Oscillation frequency and X
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
13-7
Table 13-4. Subsystem Clock Oscillator Characteristics
(T
A
= 40
C + 85
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XT
IN
XT
OUT
C1
C2
Oscillation frequency
(1)
32
32.768
35
kHz
Stabilization time
(2)
V
DD
= 4.5 V to 5.5 V
1.0
2
s
V
DD
= 1.8 V to 4.5 V
10
External
Clock
XT
IN
XT
OUT
XT
IN
input frequency
(1)
32
100
KHz
XT
IN
input high and
low level width (t
XTL
,
t
XTH
)
5
15
s
NOTES:
1.
Oscillation frequency and XT
IN
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs.
Table 13-5. Input/Output Capacitance
(T
A
= 25
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
15
pF
Output
capacitance
C
OUT
15
pF
I/O capacitance
C
IO
15
pF
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
13-8
Table 13-6. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction cycle
t
CY
V
DD
= 2.7 V to 5.5 V
0.67
64
s
time
(1)
V
DD
= 1.8 V to 5.5 V
0.95
64
With subsystem clock (fxt)
114
122
125
TCL0 input
f
TI0
V
DD
= 2.7 V to 5.5 V
0
1.5
MHz
frequency
V
DD
= 1.8 V to 5.5 V
1
MHz
TCL0 input high,
t
TIH0
,
t
TIL0
V
DD
= 2.7 V to 5.5 V
0.48
s
low width
V
DD
= 1.8 V to 5.5 V
1.8
Interrupt input
t
INTH
, t
INTL
INT0
(2)
s
high, low width
INT1, INT2, KS0KS3
10
RESET
Input Low
Width
t
RSL
Input
10
s
NOTES:
1.
Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock (fx) source.
2.
Minimum value for INT0 is based on a clock of 2t
CY
or 128/fx as assigned by the IMOD0 register setting.
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
13-9
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
1
SUPPLY VOLTAGE (V)
250 kHz
500 kHz
15.6 kHz
CPU CLOCK
750 kHz
1.0475 MHz
1.5 MHz
2
3
4
5
6
7
Main OSC. Freq.
3 MHz
4.19 MHz
6 MHz
Figure 13-1. Standard Operating Voltage Range
Table 13-7. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
Normal operation
1.5
6.5
V
Data retention supply current
I
DDDR
V
DDDR
= 2.0 V
0.1
1
A
Release signal set time
t
SREL
Normal operation
0
s
Oscillator stabilization wait
t
WAIT
Released by
RESET
2
17
/ fx
ms
time
(1)
Released by interrupt
(2)
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-
up.
2.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
13-10
TIMING WAVEFORMS
t
SREL
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
MODE
Figure 13-2. Stop Mode Release Timing When Initiated By
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL
OPERATING
MODE
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated By Interrupt Request
S3C72N2/C72N4/P72N4
ELECTRICAL DATA
13-11
0.8
V
DD
0.2
V
DD
0.8
V
DD
0.2
V
DD
MEASUREMENT
POINTS
Figure 13-4. A.C. Timing Measurement Points (Except for X
in
and XT
in
)
Xin
t
XL
t
XH
1 / fx
V
DD
0.1 V
0.1 V
Figure 13-5. Clock Timing Measurement at X
in
XTin
t
XTL
t
XTH
1 / fxt
V
DD
0.1 V
0.1 V
Figure 13-6. Clock Timing Measurement at XT
in
ELECTRICAL DATA
S3C72N2/C72N4/P72N4
13-12
TCL0
t
TIL0
t
TIH0
1 / f TI0
0.8 V
DD
0.2 V
DD
Figure 13-7. TCL0 Timing
RESET
tRSL
0.2 VDD
Figure 13-8. Input Timing for
RESET
Signal
INT0, 1, 2, 4
KS0 to KS3
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 13-9. Input Timing for External Interrupts and Quasi-Interrupts
S3C72N2/C72N4/P72N4
MECHANICAL DATA
14
MECHANICAL DATA
OVERVIEW
The S3C72N2/C72N4 microcontroller is available in a 64-pin QFP package (Samsung: 64-QFP-1420F).
Package dimensions are shown in Figure 14-1.
NOTE: Dimensions are in millimeters.
17.90 0.3
14.00 0.2
(1.00
)
64-QFP-1420F
23.90 0.3
#64
(1.00)
#1
0.40
+0.10
- 0.05
0.15MAX
0.80
0.20
2.65
0.10
0.05~0.25
3.00 MAX
0.15
+0.10
- 0.05
0-8
0.10 MAX
0.80
0.20
1.00
20.00 0.2
Figure 14-1. 64-QFP-1420F Package Dimensions
S3C72N2/C72N4/P72N4
S3P72N4 OTP
15-1
15
S3P72N4 OTP
OVERVIEW
The S3P72N4 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the
S3C72N2/C72N4 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed
by a serial data format.
The S3P72N4 is fully compatible with the S3C72N2/C72N4, both in function and in pin configuration. Because of
its simple programming requirements, the S3P72N4 is ideal for use as an evaluation chip for the S3C72N4.
S3P72N4 OTP
S3C72N2/C72N4/P72N4
15-2
COM0
COM1
COM2
COM3
BIAS
VLC0
SDAT/VLC1
SCLK/VLC2
V
DD
/V
DD
V
SS
/V
SS
Xout
Xin
V
PP
/TEST
XTin
XTout
RESET
/
RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
S3P72N4
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
64
63
62
61
60
59
58
57
56
55
54
53
52
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
20
21
22
23
24
25
26
27
28
29
30
31
32
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24/P8.0
SEG25/P8.1
SEG26/P8.2
SEG27/P8.3
SEG28/P8.4
SEG29/P8.5
SEG30/P8.6
SEG31/P8.7
Figure 15-1. S3P72N4 Pin Assignments (64-QFP)
S3C72N2/C72N4/P72N4
S3P72N4 OTP
15-3
Table 15-1. Pin Descriptions Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
V
LC1
SDAT
7
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
V
LC2
SCLK
8
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
13
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET
RESET
16
I
Chip initialization
V
DD
/ V
SS
V
DD
/ V
SS
9/10
I
Logic power supply pin. V
DD
should be tied to
+5 V during programming.
Table 15-2. Comparison of S3P72N4 and S3C72N2/C72N4 Features
Characteristic
S3P72N4
S3C72N2/C72N4
Program Memory
4-Kbyte EPROM
2-K / 4-Kbyte mask ROM
Operating Voltage (V
DD
)
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
2.0 V to 5.5 V at 4.19 MHz
1.8 V to 5.5 V at 3 MHz
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5 V
Pin Configuration
64 QFP
64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp (TEST) pin of the S3P72N4, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 15-3. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
MEM
Address
(A15-A0)
R/
W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means low level; "1" means high level.
S3P72N4 OTP
S3C72N2/C72N4/P72N4
15-4
Table 15-4. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input high
voltage
V
IH1
All input pins except those
specified below for V
IH2
, V
IH3
0.7 V
DD
V
DD
V
V
IH2
Ports 1, 6, and
RESET
0.8 V
DD
V
DD
V
IH3
X
IN
, X
OUT
, and XT
IN
V
DD
0.1
V
DD
Input low
V
IL1
Ports 2 and 3
0.3 V
DD
V
voltage
V
IL2
Ports 1, 6 and
RESET
0.2 V
DD
V
IL3
X
IN
, X
OUT,
and XT
IN
0.1
Output high
voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
Ports 2, 3, 6 and BIAS
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 100 A Port 8 only
V
DD
2.0
Output low
voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA, Ports 2, 3, 6
0.4
2
V
V
OL2
V
DD
= 4.5 V to 5.5 V
I
OL
= 100 A; Port 8 only
1
Input high
leakage
current
I
LIH1
V
IN
= V
DD
All input pins except those
specified below for I
LIH2
3
A
I
LIH2
V
IN
= V
DD
X
IN
, X
OUT
and XT
IN
20
Input low
leakage
current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
,
and XT
IN
3
A
I
LIL2
V
IN
= 0 V
X
IN
, X
OUT
, and XT
IN
20
Output high
leakage
current
I
LOH1
V
OUT
= V
DD
All output pins
3
A
Output low
leakage
current
I
LOL
V
OUT
= 0 V
All output pins
3
S3C72N2/C72N4/P72N4
S3P72N4 OTP
15-5
Table 15-4. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Pull-up
resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Ports 1, 2, 3, 6
25
50
100
K
V
DD
= 3 V
50
100
200
R
L2
V
IN
= 0 V; V
DD
= 5 V
RESET
100
250
400
V
DD
= 3 V
200
500
800
LCD voltage
dividing
resistor
R
LCD
T
A =
25
C
120
170
220
COM output
R
COM
V
DD
= 5 V
3
6
impedance
V
DD
= 3 V
5
15
SEG output
R
SEG
V
DD
= 5 V
3
6
impedance
V
DD
= 3 V
5
15
COM output
voltage
deviation
V
DC
V
DD
= 5 V (V
LC0
-COMi)
Io =
15uA (i= 0-3)
45
90
mV
SEG output
voltage
deviation
V
DS
V
DD
= 5 V (V
LC0
-SEGi)
Io =
15uA (i= 0-31)
45
90
mV
VLC0 Output
voltage
V
LC0
T
A =
25
C
0.6V
DD
0.2
0.6VDD
0.6V
DD
+ 0.2
V
VLC1 Output
voltage
V
LC1
T
A =
25
C
0.4V
DD
0.2
0.4VDD
0.4V
DD
+ 0.2
VLC2 Output
voltage
V
LC2
T
A =
25
C
0.2V
DD
0.2
0.2VDD
0.2V
DD
+ 0.2
S3P72N4 OTP
S3C72N2/C72N4/P72N4
15-6
Table 15-4. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
(1)
I
DD1
(2)
Main operating:
V
DD
= 5 V
10%
CPU = fx/4
SCMOD = 0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
3.5
2.5
8
5.5
mA
V
DD
= 3 V
10%
6.0 MHz
4.19 MHz
1.6
1.2
4
3
I
DD2
(2)
Main idle mode;
V
DD
= 5 V
10%
CPU = fx/4
SCMOD =0000B
Crystal oscillator
C1 = C2 = 22 pF
6.0 MHz
4.19 MHz
1
0.9
2.5
2
V
DD
= 3 V
10%
6.0 MHz
4.19 MHz
0.5
0.4
1.0
0.8
I
DD3
Sub operating:
V
DD
= 3 V
10%
CPU = fxt/4,
SCMOD = 1001B
32 kHz crystal oscillator
15
30
A
I
DD4
Sub idle mode:
V
DD
= 3 V
10%
CPU = fxt/4, SCMOD = 1001B
32 kHz crystal oscillator
6
15
I
DD5
Stop mode:
VDD = 5V
10%
CPU=fxt/4, SCMOD = 1101B
I
DD6
(3)
Stop mode:
V
DD
= 5 V
10%
CPU = fx/4, SCMOD = 0100B
0.5
3
NOTES:
1.
D.C. electrical values for supply current (I
DD1
to I
DD6
) do not include current drawn through internal pull-up resistors
and through LCD voltage dividing resistors.
2.
Data includes the power consumption for sub-system clock oscillation.
3.
When the system clock mode register, SCMOD, is set to 0100B, the sub-system clock oscillation stops. The main-
system clock oscillation stops by the STOP instruction.
S3C72N2/C72N4/P72N4
S3P72N4 OTP
15-7
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
1
SUPPLY VOLTAGE (V)
250 kHz
500 kHz
15.6 kHz
CPU CLOCK
750 kHz
1.0475 MHz
1.5 MHz
2
3
4
5
6
7
Main OSC. Freq.
3 MHz
4.19 MHz
6 MHz
Figure 15-2. Standard Operating Voltage Range
S3P72N4 OTP
S3C72N2/C72N4/P72N4
15-8
(mA)
35.00
3.500/div
.0000
2.000
V
O
L (V)
I
OL
V
DD
= 2.2 V
V
DD
= 3.3 V
V
DD
= 4.5 V
V
DD
= 5.5 V
.0000
.2000/div
Figure 15-3. Port 2 I
OL
vs V
OL
Curve
PDF 
ZIP