S3C8075/P8075
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
-- Efficient register-oriented architecture
-- Selectable CPU clock sources
-- Idle and Stop power-down mode release by interrupt
-- Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.
S3C8075/P8075 MICROCONTROLLERS
S3C8075/P8075 single-chip 8-bit microcontrollers are based on the powerful SAM87 CPU architecture. The
internal register file is logically expanded to increase the on-chip register space. The S3C8075 has 16-Kbyte
mask-programmable ROM. The S3P8075 has 16-Kbyte one-time-programmable EPROM.
Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core:
-- Seven programmable I/O ports (total 56 pins)
-- One 8-bit basic timer for oscillation stabilization and watchdog functions
-- One synchronous operating mode and three full-duplex asynchronous UART modes
-- Two 8-bit timers with interval timer and PWM modes
-- Two 16-bit general-purpose timer/counters
OTP
The S3C8075 microcontroller is also available in OTP (One Time Programmable) version, S3P8075. S3P8075
microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM. The
S3P8075 is comparable to S3C8075, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C8075/P8075
1-2
FEATURES
CPU
SAM87 CPU core
Memory
272-byte general purpose register area
16-Kbyte internal program memory
ROM-less operating mode
External Interface
64-Kbyte external data memory area
64-Kbyte external program memory area (ROM-
less mode)
Instruction Set
78instructions
IDLE and STOP instructions for power-down
mode
Instruction Execution Time
500 ns at 12 MHz f
CPU
(Min.)
Interrupts
17 interrupt sources
17 interrupt vectors
Eight interrupt levels
Fast interrupt processing
General I/O
Four nibble-programmable ports
One bit-programmable port
Two bit-programmable ports for external
interrupts
Timers
Two 8-bit timers with interval timer and PWM
modes
Timer/Counters
Two 16-bit general-purpose timer/counters
Basic Timer
One 8-bit basic timer (BT) for oscillation
stabilization control and watch dog timer function.
Serial Port
One synchronous operating mode and three full-
duplex asynchronous UART modes
Operating Temperature Range
40
C to + 85
C
Operating Voltage Range
2.7 V to 5.5 V
Package Types
64-pin SDIP, 64-pin QFP
S3C8075/P8075
PRODUCT OVERVIEW
1-3
Table 1-1. Comparison Table
Feature
S3C80B5
S3C8075
Core
SAM8
SAM87
ROM
16 K bytes
Same
RAM
272 bytes
Same
I/O
54
56 (add two pins)
Port 6
Open drain (9 V drive)
Normal C-MOS output
I/O option
None
Same
Timer
8-bit back-up timer
None
Timer A, B
-- 8-bit
-- Interval/PWM mode
-- Timer A match interrupt
Same
(some differ in interval mode,
see manual)
Timer C, D
-- Gate function
-- Timer/counter
Same
Watchdog timer
None
Watchdog timer (with BT)
SIO
UART
-- 8-bit/9-bit UART
-- SIO
Same
Interrupt
External
12
-- P2.4P2.7, P4.0P4.7
Same
Internal
6
-- Timer A, C, D, SI, SO, Back-up
Internal
5
-- Timer A, C, D, SI, SO
Power down
Stop/idle
Same
Oscillator
Crystal, ceramic
Same
CPU clock divider
1/2
1/1, 1/2, 1/8, 1/16
Execution time (Min.)
0.6
s at 20 MHz (f
CPU
= 10 MHz)
0.5
s at 12 MHz (f
CPU
= 12 MHz)
Operating frequency
Max. 20 MHz (f
CPU
= 10 MHz)
Max. 12 MHz (at 4.5 V)
(2)
Max. 4 MHz (at 2.7 V)
Operating voltage
4.55.5 V
2.75.5 V at 4 MHz
4.55.5 V at 12 MHz
OTP/MTP
MTP
OTP
Pin assignment
Different
Package
64SDIP/64QFP
Same
Start address
0020h
0100h
P5CON, P6CON
BANK0
BANK1
Interrupt pending bit clear
Write "1"
Write "0"
NOTES:
1.
The S3C8075 can replace the S3C80B5. Their functions are mostly the same, but there are some differences.
Table 1-1 shows the comparison of S3C8075 and S3C80B5.
2.
Operating frequency is maximum CPU clock; the maximum oscillation frequency is 22.1184 MHz.
PRODUCT OVERVIEW
S3C8075/P8075
1-4
BLOCK DIAGRAM
TCCK
TDCK
TA
TB
PORT I/O and
INTERRUPT CONTROL
16-KB ROM
272-BYTE
REGISTER FILE
PORT 2
P2.0P2.3,
P2.4/INT0P2.7/INT3
P3.0P3.7
RESET
EA
P5.0P5.3
P5.4P5.7
P6.0P6.7
PORT 0
P0.0P0.7
(A8A15)
PORT 1
P1.0P1.7
(AD0AD7)
SAM87 BUS
P4.0/INT4 (TCG)
P4.1/INT5 (TDG)
P4.2/INT6
P4.7/INT11
TIMERS
C and D
PORT 3
PORT 4
PORT 5
PORT 6
X
IN
X
OUT
BASIC
TIMER
MAIN
OSC
TIMERS
A and B
SERIAL
PORT
SAM87 CPU
RxD
TxD
Figure 1-1. S3C8075 Block Diagram
S3C8075/P8075
PRODUCT OVERVIEW
1-5
S3C8075
64-SDIP
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V
DD2
V
SS2
P2.0/
AS
P2.1/
DS
P2.2/R/
W
P2.3/
DM
P2.4/INT0/
WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG
V
DD1
V
SS1
X
OUT
X
IN
EA
P5.6
P5.7
RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
P3.4/TA
P3.3
P3.2
P3.1/TDCK
P3.0/TCCK
P6.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Figure 1-2. S3C8075 Pin Assignments (64-SDIP)
PRODUCT OVERVIEW
S3C8075/P8075
1-6
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
52
53
54
55
56
57
58
59
60
61
62
63
64
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P3.0/TCCK
P3.1/TDCK
P3.2
P3.3
P3.4/TA
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V
DD2
V
SS2
P2.0/
AS
P2.1/
DS
P2.2/R/
W
P2.3/
DM
P2.4/INT0/
WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
P1.4/AD4
P1.3/AD3
P1.2/AD2
P1.1/AD1
P1.0/AD0
P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG
V
DD1
V
SS1
X
OUT
X
IN
EA
P5.6
P5.7
RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
S3C8075
64-QFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 1-3. S3C8075 Pin Assignments (64-QFP)
S3C8075/P8075
PRODUCT OVERVIEW
1-7
Table 1-2. S3C8075 Pin Descriptions (64-SDIP)
Pin
Name
Pin
Type
Pin
Description
Circuit
Number
SDIP Pin
Number
Share
Pins
P0.0P0.7
I/O
I/O port with nibble-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups; also
configurable as external interface address
lines A8-A15.
E
17, 64
A8A15
P1.0P1.7
I/O
Same general characteristics as port 0; also
configurable as external interface
address/data lines AD0AD7.
E
5663
AD0AD7
P2.0P2.3
P2.4P2.7
I/O
I/O port with bit-programmable pins; Input
or push-pull output. Lower nibble pins 03
are configurable for external interface
signals; upper nibble pins 47 are bit-
programmable for external interrupts INT0
INT3. P2.4 can also be used for external
WAIT
input.
D-1 (lower
nibble);
D-1 (upper
nibble; with
noise filter)
4047
AS, DS,
DM,
R/
W
INT0INT3,
WAIT
P3.0P3.7
I/O
I/O port with bit-programmable pins; Input
or push-pull output. Alternate functions
include software-selectable UART transmit
and receive on pins 3.7 and 3.6, timer B
and timer A outputs at pins 3.5 and 3.4, and
timer D and C clock inputs at pins 3.1 and
3.0.
D-1
24 31
TCCK,
TDCK, TA,
TB, TxD,
RxD
P4.0P4.7
I/O
I/O port with bit-programmable pins; Input
or push-pull output; software-assignable
pull-ups. Alternate functions include
external interrupt inputs INT4-INT11 (with
interrupt enable and pending control) and
timer C and D gate input at P4.0 and P4.1.
D
(with noise
filter)
815
INT4
INT11,
TCG, TDG
P5.0P5.7
I/O
I/O port with nibble-programmable pins;
Input or push-pull, open-drain output;
software-assignable pull-ups.
E
21, 22,
5055
P6.0P6.7
O
Output port with nibble-programmable pins;
push-pull, open-drain output; software-
assignable pull-ups.
E-8
3239
RxD
I/O
Bi-directional serial data input pin
24
P3.7
TxD
I/O
Serial data output pin
25
P3.6
TA, TB
I/O
Timer A and B output pins
4
27, 26
P3.4, P3.5
TCCK, TDCK
I/O
Timer C and D external clock input pins
D-1
30, 31
P3.0, P3.1
INT0INT3
I/O
External interrupts. I/O pin 2.4 (share pin
with INT0) is also configurable as a
WAIT
signal input pin for the external interface.
D-1
(with noise
filter)
4043
P2.4P2.7
PRODUCT OVERVIEW
S3C8075/P8075
1-8
Table 1-2. S3C8075 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin
Description
Circuit
Number
SDIP Pin
Number
Share
Pins
INT4INT11
I/O
Bit-programmable external interrupt input
pins with interrupt pending and enable
/disable control
D
(with noise
filter)
815
P4.0P4.7
X
IN
, X
OUT
System clock input and output pins
18, 19
RESET
I
System reset pin
(internal pull-up: 280 K
)
B
23
EA
I
External access (EA) pin with three modes:
0 V: Normal operation (internal ROM)
5 V: ROM-less operation (external interface)
20
V
DD2
, V
SS2
Power input pins for port output (external)
49, 48
V
DD1
, V
SS1
Power input pins for CPU (internal)
16, 17
S3C8075/P8075
PRODUCT OVERVIEW
1-9
PIN CIRCUIT
Data
In/Out
Pull-Up
Enable
In
Open-Drain
Output Disable
V
DD
V
DD
Pull-Up Resistor
(Typical Value: 47 )
K
Figure 1-4. Pin Circuit Type E (Ports 0, 1, 5)
Data
In/Out
Pull-Up
Enable
V
DD
V
SS
V
DD
Pull-Up Resistor
(Typical Value: 47 )
K
Open-Drain
Figure 1-5. Pin Circuit Type E-8 (Ports 6)
PRODUCT OVERVIEW
S3C8075/P8075
1-10
Data
In/Out
In
Output Disable
V
DD
V
SS
Port 2 (Low Byte) Data
External Interface
Select
(
AS, DS,
W, DM
)
R/
M
U
X
Figure 1-6. Pin Circuit Type D-1 (P2.0P2.3)
In/Out
Output Disable
V
DD
V
SS
External Interrupt
Port 2 (High Byte) Data
Normal Input or
WAIT
Input
Noise Filter
Figure 1-7. Pin Circuit Type D-1 (P2.4P2.7)
S3C8075/P8075
PRODUCT OVERVIEW
1-11
Data
In/Out
In
Output Disable
V
DD
V
SS
Port 3 Data
Control Output
Select
M
U
X
Figure 1-8. Pin Circuit Type D-1 (Port 3)
In/Out
Output Disable
V
DD
V
SS
External
Interrpt Input
Data
Input
Pull-Up Enable
V
DD
Noise Filter
Pull-Up Resistor
(Typical Value: 47 )
K
Figure 1-9. Pin Circuit Type D (Port 4)
PRODUCT OVERVIEW
S3C8075/P8075
1-12
RESET
V
DD
Pull-up Resistor
(Typical 210 K
)
Figure 1-10. Pin Circuit Type B (
RESET
RESET
)
S3C8075/P8075
ELECTRICAL DATA
14-1
14
ELECTRICAL DATA
OVERVIEW
In this section, S3C8075 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Oscillation characteristics
-- Oscillation stabilization time
ELECTRICAL DATA
S3C8075/P8075
14-2
Table 14-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
0.3 to + 6.5
V
Input voltage
V
I
All ports (in input mode)
0.3 to V
DD
+ 0.3
Output voltage
V
O
All ports (in output mode)
0.3 to V
DD
+ 0.3
V
Output current high
I
OH
One I/O pin active
10
mA
All I/O pins active
60
Output current low
I
OL
One I/O pin active
+ 30
mA
Total pin current for ports 04
+ 100
Total pin current for ports 5 and 6
+ 100
Operating
temperature
T
A
40 to + 85
C
Storage temperature
T
STG
65 to + 150
C
S3C8075/P8075
ELECTRICAL DATA
14-3
Table 14-2. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input high
voltage
V
IH1
All input pins except V
IH2
0.8 V
DD
V
DD
V
V
IH2
X
IN
V
DD
0.5
Input low voltage
V
IL1
All input pins except V
IL2
0.2 V
DD
V
V
IL2
X
IN
0.4
Output high
voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 4 mA
Port 5, 6
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
All output pins except
port 5, 6
Output low voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA
Ports 5 and 6
1.0
V
V
OL2
I
OL
= 2 mA
Ports 04
0.4
Input high leakage
current
I
LIH1
V
IN
= V
DD
All input pins except X
IN
, X
OUT
3
A
I
LIH2
V
IN
= V
DD
,
X
IN
, X
OUT
20
Input low leakage
current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
3
A
I
LIL2
V
IN
= 0 V, X
IN
, X
OUT
20
Output high
leakage current
I
LOH
V
OUT
= V
DD
All output pins
5
A
Output low leakage
current
I
LOL
V
OUT
= 0 V
5
A
Pull-up resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Ports 0, 1, 4, 5 and 6
30
47
70
K
R
L2
V
IN
= 0 V; V
DD
= 5 V
RESET
only
110
210
310
ELECTRICAL DATA
S3C8075/P8075
14-4
Table 14-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply current
(1)
I
DD1
(2)
V
DD
= 5 V
10 %
12-MHz oscillation
12
25
mA
4-MHz oscillation
4.5
10
V
DD
= 3 V
10 %
12-MHz oscillation
6
15
4-MHz oscillation
2.5
7
I
DD2
(2)
Idle mode; V
DD
= 5 V
10 %
12-MHz oscillation
3
10
4-MHz oscillation
1.5
4
Idle mode; V
DD
= 3 V
10 %
12-MHz oscillation
1.2
3
4-MHz oscillation
0.6
1.5
I
DD3
Stop mode:
V
DD
= 5 V
10 %
0.1
3
A
NOTES:
1.
Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2.
At supply current, the CPU clock frequency is same with oscillation frequency (CPU use non divided clock).
Table 14-3. Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply
voltage
V
DDDR
Stop mode
2
6
V
Data retention supply
current
I
DDDR
Stop mode, V
DDDR
= 2.0 V
3
A
NOTES:
1.
During the oscillator stabilization wait time (t
WAIT
), all CPU operations must be stopped.
2.
Supply current does not include drawn through internal pullup resistors and external output current loads.
S3C8075/P8075
ELECTRICAL DATA
14-5
t
WAIT
V
DD
EXT INT
Execution of
Stop Instruction
V
DDDR
Data Retention Mode
Stop Mode
Idle Mode
(Oscillation
Stabilzation Time)
0.8 V
DD
0.2 V
DD
Normal
Operating
Mode
NOTE: t
WAIT
is the same as 16 x BT clock.
Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt
t
WAIT
V
DD
RESET
Execution of
Stop Instruction
V
DDDR
Data Retention Mode
Stop Mode
Oscillation
Stabilzation
Time
Normal
Operating
Mode
NOTE: t
WAIT
is the same as 4096 x 16 x 1/f
Reset Occurs
OSC
.
Figure 14-2. Stop Mode Release Timing When Initiated by a Reset
ELECTRICAL DATA
S3C8075/P8075
14-6
Table 14-4. Input/output Capacitance
(T
A
= 40
C to + 85
C, V
DD
=
0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
capacitance
C
IN
f = 1 MHz; unmeasured
pins are connected to V
SS
10
pF
Output
capacitance
C
OUT
I/O capacitance
C
IO
Table 14-5. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input high,
low width
t
INTH
,
t
I
NTL
P2.4P2.7
100
ns
P4.0P4.7
100
RESET
input low width
t
RSL
Input
10
s
NOTE: User must keep the larger value with the min value.
t
INTL
t
INTH
0.8 V
DD
0.2 V
DD
Figure 14-3. Input Timing for External Interrupts (Port 2 and 4)
S3C8075/P8075
ELECTRICAL DATA
14-7
RESET
t
RSL
0.2 V
DD
Figure 14-4. Input Timing for
RESET
RESET
Table 14-6. Oscillation Characteristics
(T
A
= 20
C + 85
C, V
DD
= 4.5 V to 5.5 V)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Crystal
C2
X
IN
X
OUT
C1
Oscillation frequency
1
22.1184
MHz
Ceramic
C2
X
IN
X
OUT
C1
Oscillation frequency
1
22.1184
MHz
External clock
X
IN
X
OUT
X
IN
input frequency
1
22.1184
MHz
ELECTRICAL DATA
S3C8075/P8075
14-8
Table 14-7. Main Oscillator Clock Stabilization Time (t
ST1
)
(T
A
= 20
C + 85
C, V
DD
= 4.5 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Crystal
V
DD
= 4.5 V to 5.5 V
20
ms
Ceramic
Stabilization occurs when V
DD
is equal to the minimum
oscillator voltage range.
10
ms
NOTE: Oscillation stabilization time (tST1) is the time required for the CPU clock to return to its normal oscillation
frequency after a power-on occurs, or when Stop mode is released by a RESET signal.
1 MHz
4 MHz
12 MHz
2
3
4
5
6
7
1
2.7
4.5
CPU clock
V
DD
5.5
Figure 14-5. Frequency VS. Voltage
S3C8075/P8075
MECHANICAL DATA
15-1
15
MECHANICAL DATA
OVERVIEW
The S3C8075 microcontroller is available in a 64-pin SDIP package (64-SDIP-750) and a 64-pin QFP package
(64-QFP-1420F).
NOTE:
Dimensions are in millimeters
.
64-SDIP-75 0
17.00
0.2
#1
#32
#64
#33
19.05
0
-
15
0.25
+0.1 0.05
1.00
0.1
0.45
0.1
57.80
0.2
58.20 MAX
0.51MIN
4.10
0.2
3.30
0.3
5.08MAX
(1.34)
1.778
Figure 15-1. 64-SDIP-750 Package Dimensions
MECHANICAL DATA
S3C8075/P8075
15-2
NOTE: Dimensions are in millimeters.
44-QFP-1010B
13.20
0.3
#44
(1.00)
#1
13.20
0.3
10.00
0.2
0.35
+0.10
- 0.05
0.10 MAX
0.15
+0.10
- 0.05
0-8
0.05 MIN
2.05
0.10
2.30 MAX
0.80
0.20
0.80
10.00
0.2
Figure 15-2. 64-QFP-1420F Package Dimensions
S3C8075/P8075
S3P8075 OTP
16-1
16
S3P8075 OTP
OVERVIEW
The S3C8075 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the S3C8075
microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data
format.
S3P8075 is fully compatible with S3C8075, both in function and in pin configuration. As it has simple
programming requirements, S3P8075 is ideal for use as an evaluation chip for the S3C8075.
S3P8075 OTP
S3C8075/P8075
16-2
S3P8075
64-SDIP
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V
DD2
V
SS2
P2.0/
AS
P2.1/
DS
P2.2/R/
W
P2.3/
DM
P2.4/INT0/
WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
SDATA/P4.1/INT5/TDG
SCLK /P4.0/INT4/TCG
V
DD
/V
DD1
V
SS
/V
SS1
X
OUT
X
IN
V
PP
/EA
P5.6
P5.7
RESET
RESET /RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
P3.4/TA
P3.3
P3.2
P3.1/TDCK
P3.0/TCCK
P6.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Figure 16-1. S3P8075 Pin Assignments (64-SDIP Package)
S3C8075/P8075
S3P8075 OTP
16-3
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P3.0/TCCK
P3.1/TDCK
P3.2
P3.3
P3.4/TA
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
52
53
54
55
56
57
58
59
60
61
62
63
64
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
V
DD2
V
SS2
P2.0/
AS
P2.1/
DS
P2.2/R/
W
P2.3/
DM
P2.4/INT0/
WAIT
P2.5/INT1
P2.6/INT2
P2.7/INT3
P1.4/AD4
P1.3/AD3
P1.2/AD2
P1.1/AD1
P1.0/AD0
P0.7/A15
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
SDAT /P4.1/INT5/TDG
SCLK /P4.0/INT4/TCG
V
DD
/V
DD1
V
SS
/V
SS1
X
OUT
X
IN
V
PP
/EA
P5.6
P5.7
RESET
RESET /RESET
P3.7/RxD
P3.6/TxD
P3.5/TB
S3P8075
64-QFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Figure 16-2. S3P8075 Pin Assignments (64-QFP Package)
S3P8075 OTP
S3C8075/P8075
16-4
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P4.1
SDAT
14 (7)
I/O
Serial Data Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned.
P4.0
SCLK
15 (8)
I
Serial Clock Pin (Input Only Pin)
EA
V
PP
20 (13)
I
EPROM Cell Writing Power Supply Pin
(Indicates OTP Mode Entering) When writing
12.5V is applied and when reading 5 V is applied
(Option).
RESET
RESET
23 (9)
I
Chip Initialization
V
DD1
/V
SS1
V
DD
/V
SS
16/17
(9/10)
I
Logic Power Supply Pin. VDD should be tied to
5V during programming.
NOTE: Parentheses indicate 64-QFP pin number.
Table 16-2. Comparison of S3P8075 and S3C8075 Features
Characteristic
S3P8075
S3C8075
Program Memory
16 Kbyte EPROM
16 Kbytes mask ROM
Operating Voltage (V
DD
)
2.7 V to 5.5 V
2.7 V to 5.5V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5V
Pin Configuration
64 SDIP, 64 QFP
64 SDIP, 64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of S3P8075, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
MEM
ADDRESS
(A15A0)
R/
W
W
MODE
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3C8075/P8075
S3P8075 OTP
16-5
D.C. ELECTRICAL CHARACTERISTICS
Table 16-4. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input High
Voltage
V
IH1
All input pins except V
IH2
0.8 V
DD
V
DD
V
V
IH2
X
IN
V
DD
0.5
Input Low Voltage
V
IL1
All input pins except V
IL2
0.2 V
DD
V
V
IL2
X
IN
0.4
Output High
Voltage
V
OH1
V
DD
= 4.5 V to 5.5 V
I
OH
= 4 mA
Port 5, 6
V
DD
1.0
V
V
OH2
V
DD
= 4.5 V to 5.5 V
I
OH
= 1 mA
All output pins except port 5, 6
V
DD
1.0
Output Low
Voltage
V
OL1
V
DD
= 4.5 V to 5.5 V
I
OL
= 15 mA
Ports 5 and 6
1.0
V
V
OL2
I
OL
= 2 mA
Ports 0 - 4
0.4
S3P8075 OTP
S3C8075/P8075
16-6
Table 16-4. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 2.7 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input High Leakage
Current
I
LIH1
V
IN
= V
DD
All input pins except X
IN
, X
OUT
3
uA
I
LIH2
V
IN
= V
DD
,
X
IN
, X
OUT
20
Input Low Leakage
Current
I
LIL1
V
IN
= 0 V
All input pins except X
IN
, X
OUT
3
uA
I
LIL2
V
IN
= 0 V, X
IN
, X
OUT
20
Output High
Leakage Current
I
LOH
V
OUT
= V
DD
All output pins
5
uA
Output Low
Leakage Current
I
LOL
V
OUT
= 0 V
5
uA
Pull-up Resistor
R
L1
V
IN
= 0 V; V
DD
= 5 V
Ports 0, 1, 4, 5 and 6
30
47
70
K
R
L2
V
IN
= 0 V; V
DD
= 5 V
RESET
only
110
210
310
Supply Current
(1)
I
DD1
(2)
V
DD
= 5 V
10%
12-MHz oscillation
12
25
mA
4-MHz oscillation
4.5
10
V
DD
= 3 V
10%
12-MHz oscillation
6
15
4-MHz oscillation
2.5
7
I
DD2
(2)
Idle mode; V
DD
= 5 V
10 %
12-MHz oscillation
2.5
6
4-MHz oscillation
1.5
4
Idle mode; V
DD
= 3 V
10 %
12-MHz oscillation
1.2
3
4-MHz oscillation
0.6
1.5
I
DD3
Stop mode:
V
DD
= 5 V
10 %
0.1
3
uA
NOTES:
1.
Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2.
At supply current, the CPU clock frequency is the same as oscillation frequency (CPU use non divided clock).
S3C8075/P8075
S3P8075 OTP
16-7
START
Address= First Location
V
DD
=5V, V
PP
=12.5V
x = 0
Program One 1ms Pulse
Increment X
x = 10
Verify 1 Byte
Last Address
V
DD
= V
PP
= 5 V
Compare All Byte
Device Passed
Increment Address
Verify Byte
Device Failed
PASS
FAIL
NO
FAIL
YES
FAIL
NO
Figure 16-3. OTP Programming Algorithm
S3P8075 OTP
S3C8075/P8075
16-8
NOTES
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