Important Notice

The information in this publication has been
carefully checked and is believed to be entirely
accurate at the time of publication. Samsung
assumes no responsibility, however, for possible
errors or omissions, or for any consequences
resulting from the use of the information contained
herein.

Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.

This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of
any product or circuit and specifically disclaims any
and all liability, including without limitation any
consequential or incidental damages.

"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.

Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
Samsung product could create a situation where
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Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
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unauthorized use, even if such claim alleges that
Samsung was negligent regarding the design or
manufacture of said product.

S3P80C5/C80C5/C80C8 8-Bit CMOS Microcontrollers
User's Manual, Revision 1
Publication Number: 21-S3- P80C5/C80C5/C80C8-052002

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are
designed and manufactured in accordance with the highest quality standards and
objectives.

Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 440-900

TEL:

(82)-(31)-209-1934

FAX:

(82)-(31)-209-1899

Home Page: http://www.samsungsemi.com
Printed in the Republic of Korea

S3P80C5/C80C5/C80C8

MICROCONTROLLER

iii

Preface

The S3C80C5/C80C8 Microcontroller User's Manual is designed for application designers and programmers who
are using the S3C80C5/C80C8 microcontroller for application development.
It is organized in two main parts:

Part I Programming Model

Part II Hardware Descriptions

Part I contains software-related information to familiarize you with the microcontroller's architecture,
programming model, instruction set, and interrupt structure. It has six chapters:

Chapter 1

Product Overview

Chapter 2

Address Spaces

Chapter 3

Addressing Modes

Chapter 4

Control Registers

Chapter 5

Interrupt Structure

Chapter 6

Instruction Set

Chapter 1, "Product Overview," is a high-level introduction to S3C80C5/C80C8 with general product descriptions,
as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," describes program and data memory spaces, the internal register file, and register
addressing. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack
operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the
KS88-series CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register
values, as well as detailed one-page descriptions in a standardized format. You can use these easy-to-read,
alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the S3C80C5/C80C8 interrupt structure in detail and further prepares
you for additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "Instruction Set," describes the features and conventions of the instruction set used for all S3C8-series
microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of
each instruction are presented in a standard format. Each instruction description includes one or more practical
examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in
Part II. If you are not yet familiar with the S3C8-series microcontroller family and are reading this manual for the
first time, we recommend that you first read Chapters 13 carefully. Then, briefly look over the detailed
information in Chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the
S3C80C5/C80C8 microcontroller. Also included in Part II are electrical, mechanical, OTP, and development tools
data. It has eight chapters:

Chapter 7

Clock Circuit

Chapter 8

RESET

and Power-Down

Chapter 9

I/O Ports

Chapter 10

Basic Timer and Timer 0

Chapter 11

Timer 1

Chapter 12

Counter A

Chapter 13

Electrical Data

Chapter 14

Mechanical Data

Two order forms are included at the back of this manual to facilitate customer order for S3C80C5/C80C8
microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these
forms, fill them out, and then forward them to your local Samsung Sales Representative.

S3P80C5/C80C5/C80C8

MICROCONTROLLER

Table of Contents

Part I -- Programming Model

Chapter 1

Product Overview

Overview .................................................................................................................................................1-1
S3P80C5/C80C5/C80C8 Microcontroller .................................................................................................1-1
Features ..................................................................................................................................................1-2
CPU ........................................................................................................................................................1-2
Block Diagram .........................................................................................................................................1-3
Pin Assignments......................................................................................................................................1-4
Pin Descriptions.......................................................................................................................................1-5
Pin Circuits ..............................................................................................................................................1-6

Chapter 2

Address Spaces

Register Page Pointer (PP) .............................................................................................................2-5
Register Set 1 .................................................................................................................................2-6
Register Set 2 .................................................................................................................................2-6
Prime Register Space .....................................................................................................................2-7
Working Registers ...........................................................................................................................2-8
Using The Register Pointers ............................................................................................................2-9

Register Addressing.................................................................................................................................2-11

Common Working Register Area (C0HCFH)..................................................................................2-13
4-Bit Working Register Addressing ..................................................................................................2-14
8-Bit Working Register Addressing ..................................................................................................2-16

System and User Stacks..........................................................................................................................2-18

Chapter 3

Addressing Modes

Overview .................................................................................................................................................3-1

Register Addressing Mode (R).........................................................................................................3-2
Indirect Register Addressing Mode (IR) ...........................................................................................3-3
Indexed Addressing Mode (X)..........................................................................................................3-7
Direct Address Mode (DA)...............................................................................................................3-10
Indirect Address Mode (IA) ..............................................................................................................3-12
Relative Address Mode (RA) ...........................................................................................................3-13
Immediate Mode (IM) ......................................................................................................................3-14

S3P80C5/C80C5/C80C8

MICROCONTROLLER

Table of Contents

(Continued

Chapter

Control Registers

................................

.................

Chapter 5

Overview ................................

................................................................

5-1

Interrupt Types

................................................................

5-2

Interrupt Structure

................................................................

5-3

Interrupt Vector Addresses

................................................................

5-5

Enable/Disable Interrupt Instructions (EI, DI)

...................................................

System-Level Interrupt Control Registers ................................

........................5-7

................................................................

..5-8

................................................................

5-9

System Mode Register (SYM)

................................................................

5-10

Interrupt Mask Register (IMR)

................................................................

5-11

Interrupt Priority Register (IPR)

................................................................

5-12

Interrupt Request Register (IRQ)

................................................................

5-14

Interrupt Pending Function Types

................................................................

5-15

Interrupt Source Polling Sequence

................................................................ 5-16

Interrupt Service Routines

................................................................

5-16

Generating Interrupt Vector Addresses

............................................................

Nesting of Vectored Interrupts ................................

.........................................

Instruction Pointer (IP)................................

.....................................................

Fast Interrupt Processing

................................................................

5-17

Chapter

Instruction Set

Overview

................................................................

.................6-1

................................................................

......................................

........................................................

Addressing Modes ................................

...........................................................

Flags Register (FLAGS) ................................

..................................................

Flag Descriptions................................

.............................................................

Instruction Set Notation ................................

...................................................

Condition Codes ................................

..............................................................

Instruction Descriptions ................................

...................................................

S3P80C5/C80C5/C80C8

MICROCONTROLLER

vii

Table of Contents

(Continued)

Part II Hardware Descriptions

Chapter 7

Clock Circuit

Overview .................................................................................................................................................7-1

System Clock Circuit .......................................................................................................................7-1
Clock Status During Power-Down Modes.........................................................................................7-2
System Clock Control Register (CLKCON) ......................................................................................7-3

Chapter 8

RESET

and Power-Down

System Reset ..........................................................................................................................................8-1

LVD Reset.......................................................................................................................................8-1
Interrupt with Reset (INTR)..............................................................................................................8-2
Watch-Dog Timer Reset..................................................................................................................8-2
Power-on Reset (POR)....................................................................................................................8-2
System Reset Operation .................................................................................................................8-3
Hardware Reset Values ...................................................................................................................8-4

Power-Down Modes.................................................................................................................................8-6

Stop mode.......................................................................................................................................8-6
Using POR to Release Stop Mode...................................................................................................8-6
Using an INTR to Release Stop Mode .............................................................................................8-6
Idle Mode ........................................................................................................................................8-9
Summary Table of Stop Mode, and Idle Mode.................................................................................8-10

Chapter 9

I/O Ports

Overview .................................................................................................................................................9-1

Port Data Registers .........................................................................................................................9-2
Pull-Up Resistor Enable Registers...................................................................................................9-2
Port 0 ..............................................................................................................................................9-4
Port 0 Interrupt Enable Register (P0INT) .........................................................................................9-5
Port 0 Interrupt Pending Register (P0PND)......................................................................................9-5
Port 1 ..............................................................................................................................................9-7
Port 2 ..............................................................................................................................................9-9

Chapter 10

Basic Timer and Timer 0

Module Overview.....................................................................................................................................10-1

Basic Timer Control Register (BTCON) ...............................................................................................10-1
Basic Timer Function Description ........................................................................................................10-3
Timer 0 Control Register (T0CON) ......................................................................................................10-3
Timer 0 Function Description...............................................................................................................10-5

viii

S3P80C5/C80C5/C80C8

MICROCONTROLLER

Table of Contents

(Concluded)

Chapter 11

Timer 1

Overview .................................................................................................................................................11-1

Timer 1 Overflow Interrupt...............................................................................................................11-2
Timer 1 Match Interrupt ...................................................................................................................11-2
Timer 1 Control Register (T1CON) ..................................................................................................11-4

Chapter 12

Counter A

Overview .................................................................................................................................................12-1

Counter A Control Register (CACON)..............................................................................................12-3
Counter A Pulse Width Calculations ................................................................................................12-4

Chapter 13

Electrical Data

Overview .................................................................................................................................................13-1

Chapter 14

Mechanical Data

Overview .................................................................................................................................................14-1

S3P80C5/C80C5/C80C8

MICROCONTROLLER

List of Figures

Figure

Title

Page

Number

1-1

Block Diagram........................................................................................................1-3

1-2

Pin Assignment Diagram (24-Pin SOP/SDIP Package) ..........................................1-4

1-3

Pin Circuit Type 1 (Port 0) ......................................................................................1-6

1-4

Pin Circuit Type 2 (Port 1) ......................................................................................1-7

1-5

Pin Circuit Type 3 (P2.0) ........................................................................................1-8

1-6

Pin Circuit Type 4 (P2.1) ........................................................................................1-9

1-7

Pin Circuit Type 5 (P2.2) ........................................................................................1-10

2-1

Program Memory Address Space ...........................................................................2-2

2-2

Internal Register File Organization .........................................................................2-4

2-3

2-4

Set 1, Set 2, and Prime Area Register Map ............................................................2-7

2-5

8-Byte Working Register Areas (Slices)..................................................................2-8

2-6

Contiguous 16-Byte Working Register Block ..........................................................2-9

2-7

Non-Contiguous 16-Byte Working Register Block ...................................................2-10

2-8

16-Bit Register Pair ................................................................................................2-11

2-9

2-10

Common Working Register Area ............................................................................2-13

2-11

4-Bit Working Register Addressing .........................................................................2-15

2-12

4-Bit Working Register Addressing Example ..........................................................2-15

2-13

8-Bit Working Register Addressing .........................................................................2-16

2-14

8-Bit Working Register Addressing Example ..........................................................2-17

2-15

Stack Operations....................................................................................................2-18

3-1

3-2

Working Register Addressing .................................................................................3-2

3-3

Indirect Register Addressing to Register File ..........................................................3-3

3-4

Indirect Register Addressing to Program Memory...................................................3-4

3-5

Indirect Working Register Addressing to Register File ............................................3-5

3-6

Indirect Working Register Addressing to Program or Data Memory ........................3-6

3-7

Indexed Addressing to Register File .......................................................................3-7

3-8

Indexed Addressing to Program or Data Memory with Short Offset ........................3-8

3-9

Indexed Addressing to Program or Data Memory ...................................................3-9

3-10

Direct Addressing for Load Instructions ..................................................................3-10

3-11

Direct Addressing for Call and Jump Instructions....................................................3-11

3-12

Indirect Addressing.................................................................................................3-12

3-13

Relative Addressing ...............................................................................................3-13

3-14

Immediate Addressing............................................................................................3-14

4-1

S3P80C5/C80C5/C80C8

MICROCONTROLLER

List of Figures

(Continued)

Figure

Title

Page

Number

5-1

KS88-Series Interrupt Types...................................................................................5-2

5-3

ROM Vector Address Area .....................................................................................5-5

5-2

Interrupt Structure ..................................................................................................5-4

5-4

Interrupt Function Diagram .....................................................................................5-8

5-5

System Mode Register (SYM) ................................................................................5-10

5-6

Interrupt Mask Register (IMR).................................................................................5-11

5-7

Interrupt Request Priority Groups ...........................................................................5-12

5-8

Interrupt Priority Register (IPR)...............................................................................5-13

5-9

Interrupt Request Register (IRQ) ............................................................................5-14

6-1

System Flags Register (FLAGS).............................................................................6-6

7-1

Main Oscillator Circuit (External Crystal or Ceramic Resonator) .............................7-1

7-2

External Clock Circuit .............................................................................................7-1

7-3

System Clock Circuit Diagram ................................................................................7-2

7-4

System Clock Control Register (CLKCON) .............................................................7-3

8-1

Reset Block Diagram..............................................................................................8-1

8-2

Power-on Reset Circuit...........................................................................................8-2

8-3

Timing Diagram for Power-on Reset Circuit............................................................8-3

9-1

S3P80C5/C80C5/C80C8 I/O Port 0 Data Register Format......................................9-2

9-2

S3P80C5/C80C5/C80C8 I/O Port 1 Data Register Format......................................9-3

9-3

Port 0 High-Byte Control Register (P0CONH) .........................................................9-4

9-4

Port 0 Low-Byte Control Register (P0CONL) ..........................................................9-5

9-5

Port 0 External Interrupt Control Register (P0INT) ..................................................9-6

9-6

Port 0 External Interrupt Pending Register (P0PND)...............................................9-7

9-7

Port 1 High-Byte Control Register (P1CONH) .........................................................9-7

9-8

Port 1 Low-Byte Control Register (P1CONL) ..........................................................9-8

9-9

Port 2 Control Register (P2CON)............................................................................9-9

9-10

Port 2 Data Register (P2) .......................................................................................9-10

S3P80C5/C80C5/C80C8

MICROCONTROLLER

List of Figures

(Concluded)

Figure

Title

Page

Number

10-1

Basic Timer Control Register (BTCON) ..................................................................10-2

10-2

Timer 0 Control Register (T0CON) .........................................................................10-4

10-3

Simplified Timer 0 Function Diagram: Interval Timer Mode ....................................10-5

10-4

Simplified Timer 0 Function Diagram: PWM Mode .................................................10-6

11-1

Simplified Timer 1 Function Diagram: Interval Timer Mode ....................................11-2

11-2

Timer 1 Block Diagram...........................................................................................11-3

11-3

Timer 1 Control Register (T1CON) .........................................................................11-4

11-4

Timer 1 Registers ...................................................................................................11-5

12-1

Counter A Block Diagram .......................................................................................12-2

12-2

Counter A Control Register (CACON).....................................................................12-3

12-3

Counter A Registers ...............................................................................................12-4

12-4

Counter A Output Flip-Flop Waveforms in Repeat Mode........................................12-5

13-1

Input Timing for External Interrupts (Port 0)............................................................13-5

13-2

Operating Voltage Range ......................................................................................13-6

14-1

24-Pin SOP Package Mechanical Data ..................................................................14-1

14-2

24-Pin SDIP Package Mechanical Data..................................................................14-2

S3P80C5/C80C5/C80C8

MICROCONTROLLER

xiii

List of Tables

Table

Title

Page

Number

1-1

Pin Descriptions .....................................................................................................1-5

2-1

4-1

Mapped Registers (Set1)........................................................................................4-2

5-1

Interrupt Vectors.....................................................................................................5-6

5-2

Interrupt Control Register Overview .......................................................................5-7

5-3

Interrupt Source Control and Data Registers...........................................................5-9

6-1

Instruction Group Summary....................................................................................6-2

6-2

Flag Notation Conventions .....................................................................................6-8

6-3

Instruction Set Symbols..........................................................................................6-8

6-4

Instruction Notation Conventions ............................................................................6-9

6-5

Opcode Quick Reference .......................................................................................6-10

6-6

Condition Codes.....................................................................................................6-12

8-1

Set 1 Register Values After Reset ..........................................................................8-4

8-2

Summary of Each Mode.........................................................................................8-10

9-1

S3P80C5/C80C5/C80C8 Port Configuration Overview ...........................................9-1

9-2

Port Data Register Summary..................................................................................9-2

13-1

Absolute Maximum Ratings....................................................................................13-2

13-2

D.C. Electrical Characteristics ................................................................................13-2

13-3

Characteristics of Low Voltage Detect circuit ..........................................................13-4

13-4

Data Retention Supply Voltage in Stop Mode .........................................................13-4

13-5

Input/Output Capacitance .......................................................................................13-4

13-6

A.C. Electrical Characteristics ................................................................................13-4

13-7

Oscillation Characteristics ......................................................................................13-5

13-8

Oscillation Stabilization Time .................................................................................13-6

S3P80C5/C80C5/C80C8

MICROCONTROLLER

List of Programming Tips

Description

Page

Number

Chapter 2:

Address Spaces

Setting the Register Pointers ...............................................................................................................2-9
Using the RPs to Calculate the Sum of a Series of Registers...............................................................2-10
Addressing the Common Working Register Area .................................................................................2-14
Standard Stack Operations Using PUSH and POP ..............................................................................2-19

Chapter 8:

RESET

and Power-Down

To Divide STOP Mode Releasing and POR.........................................................................................8-8

Chapter 10:

Basic Timer and Timer 0

Configuring the Basic Timer ................................................................................................................10-8
Programming Timer 0..........................................................................................................................10-9

Chapter 12:

Counter A

To Generate 38 kHz, 1/3duty Signal Through P2.1 ..............................................................................12-6
To Generate a One Pulse Signal Through P2.1 ...................................................................................12-7

S3P80C5/C80C5/C80C8

MICROCONTROLLER

xvii

List of Register Descriptions

Register

Full Register Name

Page

Identifier

Number

BTCON

Basic Timer Control Register..................................................................................4-5

CACON

Counter A Control Register.....................................................................................4-6

CLKCON

System Clock Control Register ...............................................................................4-7

EMT

External Memory Timing Register ..........................................................................4-8

FLAGS

System Flags Register ...........................................................................................4-9

IMR

Interrupt Mask Register ..........................................................................................4-10

IPH

Instruction Pointer (High Byte) ...............................................................................4-11

IPL

Instruction Pointer (Low Byte) ................................................................................4-11

IPR

Interrupt Priority Register........................................................................................4-12

IRQ

Interrupt Request Register......................................................................................4-13

P0CONH

Port 0 Control Register (High Byte) ........................................................................4-14

P0CONL

Port 0 Control Register (Low Byte) .........................................................................4-15

P0INT

Port 0 Interrupt Control Register .............................................................................4-16

P0PND

Port 0 Interrupt Pending Register ...........................................................................4-17

P0PUR

Port 0 Pull-up Resistor Enable Register..................................................................4-18

P1CONH

Port 1 Control Register (High Byte) ........................................................................4-19

P1CONL

Port 1 Control Register (Low Byte) .........................................................................4-20

P1PUR

Port 1 Pull-up Resistor Enable Register .................................................................4-21

P2CON

Port 2 Control Register ...........................................................................................4-22

RP0

Register Pointer 0...................................................................................................4-24

RP1

Register Pointer 1...................................................................................................4-24

SPL

Stack Pointer (Low Byte) ........................................................................................4-25

STOPCON

Stop Control Register .............................................................................................4-25

SYM

System Mode Register ...........................................................................................4-26

T0CON

Timer 0 Control Register ........................................................................................4-27

T1CON

Timer 1 Control Register ........................................................................................4-28

S3P80C5/C80C5/C80C8

MICROCONTROLLER

xix

List of Instruction Descriptions

Instruction

Full Register Name

Page

Mnemonic

Number

ADC

Add with Carry........................................................................................................6-14

ADD

Add ........................................................................................................................6-15

AND

Logical AND ...........................................................................................................6-16

BAND

Bit AND ..................................................................................................................6-17

BCP

Bit Compare ...........................................................................................................6-18

BITC

Bit Complement .....................................................................................................6-19

BITR

Bit Reset ................................................................................................................6-20

BITS

Bit Set ....................................................................................................................6-21

BOR

Bit OR ....................................................................................................................6-22

BTJRF

Bit Test, Jump Relative on False............................................................................6-23

BTJRT

Bit Test, Jump Relative on True .............................................................................6-24

BXOR

Bit XOR..................................................................................................................6-25

CALL

Call Procedure .......................................................................................................6-26

CCF

Complement Carry Flag .........................................................................................6-27

CLR

Clear ......................................................................................................................6-28

COM

Complement...........................................................................................................6-29

Compare ................................................................................................................6-30

CPIJE

Compare, Increment, and Jump on Equal ..............................................................6-31

CPIJNE

Compare, Increment, and Jump on Non-Equal .......................................................6-32

Decimal Adjust .......................................................................................................6-33

DEC

Decrement .............................................................................................................6-35

DECW

Decrement Word ....................................................................................................6-36

Disable Interrupts ...................................................................................................6-37

DIV

Divide (Unsigned)...................................................................................................6-38

DJNZ

Decrement and Jump if Non-Zero ..........................................................................6-39

Enable Interrupts ....................................................................................................6-40

ENTER

Enter ......................................................................................................................6-41

EXIT

Exit ........................................................................................................................6-42

IDLE

Idle Operation ........................................................................................................6-43

INC

Increment ...............................................................................................................6-44

INCW

Increment Word .....................................................................................................6-45

IRET

Interrupt Return ......................................................................................................6-46

Jump ......................................................................................................................6-47

Jump Relative ........................................................................................................6-48

Load.......................................................................................................................6-49

LDB

Load Bit..................................................................................................................6-51

S3P80C5/C80C5/C80C8

MICROCONTROLLER

List of Instruction Descriptions

(Continued)

Instruction

Full Register Name

Page

Mnemonic

Number

LDC/LDE

Load Memory .........................................................................................................6-52

LDCD/LDED

Load Memory and Decrement ................................................................................6-54

LDCI/LDEI

Load Memory and Increment ..................................................................................6-55

LDCPD/LDEPD

Load Memory with Pre-Decrement .........................................................................6-56

LDCPI/LDEPI

Load Memory with Pre-Increment ...........................................................................6-57

LDW

Load Word .............................................................................................................6-58

MULT

Multiply (Unsigned).................................................................................................6-59

Next .......................................................................................................................6-60

NOP

No Operation ..........................................................................................................6-61

Logical OR .............................................................................................................6-62

POP

Pop from Stack.......................................................................................................6-63

POPUD

Pop User Stack (Decrementing) .............................................................................6-64

POPUI

Pop User Stack (Incrementing) ...............................................................................6-65

PUSH

Push to Stack .........................................................................................................6-66

PUSHUD

Push User Stack (Decrementing)............................................................................6-67

PUSHUI

Push User Stack (Incrementing) .............................................................................6-68

RCF

Reset Carry Flag ....................................................................................................6-69

RET

Return ....................................................................................................................6-70

Rotate Left .............................................................................................................6-71

RLC

Rotate Left through Carry .......................................................................................6-72

Rotate Right ...........................................................................................................6-73

RRC

Rotate Right through Carry .....................................................................................6-74

SB0

Select Bank 0 .........................................................................................................6-75

SB1

Select Bank 1 .........................................................................................................6-76

SBC

Subtract with Carry .................................................................................................6-77

SCF

Set Carry Flag ........................................................................................................6-78

SRA

Shift Right Arithmetic..............................................................................................6-79

SRP/SRP0/SRP1

Set Register Pointer ...............................................................................................6-80

STOP

Stop Operation .......................................................................................................6-81

SUB

Subtract..................................................................................................................6-82

SWAP

Swap Nibbles .........................................................................................................6-83

TCM

Test Complement under Mask ................................................................................6-84

Test under Mask.....................................................................................................6-85

WFI

Wait for Interrupt ....................................................................................................6-86

XOR

Logical Exclusive OR .............................................................................................6-87

S3P80C5/C80C5/C80C8

PRODUCT OVERVIEW

1-1

PRODUCT OVERVIEW

OVERVIEW

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:

-- Efficient register-oriented architecture

-- Selectable CPU clock sources

-- Idle and Stop power-down mode release by interrupt

-- Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.

S3P80C5/C80C5/C80C8 MICROCONTROLLER

The S3P80C5/C80C5/C80C8 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS
process and is based on Samsung's newest CPU architecture.

The S3C80C5/C80C8 is the microcontroller which has mask-programmable ROM.

The S3P80C5 is the microcontroller which has one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers developed the S3P80C5/C80C5/C80C8 by
integrating the following peripheral modules with the powerful SAM87 RC core:

-- Three programmable I/O ports, including two 8-bit ports and one 3-bit port, for a total of 19 pins.

-- Internal LVD circuit and eight bit-programmable pins for external interrupts.

-- One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).

-- One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

-- One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3P80C5/C80C5/C80C8 is a versatile general-purpose microcontroller which is especially suitable for use
as remote transmitter controller. It is currently available in a 24-pin SOP and SDIP package.

PRODUCT OVERVIEW

S3P80C5/C80C5/C80C8

1-2

FEATURES

CPU

SAM87RC CPU core

Memory

Program memory (ROM)

S3C80C8: 8-Kbyte
(0000H1FFFH)

S3C80C5: 15,872 byte
(0000H3E00H)

Data memory: 256-byte RAM

Instruction Set

78 instructions

IDLE and STOP instructions added for power-
down modes

Instruction Execution Time

1000 ns at 4-MHz f

OSC

(minimum)

Interrupts

13 interrupt sources with 10 vector.

5 level, 10 vector interrupt structure

I/O Ports

Two 8-bit I/O ports (P0-P1) and one 3-bit port
(P2) for a total of 19 bit-programmable pins

Eight input pins for external interrupts

Carrier Frequency Generator

One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)

Back-up mode

When V

is lower than V

LVD

, the chip enters

Back-up mode to block oscillation and reduce the
current consumption.

Timers and Timer/Counters

One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
function

One 8-bit timer/counter (Timer 0) with two
operating modes; Interval mode and PWM mode.

One 16-bit timer/counter with one operating
modes; Interval mode

Low Voltage Detect Circuit

Low voltage detect for reset or Back-up mode.

Low level detect voltage
S3C80C5/C80C8:
1.90 V (Typ)

200 mV

Auto Reset Function

Reset occurs when stop mode is released by P0.

When a falling edge is detected at Port 0 during
Stop mode, system reset occurs.

Operating Temperature Range

· 40

C to + 85

Operating Voltage Range

1.7 V to 3.6 V at 4 MHz f

OSC

Package Type

24-pin SOP/SDIP

S3P80C5/C80C5/C80C8

PRODUCT OVERVIEW

1-5

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

Pin

Names

Pin

Type

Pin

Description

Circuit

Type

24-Pin

Number

Shared

Functions

P0.0P0.7

I/O

I/O port with bit-programmable pins.
Configurable to input or push-pull output
mode. Pull-up resistors are assignable by
software. Pins can be assigned individually
as external interrupt inputs with noise filters,
interrupt enable/ disable, and interrupt
pending control. Interrupt with Reset(INTR)
is assigned to Port 0.

512

INT0 INT4/INTR

P1.0P1.7

I/O

I/O port with bit-programmable pins.
Configurable to input mode or output mode.
Pin circuits are either push-pull or n-
channel open-drain type. Pull-up resistors
are assignable by software.

1320

P2.0
P2.1
P2.2

I/O

3-bit I/O port with bit-programmable pins.
Configurable to input mode, push-pull
output mode, or n-channel open-drain
output mode. Input mode with pull-up
resistors are assignable by software. The
two pins of port 2 have high current drive
capability.

3
4
5

2123

REM/T0CK

, X

OUT

System clock input and output pins

2, 3

TEST

Test signal input pin (for factory use only;
must be connected to V

Power supply input pin

Ground pin

S3P80C5/C80C5/C80C8

ADDRESS SPACES

2-1

ADDRESS SPACES

OVERVIEW

The S3P80C5/C80C5/C80C8 microcontroller has two types of address space:

-- Internal program memory (ROM)

-- Internal register file

A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.

The S3C80C5 has an internal 15,872 byte programmable ROM, the S3C80C8 has an internal 8-Kbyte
programmable ROM. An external memory interface is not implemented. The 256-byte physical RAM space is
expanded into an addressable area of 320 bytes by the use of addressing modes.

There are 312 mapped registers in the internal register file. Of these, 272 are for general-purpose use. (This
number includes a 16-byte working register common area that is used as a " scratch area" for data operations, a
256 prime register area that is used for general purpose and stack operation). Eighteen 8-bit registers are used
for CPU and system control and 22 registers are mapped peripheral control and data registers.

S3P80C5/C80C5/C80C8

ADDRESS SPACES

2-3

REGISTER ARCHITECTURE

The S3P80C5/C80C5/C80C8 register file has 312 registers. The upper 64 bytes register files are addressed as
system control register and working register. The lower 192-byte area of the physical register file(00HBFH)
contains freely-addressable, general-purpose registers called prime registers. It can be also used for stack
operation.

The extension of register space into separately addressable sets is supported internally by addressing mode
restrictions.

Specific register types and the area (in bytes) they occupy in the S3P80C5/C80C5/C80C8 internal register space
are summarized in Table 2-1.

Table 2-1. S3P80C5/C80C5/C80C8 Register Type Summary

Register Type

Number of Bytes

General-purpose registers (including the 16-byte common working register area,
the 256-byte prime register area.)

272

CPU and system control registers

Mapped clock, peripheral, and I/O control and data registers

Total Addressable Bytes

312

S3P80C5/C80C5/C80C8

ADDRESS SPACES

2-5

REGISTER PAGE POINTER (PP)

The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using
an 8-bit data bus) into as many as 15 separately addressable register pages. Page addressing is controlled by
the register page pointer (PP, DFH). In the S3P80C5/C80C5/C80C8 microcontroller, a paged register file
expansion is not implemented and the register page pointer settings therefore always point to "page 0."

Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always
'0000', automatically selecting page 0 as the source and destination page for register addressing. These page
pointer (PP) register settings, as shown in Figure 2-3, should not be modified during normal operation.

DFH, Set 1, R/W

MSB

LSB

Dectination register page selection bits:

0 0 0 0

Destination: page 0

Source register page selection bits:

0 0 0 0

Source: page 0

NOTE:

In the S3C80C5/C80C8 microcontroller, only pate 0 is implemented.
A hardware reset operation writes the 4-bit destination and source values
shown above to the register pate pointer. These values should not be
modified.

Figure 2-3. Register Page Pointer (PP)

ADDRESS SPACES

S3P80C5/C80C5/C80C8

2-6

REGISTER SET 1

The term set 1 refers to the upper 64 bytes of the register file, locations C0HFFH.

In some S3C8-series microcontrollers, the upper 32-byte area of this 64-byte space (E0HFFH) is divided into
two 32-byte register banks, bank 0 and bank 1. The set register bank instructions SB0 or SB1 are used to
address one bank or the other. In the S3P80C5/C80C5/C80C8 microcontroller, bank 1 is not implemented. A
hardware reset operation therefore always selects bank 0 addressing, and the SB0 and SB1 instructions are not
necessary.

The upper 32-byte area of set 1 (FFHE0H) contains 26 mapped system and peripheral control registers. The
lower 32-byte area contains 16 system registers (DFHD0H) and a 16-byte common working register area (CFH
C0H). You can use the common working register area as a "scratch" area for data operations being performed in
other areas of the register file.

Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing. (For more information about
working register addressing, please refer to Section 3, "Addressing Modes," .)

REGISTER SET 2

The same 64-byte physical space that is used for set 1 locations C0HFFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. All set 2 locations (C0HFFH)
are addressed as part of page 0 in the S3P80C5/C80C5/C80C8 register space.

The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only
Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect
addressing mode or Indexed addressing mode.

The set 2 register area is commonly used for stack operations.

ADDRESS SPACES

S3P80C5/C80C5/C80C8

2-8

WORKING REGISTERS

Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as
consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.

Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except for the set 2 area.

The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:

-- One working register slice is 8 bytes (eight 8-bit working registers; R0R7 or R8R15)

-- One working register block is 16 bytes (sixteen 8-bit working registers; R0R15)

All of the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file.
The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.

After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0HCFH).

Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.

1 1 1 1 1 X X X

RP1 (Registers R8-R15)

RP0 (Registers R0-R7)

Slice 32

Slice 31

CFH
C0H

FFH
F8H
F7H
F0H

FH
8H
7H
0H

Slice 2

Slice 1

10H

Set 1
Only

0 0 0 0 0 X X X

Figure 2-5. 8-Byte Working Register Areas (Slices)

S3P80C5/C80C5/C80C8

ADDRESS SPACES

2-9

USING THE REGISTER POINTERS

Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0HC7H, and RP1 points to addresses C8HCFH.

To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see
Figures 2-6 and 2-7).

With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0HFFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.

The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see
Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous)
areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.

Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can
define the working register area very flexibly to support program requirements.

PROGRAMMING TIP -- Setting the Register Pointers

SRP

#70H

; RP0

70H, RP1

78H

SRP1

#48H

; RP0

no change, RP1

48H,

SRP0

#0A0H

; RP0

A0H, RP1

no change

CLR

RP0

; RP0

00H, RP1

no change

RP1,#0F8H

; RP0

no change, RP1

0F8H

FH (R15)

0H (R0)

16-Byte
Contiguous
Working
Register block

Contains 32

8-Byte Slices

RP0

RP1

8H
7H

0 0 0 0 1 X X X

0 0 0 0 0 X X X

8-Byte Slice

Figure 2-6. Contiguous 16-Byte Working Register Block

ADDRESS SPACES

S3P80C5/C80C5/C80C8

2-10

16-Byte
Contiguous
working
Register block

Contains 32

8-Byte Slices

0 0 0 0 0 X X X

RP1

1 1 1 1 0 X X X

RP0

0H (R0)

7H (R15)

F0H (R0)

F7H (R7)

8-Byte Slice

Figure 2-7. Non-Contiguous 16-Byte Working Register Block

PROGRAMMING TIP -- Using the RPs to Calculate the Sum of a Series of Registers

Calculate the sum of registers 80H85H using the register pointer. The register addresses 80H through 85H
contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:

SRP0

#80H

; RP0

80H

ADD

R0,R1

; R0

R0 + R1

ADC

R0,R2

; R0

R0 + R2 + C

ADC

R0,R3

; R0

R0 + R3 + C

ADC

R0,R4

; R0

R0 + R4 + C

ADC

R0,R5

; R0

R0 + R5 + C

The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used
to calculate the sum of these registers, the following instruction sequence would have to be used:

ADD

80H,81H

; 80H

(80H) + (81H)

ADC

80H,82H

; 80H

(80H) + (82H) + C

ADC

80H,83H

; 80H

(80H) + (83H) + C

ADC

80H,84H

; 80H

(80H) + (84H) + C

ADC

80H,85H

; 80H

(80H) + (85H) + C

Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.

S3P80C5/C80C5/C80C8

ADDRESS SPACES

2-11

REGISTER ADDRESSING

The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.

With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access all locations in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.

Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the
least significant byte is always stored in the next (+ 1) odd-numbered register.

Working register addressing differs from Register addressing because it uses a register pointer to identify a
specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.

MSB

LSB

Rn+1

n = Even address

Figure 2-8. 16-Bit Register Pair

ADDRESS SPACES

S3P80C5/C80C5/C80C8

2-14

PROGRAMMING TIP -- Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0HCFH,
using working register addressing mode only.

Example 1:

0C2H,40H

; Invalid addressing mode!

Use working register addressing instead:

SRP

#0C0H

R2,40H

; R2 (C2H)

the value in location 40H

Example 2:

ADD

0C3H,#45H

; Invalid addressing mode!

Use working register addressing instead:

SRP

#0C0H

ADD

R3,#45H

; R3 (C3H)

R3 + 45H

4-BIT WORKING REGISTER ADDRESSING

Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:

-- The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);

-- The five high-order bits in the register pointer select an 8-byte slice of the register space;

-- The three low-order bits of the 4-bit address select one of the eight registers in the slice.

As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.

Figure 2-12 shows a typical example of 4-bit working register addressing: The high-order bit of the instruction
'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

ADDRESS SPACES

S3P80C5/C80C5/C80C8

2-16

8-BIT WORKING REGISTER ADDRESSING

You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.

As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address; the
three low-order bits of the complete address are provided by the original instruction.

Figure 2-14 shows an example of 8-bit working register addressing: The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).

8-bit Logical
Address

8-bit Physical Address

Address

Selects
RP0 or RP1

RP1

RP0

Three low-
order Bits

These Address
Bits Indicate 8-bit
Working Register
Addressing

Figure 2-13. 8-Bit Working Register Addressing

ADDRESS SPACES

S3P80C5/C80C5/C80C8

2-18

SYSTEM AND USER STACKS

S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations.
The S3P80C5/C80C5/C80C8 architecture supports stack operations in the internal register file.

Stack Operations

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.

Stack Contents
After a Call
Instruction

Stack Contents
After an Interrupt

Top of

Stack

FLAGS

PCH

PCL

PCH

Top of
Stack

Low Address

High Address

Figure 2-15. Stack Operations

User-Defined Stacks

You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.

Stack Pointers (SPL)

Register location D9H contain the 8-bit stack pointer (SPL) that is used for system stack operations. After a reset,
the SPL value is undetermined. Because only internal memory 256-byte is implemented in
S3P80C5/C80C5/C80C8, the SPL must be initialized to an 8-bit value in the range 00HFFH.

ADDRESSING MODES

S3P80C5/C80C5/C80C8

3-2

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).
Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-
byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).

dst

Value used in

Instruction Execution

OPCODE

OPERAND

8-bit Register

File Address

Point to One

File

One-Operand

Instruction

(Example)

Sample Instruction:

DEC

CNTR

; Where CNTR is the label of an 8-bit register address

Program Memory

Figure 3-1. Register Addressing

4-bit

Working Register

Points to the

Working Register

(1 of 8)

Two-Operand

Instruction

(Example)

Sample Instruction:

ADD

R1, R2

; Where R1 and R2 are registers in the currently

selected working register area.

Program Memory

3 LSBs

RP0 or RP1

Selected
RP Points
to Start
of Working
Register
Block

MSB Points to

RP0 ot RP1

dst

OPCODE

src

OPERAND

Figure 3-2. Working Register Addressing

S3P80C5/C80C5/C80C8

ADDRESSING MODES

3-3

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of
the operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Remember, however, that locations C0HFFH in set 1 cannot be
accessed using Indirect Register addressing mode.

dst

Address of Operand

used by Instruction

OPCODE

ADDRESS

8-bit Register

File Address

Point to One

One-Operand

Instruction

(Example)

Sample Instruction:

@SHIFT ; Where SHIFT is the label of an 8-bit register address.

Program Memory

Value used in

Instruction Execution

OPERAND

Figure 3-3. Indirect Register Addressing to Register File

S3P80C5/C80C5/C80C8

ADDRESSING MODES

3-7

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory (if implemented). You cannot, however, access
locations C0HFFH in set 1 using Indexed addressing.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range 128
to +127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for
external data memory (if implemented).

dst/src

OPCODE

Two-Operand

Instruction

Example

Point to One of the

Working Register

(1 of 8)

Sample Instruction:

LD R0, #BASE[R1]

; Where BASE is an 8-bit immediate value

Program Memory

3 LSBs

Value used in

Instruction

OPERAND

INDEX

Base Address

RP0 or RP1

Selected RP
Points to
Start of
Working
Register
Block

MSB Points to

RP0 or RP1

Figure 3-7. Indexed Addressing to Register File

ADDRESSING MODES

S3P80C5/C80C5/C80C8

3-10

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Sample Instructions:

LDC

R5,1234H ; The values in the program address (1234H)

are loaded into register R5.

LDE

R5,1234H ; Identical operation to LDC example, except that

external program memory is accessed.

dst/src

OPCODE

Program Memory

"0" or "1"

Lower Address Byte

LSB Selects Program
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory

Memory
Address
Used

Upper Address Byte

Program or

Data Memory

NOTE:

LDE command is not available, because an external interface
is not implemented for the S3C80C5/C80C8/C804C.

Figure 3-10. Direct Addressing for Load Instructions

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-2

Table 4-1. Mapped Registers (Set 1)

Register Name

Mnemonic

Decimal

Hex

R/W

Timer 0 counter

T0CNT

208

D0H

(note)

Timer 0 data register

T0DATA

209

D1H

R/W

Timer 0 control register

T0CON

210

D2H

R/W

Basic timer control register

BTCON

211

D3H

R/W

Clock control register

CLKCON

212

D4H

R/W

System flags register

FLAGS

213

D5H

R/W

RP0

214

D6H

R/W

RP1

215

D7H

R/W

Locations D8H is not mapped.

Stack pointer (low byte)

SPL

217

D9H

R/W

Instruction pointer (high byte)

IPH

218

DAH

R/W

Instruction pointer (low byte)

IPL

219

DBH

R/W

Interrupt request register

IRQ

220

DCH

(note)

Interrupt mask register

IMR

221

DDH

R/W

System mode register

SYM

222

DEH

R/W

223

DFH

R/W

Port 0 data register

224

E0H

R/W

Port 1 data register

225

E1H

R/W

Port 2 data register

226

E2H

R/W

Location E3HE6H is not mapped.

Port 0 pull-up resistor enable register

P0PUR

231

E7H

R/W

Port 0 control register (high byte)

P0CONH

232

E8H

R/W

Port 0 control register (low byte)

P0CONL

233

E9H

R/W

Port 1 control register (high byte)

P1CONH

234

EAH

R/W

Port 1 control register (low byte)

P1CONL

235

EBH

R/W

Port 1 pull-up resistor enable register

P1PUR

236

ECH

R/W

Location EDHEFH is not mapped.

Port 2 control register

P2CON

239

F0H

R/W

Port 0 interrupt enable register

P0INT

241

F1H

R/W

Port 0 interrupt pending register

P0PND

242

F2H

R/W

Counter A control register

CACON

243

F3H

R/W

Counter A data register (high byte)

CADATAH

244

F4H

R/W

Counter A data register (low byte)

CADATAL

245

F5H

R/W

Timer 1 counter register (high byte)

T1CNTH

246

F6H

(note)

Timer 1 counter register (low byte)

T1CNTL

247

F7H

(note)

Timer 1 data register (high byte)

T1DATAH

248

F8H

R/W

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-4

FLAGS - System Flags Register

Carry Flag (C)

Zero Flag (Z)

Bit Identifier

RESET

Value

Read/Write

Bit Addressing Mode

R = Read-only
W = Write-only
R/W = Read/write
'-' = Not used

Addressing mode or
modes you can use
to modify register
values

RESET value notation:
'-' = Not used
'x' = Undetermined value
'0' = Logic zero
'1' = Logic one

Bit number(s) that is/are appended to
the register name for bit addressing

Name of individual
bit or related bits

Sign Flag (S)

Operation does not generate a carry or borrow condition

Operation generates carry-out or borrow into high-order bit 7

Operation result is a non-zero value

Operation result is zero

Operation generates positive number (MSB = "0")

Operation generates negative number (MSB = "1")

Description of the
effect of specific
bit settings

Set 1

D5H

R/W

Bit number:
MSB = Bit 7
LSB = Bit 0

Figure 4-1. Register Description Format

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-5

BTCON

-- Basic Timer Control Register

D3H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Bit Addressing

.7.4

Watchdog Timer Function Disable Code (for System Reset)

Disable watchdog timer function

Any other value

Enable watchdog timer function

.3.2

Basic Timer Input Clock Selection Bits

OSC

/4096

OSC

/1024

OSC

/128

Invalid setting; not used for S3P80C5/C80C5/C80C8.

Basic Timer Counter Clear Bit

(1)

No effect

Clear the basic timer counter value

Clock Frequency Divider Clear Bit for Basic Timer and Timer 0

(2)

No effect

Clear both clock frequency dividers

NOTES:
1.

When you write a "1" to BTCON.1, the basic timer counter value is cleared to '00H'. Immediately following the write
operation, the BTCON.1 value is automatically cleared to "0".

When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-6

CACON

Counter A Control Register

F3H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

Counter A Input Clock Selection Bits

OSC

.5.4

Counter A Interrupt Timing Selection Bits

Elapsed time for Low data value

Elapsed time for High data value

Elapsed time for combined Low and High data values

Invalid setting; not used for S3C80C5/C80C8.

Counter A Interrupt Enable Bit

Disable interrupt

Enable interrupt

Counter A Start Bit

Stop counter A

Start counter A

Counter A Mode Selection Bit

One-shot mode

Repeating mode

Counter A Output flip-flop Control Bit

Flip-flop Low level (T-FF = Low)

Flip-flop High level (T-FF = High)

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-7

CLKCON

System Clock Control Register

D4H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

Oscillator IRQ Wake-up Function Enable Bit

Not used for S3P80C5/C80C5/C80C8.

.6.5

Main Oscillator Stop Control Bits

Not used for S3P80C5/C80C5/C80C8.

.4.3

CPU Clock (System Clock) Selection Bits

(1)

OSC

/16

OSC

(non-divided)

.2.0

Subsystem Clock Selection Bit

(2)

Invalid setting for S3P80C5/C80C5/C80C8.

Other value

Select main system clock (MCLK)

NOTES:
1.

After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.

These selection bits are required only for systems that have a main clock and a subsystem clock. The

S3P80C5/C80C5/C80C8 uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-8

EMT

External Memory Timing Register

(note)

FEH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

External

WAIT

Input Function Enable Bit

Disable

WAIT

input function for external device

Enable

WAIT

input function for external device

Slow Memory Timing Enable Bit

Disable

WAIT

input function for external device

Enable

WAIT

input function for external device

.5.4

Program Memory Automatic Wait Control Bits

No wait

Wait one cycle

Wait two cycles

Wait three cycles

.3.2

Data Memory Automatic Wait Control Bits

No wait

Wait one cycle

Wait two cycles

Wait three cycles

Stack Area Selection Bit

Select internal register file area

Select external data memory area

Not used for S3P80C5/C80C5/C80C8.

NOTE: The EMT register is not used for S3P80C5/C80C5/C80C8, because an external peripheral interface is not

implemented in the S3P80C5/C80C5/C80C8.
The program initialization routine should clear the EMT register to '00H' following a reset. Modification of EMT
values during normal operation may cause a system malfunction.

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-9

FLAGS --

System Flags Register

D5H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

Carry Flag (C)

Operation does not generate a carry or borrow condition

Operation generates a carry-out or borrow into high-order bit 7

Zero Flag (Z)

Operation result is a non-zero value

Operation result is zero

Sign Flag (S)

Operation generates a positive number (MSB = "0")

Operation generates a negative number (MSB = "1")

Overflow Flag (V)

Operation result is

+127 or

128

Operation result is > +127 or < 128

Decimal Adjust Flag (D)

Add operation completed

Subtraction operation completed

Half-Carry Flag (H)

No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

Fast Interrupt Status Flag (FIS)

Interrupt return (IRET) in progress (when read)

Fast interrupt service routine in progress (when read)

Bank Address Selection Flag (BA)

Bank 0 is selected
(normal setting for S3C80C5/C80C8)

Invalid selection (bank 1 is not implemented)

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-10

IMR

-- Interrupt Mask Register

DDH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7P0.4

Enable (un-mask)

Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3P0.0

Disable (mask)

Enable (un-mask)

Not used for S3P80C5/C80C5/C80C8.

Interrupt Level 4 (IRQ4) Enable Bit; Counter A Interrupt

Disable (mask)

Enable (un-mask)

.3.2

Not used for S3P80C5/C80C5/C80C8.

Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow

Disable (mask)

Enable (un-mask)

Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow

Disable (mask)

Enable (un-mask)

NOTES:
1.

When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

Interrupt levels IRQ2, IRQ3 and IRQ5 are not used in the S3P80C5/C80C5/C80C8 interrupt structure.

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-11

IPH

-- Instruction Pointer (High Byte)

DAH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.0

Instruction Pointer Address (High Byte)

The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15IP8). The lower byte of the IP address is located in the IPL
register (DBH).

IPL

-- Instruction Pointer (Low Byte)

DBH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.0

Instruction Pointer Address (Low Byte)

The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7IP0). The upper byte of the IP address is located in the IPH
register (DAH).

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-12

IPR

-- Interrupt Priority Register

FFH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Bit Addressing

.7, .4, and .1

Priority Control Bits for Interrupt Groups A, B, and C

Group priority undefined

B > C > A

A > B > C

B > A > C

C > A > B

C > B > A

A > C > B

Group priority undefined

Interrupt Subgroup C Priority Control Bit

IRQ6 > IRQ7

IRQ7 > IRQ6

.5, .3

Not used for S3P80C5/C80C5/C80C8.

Input Group B Priority Control Bit

IRQ4

Interrupt Group A Priority Control Bit

IRQ0 > IRQ1

IRQ1 > IRQ0

NOTE: The S3P80C5/C80C5/C80C8 interrupt structure uses only five levels:

IRQ0, IRQ1, IRQ4, IRQ6IRQ7. Because IRQ2, IRQ3, IRQ5 are not recognized, the interrupt subgroup B and
group C settings (IPR.2,.3 and IPR.5) are not evaluated.

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-13

IRQ

-- Interrupt Request Register

DCH

Set 1

Bit Identifier

RESET

Value

Read/Write

Addressing Mode

Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7P0.4

Not pending

Pending

Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3P0.0

Not pending

Pending

Not used for S3P80C5/C80C5/C80C8.

Level 4 (IRQ4) Request Pending Bit; Counter A Interrupt

Not pending

Pending

.3.2

Not used for S3P80C5/C80C5/C80C8.

Level 1 (IRQ1) Request Pending Bit; Timer 1 Match or Overflow

Not pending

Pending

Level 0 (IRQ0) Request Pending Bit; Timer 0 Match or Overflow

Not pending

Pending

NOTE: Interrupt level IRQ2, IRQ3 and IRQ5 is not used in the S3P80C5/C80C5/C80C8 interrupt structure.

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-14

P0CONH

-- Port 0 Control Register (High Byte)

E8H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

P0.7/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.5.4

P0.6/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.3.2

P0.5/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1.0

P0.4/INT4 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:
1.

The INT4 external interrupts at the P0.7P0.4 pins share the same interrupt level (IRQ7) and interrupt vector
address (E8H).

You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-15

P0CONL

-- Port 0 Control Register (Low Byte)

E9H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

P0.3/INT3 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.5.4

P0.2/INT2 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.3.2

P0.1/INT1 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

.1.0

P0.0/INT0 Mode Selection Bits

C-MOS input mode; interrupt on falling edges

C-MOS input mode; interrupt on rising and falling edges

Push-pull output mode

C-MOS input mode; interrupt on rising edges

NOTES:
1.

The INT3INT0 external interrupts at P0.3P0.0 are interrupt level IRQ6. Each interrupt has a separate vector
address.

You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-16

P0INT

-- Port 0 External Interrupt Enable Register

F1H

Set 1

Bit Identifier

RESET

Value

Read/Write

Addressing Mode

P0.7 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.6 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.5 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.4 External Interrupt (INT4) Enable Bit

Disable interrupt

Enable interrupt

P0.3 External Interrupt (INT3) Enable Bit

Disable interrupt

Enable interrupt

P0.2 External Interrupt (INT2) Enable Bit

Disable interrupt

Enable interrupt

P0.1 External Interrupt (INT1) Enable Bit

Disable interrupt

Enable interrupt

P0.0 External Interrupt (INT0) Enable Bit

Disable interrupt

Enable interrupt

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-17

P0PND

-- Port 0 External Interrupt Pending Register

F2H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

P0.7 External Interrupt (INT4) Pending Flag

(note)

No P0.7 external interrupt pending (when read)

P0.7 external interrupt is pending (when read)

P0.6 External Interrupt (INT4) Pending Flag

No P0.6 external interrupt pending (when read)

P0.6 external interrupt is pending (when read)

P0.5 External Interrupt (INT4) Pending Flag

No P0.5 external interrupt pending (when read)

P0.5 external interrupt is pending (when read)

P0.4 External Interrupt (INT4) Pending Flag

No P0.4 external interrupt pending (when read)

P0.4 external interrupt is pending (when read)

P0.3 External Interrupt (INT3) Pending Flag

No P0.3 external interrupt pending (when read)

P0.3 external interrupt is pending (when read)

P0.2 External Interrupt (INT2) Pending Flag

No P0.2 external interrupt pending (when read)

P0.2 external interrupt is pending (when read)

P0.1 External Interrupt (INT1) Pending Flag

No P0.1 external interrupt pending (when read)

P0.1 external interrupt is pending (when read)

P0.0 External Interrupt (INT0) Pending Flag

No P0.0 external interrupt pending (when read)

P0.0 external interrupt is pending (when read)

NOTE: To clear an interrupt pending condition, write a "0" to the appropriate pending flag. Writing a "1" to an interrupt

pending flag (POND.07) has no effect.

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-18

P0PUR

-- Port 0 Pull-up Resistor Enable Register

E7H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

P0.7 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.6 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.5 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.4 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.3 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.2 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.1 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

P0.0 Pull-up Resistor Enable Bit

Enable pull-up resistor

Disable pull-up resistor

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-21

P1PUR

-- Port 0 Pull-up Resistor Enable Register

ECH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

P1.7 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.6 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.5 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.4 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.3 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.2 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.1 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

P1.0 Pull-up Resistor Enable Bit

Disable pull-up resistor

Enable pull-up resistor

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-22

P2CON

-- Port 2 Control Register

F0H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

P2.2 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

.5.4

P2.1 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

.3.2

P2.0 Mode Selection Bits

C-MOS input mode

Open-drain output mode

Push-pull output mode

C-MOS input with pull up mode

P2.1 Alternative Function Selection Bits

Normal I/O function

REM/T0CK function

P2.0 Alternative Function Selection Bits

Normal I/O function

T0PWN function

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-24

RP0

-- Register Pointer 0

D6H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.3

Destination Register Page Selection Bits

Register pointer 0 can independently point to one of the 24 8-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1, selecting the 8-byte working register
slice C0HC7H.

.2.0

Not used for S3P80C5/C80C5/C80C8.

RP1

-- Register Pointer 1

D7H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.3

Register Pointer 1 Address Value

Register pointer 1 can independently point to one of the 24 8-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, selecting the 8-byte working register
slice C8HCFH.

.2.0

Not used for S3P80C5/C80C5/C80C8.

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-25

SPL

-- Stack Pointer (Low Byte)

D9H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.0

Stack Pointer Address (Low Byte)

The SP value is undefined following a reset.

STOPCON

-- Stop Control Register

FBH

Set 1

Bit Identifier

RESET

Value

Read/Write

Addressing Mode

.7.0

Stop Control Register enable bits

Enable STOPCON

NOTES:
1.

To get into STOP mode, stop control register must be enabled just before STOP instruction.

When STOP mode is released, stop control register (STOPCON) value is cleared automatically.

It is prohibited to write another value into STOPCON.

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-26

SYM

-- System Mode Register

DEH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

Tri-State External Interface Control Bit

(1)

Normal operation (disable tri-state operation)

Set external interface lines to high impedance (enable tri-state operation)

.6.5

Not used for S3P80C5/C80C5/C80C8.

.4.2

Fast Interrupt Level Selection Bits

(2)

IRQ0

IRQ1

Not used for

S3P80C5/C80C5/C80C8.

IRQ6

IRQ7

Fast Interrupt Enable Bit

(3)

Disable fast interrupt processing

Enable fast interrupt processing

Global Interrupt Enable Bit

(4)

Disable global interrupt processing

Enable global interrupt processing

NOTES:
1.

Because an external interface is not implemented for the S3P80C5/C80C5/C80C8, SYM.7 must always be "0".

You can select only one interrupt level at a time for fast interrupt processing.

Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2SYM.4.

Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"
to SYM.0).

S3P80C5/C80C5/C80C8

CONTROL REGISTERS

4-27

T0CON

-- Timer 0 Control Register

D2H

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

Timer 0 Input Clock Selection Bits

OSC

/4096

OSC

/256

OSC

External clock input (at the T0CK pin, P2.1)

.5.4

Timer 0 Operating Mode Selection Bits

Interval timer mode (counter cleared by match signal)

Overflow mode (OVF interrupt can occur)

PWM mode (OVF interrupt can occur)

Timer 0 Counter Clear Bit

No effect (when write)

Clear T0 counter, T0CNT (when write)

Timer 0 Overflow Interrupt Enable Bit

(note)

Disable T0 overflow interrupt

Enable T0 overflow interrupt

Timer 0 Match Interrupt Enable Bit

Disable T0 match interrupt

Enable T0 match interrupt

Timer 0 Match Interrupt Pending Flag

No T0 match interrupt pending (when read)

Clear T0 match interrupt pending condition (when write)

T0 match interrupt is pending (when read)

No effect (when write)

NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0

match/ capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine.

CONTROL REGISTERS

S3P80C5/C80C5/C80C8

4-28

T1CON

-- Timer 1 Control Register

FAH

Set 1

Bit Identifier

RESET

Value

Read/Write

R/W

Addressing Mode

.7.6

Timer 1 Input Clock Selection Bits

OSC

/16

Internal clock (counter a flip-flop, T-FF)

.5.4

Timer 1 Operating Mode Selection Bits

Interval timer mode (counter cleared by match signal)

Overflow mode (OVF interrupt can occur)

Timer 1 Counter Clear Bit

No effect (when write)

Clear T1 counter, T1CNT (when write)

Timer 1 Overflow Interrupt Enable Bit

(note)

Disable T1 overflow interrupt

Enable T1 overflow interrupt

Timer 1 Match/Capture Interrupt Enable Bit

Disable T1 match interrupt

Enable T1 match interrupt

Timer 1 Match/Capture Interrupt Pending Flag

No T1 match interrupt pending (when read)

Clear T1 match interrupt pending condition (when write)

T1 match interrupt is pending (when read)

No effect (when write)

NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/

capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine.

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-1

INTERRUPT STRUCTURE

OVERVIEW

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM87 CPU
recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level
has more than one vector address, the vector priorities are established in hardware. A vector address can be
assigned to one or more sources.

Levels

Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0IRQ7, also called level 0 level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3P80C5/C80C5/C80C8 interrupt structure recognizes five interrupt levels.

The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are
simply identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt
levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled
by IPR settings lets you define more complex priority relationships between different levels.

Vectors

Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all.
The maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors
used for S3C8-series devices is always much smaller.) If an interrupt level has more than one vector address, the
vector priorities are set in hardware. The S3P80C5/C80C5/C80C8 uses ten vectors. One vector address is
shared by four interrupt sources.

Sources

A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for
example. Each vector can have several interrupt sources. In the S3P80C5/C80C5/C80C8 interrupt structure,
there are thirteen possible interrupt sources.

When a service routine starts, the respective pending bit is either cleared automatically by hardware or is must
be cleared "manually" by program software. The characteristics of the source's pending mechanism determine
which method is used to clear its respective pending bit.

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-2

INTERRUPT TYPES

The three components of the S3C8 interrupt structure described above -- levels, vectors, and sources -- are
combined to determine the interrupt structure of an individual device and to make full use of its available
interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1,
2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1):

Type 1:

One level (IRQn) + one vector (V

) + one source (S

)

Type 2:

One level (IRQn) + one vector (V

) + multiple sources (S

)

Type 3:

One level (IRQn) + multiple vectors (V

) + multiple sources (S

, S

n+1

n+m

)

In the S3P80C5/C80C5/C80C8 microcontroller, all three interrupt types are implemented.

Vectors

Sources

Levels

Type 2:

IRQn

Type 3:

IRQn

Type 1:

IRQn

n +

NOTES:
1. The number of S

and V

value is expandable.

2. In the S3P80C5/C80C5/C80C8 implementation, interrupt types 1, 2, and 3 is used.

Figure 5-1. S3C8-Series Interrupt Types

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-3

S3P80C5/C80C5/C80C8 INTERRUPT STRUCTURE

The S3P80C5 microcontroller supports two kinds interrupt structure

-- Vectored Interrupt

-- Non vectored interrupt (Reset interrupt): INTR

The S3P80C5/C80C5/C80C8 microcontroller supports thirteen interrupt sources. Nine of the interrupt sources
have a corresponding interrupt vector address; the remaining four interrupt sources share the same vector
address. Five interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in
Figure 5-2.

When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first. (The relative priorities of multiple interrupts within a
single level are fixed in hardware.)

When the CPU grants an interrupt request, interrupt processing starts: All other interrupts are disabled and the
program counter value and state flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed. The S3P80C5/C80C5/C80C8 microcontroller supports non vectored interrupt -
Interrupt with Reset(INTR) - to occur interrupt with system reset. The Interrupt with Reset(INTR) has nothing to do
with interrupt levels, vectors and the registers that are related to interrupt setting. It occurs only according to the
"P0" during " STOP " regardless any other things. Namely, only when a falling/rising edge occurs at any pin of
Port 0 during STOP status, this INTR and a system reset occurs even though SYM.0 is "0"(Disable interrupt). But
it dose not occurs while the oscillation - "IDLE" or "OPERATING" status- even though a falling/rising edge occurs
at port 0.

Following is the sequence that occurs Interrupt with Reset(INTR).

The oscillation status is "freeze" : STOP mode

A falling/rising edge is detected to any pin of Port 0.

INTR occurs and it makes system reset.

STOP mode is released by this system reset.

NOTE

Because H/W reset occurs whenever INTR occurs. A user should aware of the each ports, system
register, control register etc."

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-6

Table 5-1. S3P80C5/C80C5/C80C8 Interrupt Vectors

Vector Address

Interrupt Source

Request

Reset/Clear

Decimal

Value

Hex

Value

Interrupt

Level

Priority in

Level

H/W

S/W

254

100H

Basic timer overflow

RESET

252

FCH

Timer 0 (match)

IRQ0

250

FAH

Timer 0 overflow

246

F6H

Timer 1 (match)

IRQ1

244

F4H

Timer 1 overflow

236

ECH

Counter A

IRQ4

232

E8H

P0.7 external interrupt

IRQ7

232

E8H

P0.6 external interrupt

232

E8H

P0.5 external interrupt

232

E8H

P0.4 external interrupt

230

E6H

P0.3 external interrupt

IRQ6

228

E4H

P0.2 external interrupt

226

E2H

P0.1 external interrupt

224

E0H

P0.0 external interrupt

NOTES:
1.

Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on.

If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-7

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur, and according to the established priorities.

NOTE

The system initialization routine that is executed following a reset must always contain an EI instruction
to globally enable the interrupt structure.

During normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can
manipulate SYM.0 directly to enable or disable interrupts, we recommend that you use the EI and DI instructions
instead.

SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS

In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:

-- The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.

-- The interrupt priority register, IPR, controls the relative priorities of interrupt levels.

-- The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to

each interrupt source).

-- The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable

fast interrupts and control the activity of external interface, if implemented).

Table 5-2. Interrupt Control Register Overview

Control Register

R/W

Function Description

Interrupt mask register

IMR

R/W

Bit settings in the IMR register enable or disable interrupt
processing for each of the five interrupt levels: IRQ0, IRQ1,
IRQ4, and IRQ6IRQ7.

Interrupt priority register

IPR

R/W

Controls the relative processing priorities of the interrupt
levels. The five levels of the S3P80C5/C80C5/C80C8 are
organized into three groups: A, B, and C. Group A is IRQ0 and
IRQ1, group B is IRQ4, and group C is IRQ6, and IRQ7.

Interrupt request register

IRQ

This register contains a request pending bit for each interrupt
level.

System mode register

SYM

R/W

Dynamic global interrupt processing enable/ disable, fast
interrupt processing, and external interface control (An
external memory interface is not implemented in the
S3P80C5/C80C5/C80C8 microcontroller).

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-8

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source.
The system-level control points in the interrupt structure are, therefore:

-- Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 )

-- Interrupt level enable/disable settings (IMR register)

-- Interrupt level priority settings (IPR register)

-- Interrupt source enable/disable settings in the corresponding peripheral control registers

NOTE

When writing the part of your application program that handles interrupt processing, be sure to include
the necessary register file address (register pointer) information.

IRQ0, IRQ1,

IRQ4 and IRQ6- IRQ7

Interrupts

Interrupt Request

Polling
Cycle

Interrupt Mask

RESET

Interrupt Priority

Vector
Interrupt
Cycle

Global Interrupt Control

(EI, DI, or SYM.0

manipulation)

Figure 5-4. Interrupt Function Diagram

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-9

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by that peripheral (see Table 5-3).

Table 5-3. Interrupt Source Control and Data Registers

Interrupt Source

Interrupt Level

Register(s)

Location(s) in Set 1

Timer 0 match or timer 0
overflow

IRQ0

T0CON

(note)

T0DATA

D2H
D1H

Timer 1 match or timer 1
overflow

IRQ1

T1CON

(note)

T1DATAH, T1DATAL

FAH
F8H, F9H

Counter A

IRQ4

CACON
CADATAH, CADATAL

F3H
F4H, F5H

P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt

IRQ7

P0CONH
P0INT
P0PND

E8H
F1H
F2H

P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt

IRQ6

P0CONL
P0INT
P0PND

E9H
F1H
F2H

NOTE: Because the timer 0 and timer 1 overflow interrupts are cleared by hardware, the T0CON and T1CON registers

control only the enable/disable functions. The T0CON and T1CON registers contain enable/disable and pending
bits for the timer 0 and timer 1 match interrupts, respectively.

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-10

SYSTEM MODE REGISTER (SYM)

The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to
control fast interrupt processing (see Figure 5-5).

A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value for fast interrupt level selection, SYM.4SYM.2,
is undetermined.

The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which
follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to
enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this
purpose.

System Mode Register (SYM)

DEH, Set 1, R/W

Global interrupt enable bit:
0 = Disable all interrupts
1 = Enable all interrupts

Not used for the S3C80C5/C80C8.

External interface
tri-state enable bit:
0 = Normal (Tri-state)
1 = High (Tri-state)

Fast interrupt enable bit:
0 = Disable fast interrupt
1 = Enable fast interrupt

Fast interrupt level
selection bits:

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

IRQ0
IRQ1
Not used
Not used
Not used
Not used
IRQ6
IRQ7

NOTE:

An external memory interface is not implemented.

MSB

LSB

Figure 5-5. System Mode Register (SYM)

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-11

INTERRUPT MASK REGISTER (IMR)

The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual
interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required
settings by the initialization routine.

Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit
of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a
level's IMR bit to "1", interrupt processing for the level is enabled (not masked).

The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions
using the Register addressing mode.

Interrupt Mask Register (IMR)

DDH, Set 1, R/W

IRQ0

IRQ1

Not used

IRQ4

Not used

IRQ6

IRQ7

Interrupt level enable bits (7-6, 4, 1, 0):
0 = Disable (mask) interrupt
1 = Enable (un-mask) interrupt

MSB

LSB

Figure 5-6. Interrupt Mask Register (IMR)

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-12

INTERRUPT PRIORITY REGISTER (IPR)

The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels
used in the microcontroller's interrupt structure. After a reset, all IPR bit values are undetermined and must
therefore be written to their required settings by the initialization routine.

When more than one interrupt source is active, the source with the highest priority level is serviced first. If both
sources belong to the same interrupt level, the source with the lowest vector address usually has priority (This
priority is fixed in hardware).

To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5-7):

Group A

IRQ0, IRQ1

Group B

IRQ4

Group C

IRQ6, IRQ7

IPR

Group B

IPR

Group C

IRQ4

IRQ6

IRQ7

IPR

Group A

IRQ1

IRQ0

Figure 5-7. Interrupt Request Priority Groups

As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting '001B' for these bits would select the group relationship B > C > A; the setting '101B'
would select the relationship C > B > A.

The functions of the other IPR bit settings are as follows:

-- IPR.5 controls the relative priorities of group C interrupts.

-- Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2,

3, and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B. In the
S3P80C5/C80C5/C80C8 implementation, interrupt levels 2 and 3 are not used. Therefore, IPR.2 and IPR.3
settings are not evaluated, as IRQ4 is the only remaining level in the group.

-- IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-14

INTERRUPT REQUEST REGISTER (IRQ)

You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for
all levels in the microcontroller's interrupt structure. Each bit corresponds to the interrupt level of the same
number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued
for that level; a "1" indicates that an interrupt request has been generated for that level.

IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of
the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of
specific interrupt levels. After a reset, all IRQ status bits are cleared to "0".

You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.

Interrupt Request Register (IRQ)

DCH, Set 1, Read-only

MSB

LSB

IRQ1

Not

used

Not

used

IRQ4

Not

used

IRQ6

IRQ7

IRQ0

Interrupt level request pending bits:
0 = Interrupt level is not pending
1 = Interrupt level is pending

Figure 5-9. Interrupt Request Register (IRQ)

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-15

INTERRUPT PENDING FUNCTION TYPES

Overview

There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt
service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine.

Pending Bits Cleared Automatically by Hardware

For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is
waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service
routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or
written by application software.

In the S3P80C5/C80C5/C80C8 interrupt structure, the timer 0 and timer 1 overflow interrupts (IRQ0 and IRQ1),
and the counter A interrupt (IRQ4) belong to this category of interrupts whose pending condition is cleared
automatically by hardware.

Pending Bits Cleared by the Service Routine

The second type of pending bit must be cleared by program software. The service routine must clear the
appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written
to the corresponding pending bit location in the source's mode or control register.

In the S3P80C5/C80C5/C80C8 interrupt structure, pending conditions for all interrupt sources except the timer 0
and timer 1 overflow interrupts and the counter A borrow interrupt, must be cleared by the interrupt service
routine.

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-16

INTERRUPT SOURCE POLLING SEQUENCE

The interrupt request polling and servicing sequence is as follows:

A source generates an interrupt request by setting the interrupt request bit to "1".

The CPU polling procedure identifies a pending condition for that source.

The CPU checks the source's interrupt level.

The CPU generates an interrupt acknowledge signal.

Interrupt logic determines the interrupt's vector address.

The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).

The CPU continues polling for interrupt requests.

INTERRUPT SERVICE ROUTINES

Before an interrupt request can be serviced, the following conditions must be met:

-- Interrupt processing must be globally enabled (EI, SYM.0 = "1")

-- The interrupt level must be enabled (IMR register)

-- The interrupt level must have the highest priority if more than one level is currently requesting service

-- The interrupt must be enabled at the interrupt's source (peripheral control register)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle.
The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.

Save the program counter (PC) and status flags to the system stack.

Branch to the interrupt vector to fetch the address of the service routine.

Pass control to the interrupt service routine.

When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores
the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request.

S3P80C5/C80C5/C80C8

INTERRUPT STRUCTURE

5-17

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM (00HFFH) contains the addresses of interrupt service routines that
correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence:

Push the program counter's low-byte value to the stack.

Push the program counter's high-byte value to the stack.

Push the FLAG register values to the stack.

Fetch the service routine's high-byte address from the vector location.

Fetch the service routine's low-byte address from the vector location.

Branch to the service routine specified by the concatenated 16-bit vector address.

NOTE

A 16-bit vector address always begins at an even-numbered ROM address within the range 00HFFH.

NESTING OF VECTORED INTERRUPTS

It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,
you must follow these steps:

Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).

Load the IMR register with a new mask value that enables only the higher priority interrupt.

Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).

When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the
previous mask value from the stack (POP IMR).

Execute an IRET.

Depending on the application, you may be able to simplify the above procedure to some extent.

INSTRUCTION POINTER (IP)

The instruction pointer (IP) is used by all S3C8-series microcontrollers to control the optional high-speed interrupt
processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The IP register names
are IPH (high byte, IP15IP8) and IPL (low byte, IP7IP0).

FAST INTERRUPT PROCESSING

The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in
approximately six clock cycles instead of the usual 16 clock cycles. To select a specific interrupt level for fast
interrupt processing, you write the appropriate 3-bit value to SYM.4SYM.2. Then, to enable fast interrupt
processing for the selected level, you set SYM.1 to "1".

INTERRUPT STRUCTURE

S3P80C5/C80C5/C80C8

5-18

FAST INTERRUPT PROCESSING (Continued)

Two other system registers support fast interrupt processing:

-- The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the

program counter values), and

-- When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated

NOTE

For the S3P80C5/C80C5/C80C8 microcontroller, the service routine for any one of the five interrupt
levels: IRQ0, IRQ1, IRQ4 or IRQ6IRQ7, can be selected for fast interrupt processing.

Procedure for Initiating Fast Interrupts

To initiate fast interrupt processing, follow these steps:

Load the start address of the service routine into the instruction pointer (IP).

Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4SYM.2)

Write a "1" to the fast interrupt enable bit in the SYM register.

Fast Interrupt Service Routine

When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:

The contents of the instruction pointer and the PC are swapped.

The FLAG register values are written to the FLAGS' ("FLAGS prime") register.

The fast interrupt status bit in the FLAGS register is set.

The interrupt is serviced.

Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.

The content of FLAGS' ("FLAGS prime") is copied automatically back to the FLAGS register.

The fast interrupt status bit in FLAGS is cleared automatically.

Relationship to Interrupt Pending Bit Types

As described previously, there are two types of interrupt pending bits: One type is automatically cleared by
hardware after the interrupt service routine is acknowledged and executed, and the other type must be cleared by
the application program's interrupt service routine. You can select fast interrupt processing for interrupts with
either type of pending condition clear function -- by hardware or by software.

Programming Guidelines

Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-1

INSTRUCTION SET

OVERVIEW

The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8
microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the
instruction set include:

-- A full complement of 8-bit arithmetic and logic operations, including multiply and divide

-- No special I/O instructions (I/O control/data registers are mapped directly into the register file)

-- Decimal adjustment included in binary-coded decimal (BCD) operations

-- 16-bit (word) data can be incremented and decremented

-- Flexible instructions for bit addressing, rotate, and shift operations

DATA TYPES

The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can
be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least
significant (right-most) bit.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory
addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."

ADDRESSING MODES

There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA),
Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please
refer to Section 3, "Addressing Modes."

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-2

Table 6-1. Instruction Group Summary

Mnemonic

Operands

Instruction

Load Instructions

CLR

dst

Clear

dst, src

Load

LDB

dst, src

Load bit

LDE

dst, src

Load external data memory

LDC

dst, src

Load program memory

LDED

dst, src

Load external data memory and decrement

LDCD

dst, src

Load program memory and decrement

LDEI

dst, src

Load external data memory and increment

LDCI

dst, src

Load program memory and increment

LDEPD

dst, src

Load external data memory with pre-decrement

LDCPD

dst, src

Load program memory with pre-decrement

LDEPI

dst, src

Load external data memory with pre-increment

LDCPI

dst, src

Load program memory with pre-increment

LDW

dst, src

Load word

POP

dst

Pop from stack

POPUD

dst, src

Pop user stack (decrementing)

POPUI

dst, src

Pop user stack (incrementing)

PUSH

Src

Push to stack

PUSHUD

dst, src

Push user stack (decrementing)

PUSHUI

dst, src

Push user stack (incrementing)

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-4

Table 6-1. Instruction Group Summary (Continued)

Mnemonic

Operands

Instruction

Program Control Instructions

BTJRF

dst,src

Bit test and jump relative on false

BTJRT

dst,src

Bit test and jump relative on true

CALL

dst

Call procedure

CPIJE

dst,src

Compare, increment and jump on equal

CPIJNE

dst,src

Compare, increment and jump on non-equal

DJNZ

r,dst

Decrement register and jump on non-zero

ENTER

Enter

EXIT

Exit

IRET

Interrupt return

cc,dst

Jump on condition code

dst

Jump unconditional

cc,dst

Jump relative on condition code

RET

Return

WFI

Wait for interrupt

Bit Manipulation Instructions

BAND

dst,src

Bit AND

BCP

dst,src

Bit compare

BITC

dst

Bit complement

BITR

dst

Bit reset

BITS

dst

Bit set

BOR

dst,src

Bit OR

BXOR

dst,src

Bit XOR

TCM

dst,src

Test complement under mask

dst,src

Test under mask

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-6

FLAGS REGISTER (FLAGS)

The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these
bits, FLAGS.7FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and
FLAGS.2 are used for BCD arithmetic.

The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.

Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, Set 1, R/W

MSB

LSB

Bank address
status flag (BA)

First interrupt
status flag (FIS)

Half-carry flag (H)

Decimal adjust flag (D)

Overflow (V)

Sign flag (S)

Zero flag (Z)

Carry flag (C)

Figure 6-1. System Flags Register (FLAGS)

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-7

FLAG DESCRIPTIONS

Carry Flag (FLAGS.7)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to
the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the
specified register. Program instructions can set, clear, or complement the carry flag.

Zero Flag (FLAGS.6)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For
operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is
logic zero.

Sign Flag (FLAGS.5)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the
result. A logic zero indicates a positive number and a logic one indicates a negative number.

Overflow Flag (FLAGS.4)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than
128. It is also cleared to "0" following logic operations.

Decimal Adjust Flag (FLAGS.3)

The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by
programmers, and cannot be used as a test condition.

Half-Carry Flag (FLAGS.2)

The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows
out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous
addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a
program.

FIS

Fast Interrupt Status Flag (FLAGS.1)

The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET
instruction is executed.

Bank Address Flag (FLAGS.0)

The BA flag indicates which register bank in the set 1 area of the internal register file is currently
selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0
instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-9

Table 6-4. Instruction Notation Conventions

Notation

Description

Actual Operand Range

Condition code

See list of condition codes in Table 6-6.

Working register only

Rn (n = 015)

Bit (b) of working register

Rn.b (n = 015, b = 07)

Bit 0 (LSB) of working register

Rn (n = 015)

Working register pair

RRp (p = 0, 2, 4, ..., 14)

reg or Rn (reg = 0255, n = 015)

Bit 'b' of register or working register

reg.b (reg = 0255, b = 07)

reg or RRp (reg = 0254, even number only, where
p = 0, 2, ..., 14)

Indirect addressing mode

addr (addr = 0254, even number only)

Indirect working register only

@Rn (n = 015)

Indirect register or indirect working register @Rn or @reg (reg = 0255, n = 015)

Irr

Indirect working register pair only

@RRp (p = 0, 2, ..., 14)

IRR

Indirect register pair or indirect working
register pair

@RRp or @reg (reg = 0254, even only, where
p = 0, 2, ..., 14)

Indexed addressing mode

#reg [Rn] (reg = 0255, n = 015)

Indexed (short offset) addressing mode

#addr [RRp] (addr = range 128 to +127, where
p = 0, 2, ..., 14)

Indexed (long offset) addressing mode

#addr [RRp] (addr = range 065535, where
p = 0, 2, ..., 14)

Direct addressing mode

addr (addr = range 065535)

Relative addressing mode

addr (addr = number in the range +127 to 128 that is
an offset relative to the address of the next instruction)

Immediate addressing mode

#data (data = 0255)

iml

Immediate (long) addressing mode

#data (data = range 065535)

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-10

Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

DEC

IR1

ADD
r1,r2

ADD

r1,Ir2

ADD

R2,R1

ADD

IR2,R1

ADD

R1,IM

BOR

r0Rb

RLC

IR1

ADC
r1,r2

ADC

r1,Ir2

ADC

R2,R1

ADC

IR2,R1

ADC

R1,IM

BCP

r1.b, R2

INC

IR1

SUB
r1,r2

SUB

r1,Ir2

SUB

R2,R1

SUB

IR2,R1

SUB

R1,IM

BXOR

r0Rb

IRR1

SRP/0/1

SBC
r1,r2

SBC

r1,Ir2

SBC

R2,R1

SBC

IR2,R1

SBC

R1,IM

BTJR

r2.b, RA

IR1

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

LDB

r0Rb

POP

IR1

AND
r1,r2

AND

r1,Ir2

AND

R2,R1

AND

IR2,R1

AND

R1,IM

BITC

r1.b

COM

IR1

TCM

r1,r2

TCM

r1,Ir2

TCM

R2,R1

TCM

IR2,R1

TCM

R1,IM

BAND
r0Rb

PUSH

IR2

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

BIT

r1.b

DECW

RR1

DECW

IR1

PUSHUD

IR1,R2

PUSHUI

IR1,R2

MULT

R2,RR1

MULT

IR2,RR1

MULT

IM,RR1

r1, x, r2

RL
R1

IR1

POPUD

IR2,R1

POPUI
IR2,R1

DIV

R2,RR1

DIV

IR2,RR1

DIV

IM,RR1

r2, x, r1

INCW

RR1

INCW

IR1

r1,r2

r1,Ir2

R2,R1

IR2,R1

R1,IM

LDC

r1, Irr2, xL

CLR

IR1

XOR

r1,r2

XOR

r1,Ir2

XOR

R2,R1

XOR

IR2,R1

XOR

R1,IM

LDC

r2, Irr2, xL

RRC

IR1

CPIJE

Ir,r2,RA

LDC

r1,Irr2

LDW

RR2,RR1

LDW

IR2,RR1

LDW

RR1,IML

r1, Ir2

SRA

IR1

CPIJNE

Irr,r2,RA

LDC

r2,Irr1

CALL

IA1

IR1,IM

Ir1, r2

IR1

LDCD
r1,Irr2

LDCI

r1,Irr2

R2,R1

R2,IR1

R1,IM

LDC

r1, Irr2, xs

SWAP

IR1

LDCPD

r2,Irr1

LDCPI

r2,Irr1

CALL

IRR1

IR2,R1

CALL

DA1

LDC

r2, Irr1, xs

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-12

CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"
after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.

Table 6-6. Condition Codes

Binary

Mnemonic

Description

Flags Set

0000

Always false

1000

Always true

0111

(note)

Carry

C = 1

1111

(note)

No carry

C = 0

0110

(note)

Zero

Z = 1

1110

(note)

Not zero

Z = 0

1101

Plus

S = 0

0101

Minus

S = 1

0100

Overflow

V = 1

1100

NOV

No overflow

V = 0

0110

(note)

Equal

Z = 1

1110

(note)

Not equal

Z = 0

1001

Greater than or equal

(S XOR V) = 0

0001

Less than

(S XOR V) = 1

1010

Greater than

(Z OR (S XOR V)) = 0

0010

Less than or equal

(Z OR (S XOR V)) = 1

1111

(note)

UGE

Unsigned greater than or equal

C = 0

0111

(note)

ULT

Unsigned less than

C = 1

1011

UGT

Unsigned greater than

(C = 0 AND Z = 0) = 1

0011

ULE

Unsigned less than or equal

(C OR Z) = 1

NOTES:
1.

It indicates condition codes that are related to two different mnemonics but which test the same flag. For
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.

For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-14

ADC

-- Add with carry

ADC

dst,src

Operation:

dst

dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. Two's-
complement addition is performed. In multiple precision arithmetic, this instruction permits the
carry from the addition of low-order operands to be carried into the addition of high-order
operands.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result

is of the opposite sign; cleared otherwise.

D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;

cleared otherwise.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:

ADC

R1,R2

R1 = 14H, R2 = 03H

ADC

R1,@R2

R1 = 1BH, R2 = 03H

ADC

01H,02H

ADC

01H,@02H

ADC

01H,#11H

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",
and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds
03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-15

ADD

Add

ADD

dst,src

Operation:

dst

dst + src

The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.

Flags:

C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the

result is of the opposite sign; cleared otherwise.

D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

ADD

R1,R2

R1 = 15H, R2 = 03H

ADD

R1,@R2

R1 = 1CH, R2 = 03H

ADD

01H,02H

ADD

01H,@02H

ADD

01H,#25H

In the first example, destination working register R1 contains 12H and the source working
register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H
in register R1.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-16

AND

Logical AND

AND

dst,src

Operation:

dst

dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND

R1,R2

R1 = 02H, R2 = 03H

AND

R1,@R2

R1 = 02H, R2 = 03H

AND

01H,02H

AND

01H,@02H

AND

01H,#25H

In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-17

BAND

Bit AND

BAND

dst,src.b

BAND

dst.b,src

Operation:

dst(0)

dst(0) AND src(b)

dst(b)

dst(b) AND src(0)

The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of
the destination (or source). The resultant bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | b | 0

src

opc

src | b | 1

dst

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four

bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H and register 01H = 05H:

BAND R1,01H.1

R1 = 06H, register 01H = 05H

BAND 01H.1,R1

In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the
value 06H (00000110B) in register R1.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-18

BCP

Bit Compare

BCP

dst,src.b

Operation:

dst(0) src(b)

The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both
operands are unaffected by the comparison.

Flags:

C: Unaffected.
Z: Set if the two bits are the same; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | b | 0

src

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H and register 01H = 01H:

BCP

R1,01H.1

R1 = 07H, register 01H = 01H

If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-19

BITC

Bit Complement

BITC

dst.b

Operation:

dst(b)

NOT dst(b)

This instruction complements the specified bit within the destination without affecting any other
bits in the destination.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst | b | 0

NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'

is three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H

BITC

R1.1

R1 = 05H

If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H)
is cleared.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-22

BOR

Bit OR

BOR

dst,src.b

BOR

dst.b,src

Operation:

dst(0)

dst(0) OR src(b)

dst(b)

dst(b) OR src(0)

The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the
destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | b | 0

src

opc

src | b | 1

dst

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four

bits, the bit address 'b' is three bits, and the LSB address value is one bit.

Examples:

Given: R1 = 07H and register 01H = 03H:

BOR

R1, 01H.1

R1 = 07H, register 01H = 03H

BOR

01H.2, R1

In the first example, destination working register R1 contains the value 07H (00000111B) and
source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs
bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value
(07H) in working register R1.

In the second example, destination register 01H contains the value 03H (00000011B) and the
source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H
in register 01H.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-23

BTJRF

Bit Test, Jump Relative on False

BTJRF

dst,src.b

Operation:

If src(b) is a "0", then PC

PC + dst

The specified bit within the source operand is tested. If it is a "0", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRF instruction is executed.

Flags:

No flags are affected.

Format:

(Note 1)

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src | b | 0

dst

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRF SKIP,R1.3

PC jumps to SKIP location

If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"
tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the
memory location pointed to by the SKIP. (Remember that the memory location must be within
the allowed range of + 127 to 128.)

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-24

BTJRT

Bit Test, Jump Relative on True

BTJRT

dst,src.b

Operation:

If src(b) is a "1", then PC

PC + dst

The specified bit within the source operand is tested. If it is a "1", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRT instruction is executed.

Flags:

No flags are affected.

Format:

(Note 1)

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src | b | 1

dst

NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is

three bits, and the LSB address value is one bit in length.

Example:

Given: R1 = 07H:

BTJRT

SKIP,R1.1

If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"
tests bit one in the source register (R1). Because it is a "1", the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the
memory location must be within the allowed range of + 127 to 128.)

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-25

BXOR

Bit XOR

BXOR

dst,src.b

BXOR

dst.b,src

Operation:

dst(0)

dst(0) XOR src(b)

dst(b)

dst(b) XOR src(0)

The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)
of the destination (or source). The result bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | b | 0

src

opc

src | b | 1

dst

NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four

bits, the bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):

BXOR R1,01H.1

R1 = 06H, register 01H = 03H

BXOR 01H.2,R1

In the first example, destination working register R1 has the value 07H (00000111B) and source
register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs
bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in
bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is
unaffected.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-26

CALL

Call Procedure

CALL

dst

Operation:

SP 1

@SP

PCL

SP 1

@SP

PCH

dst

The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used
to return to the original program flow. RET pops the top of the stack back into the program
counter.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

opc

dst

IRR

opc

dst

Examples:

Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:

CALL

3521H

SP = 0000H

(Memory locations 0000H = 1AH, 0001H = 4AH, where

4AH is the address that follows the instruction.)

CALL

@RR0

SP = 0000H (0000H = 1AH, 0001H = 49H)

CALL

#40H

SP = 0000H (0000H = 1AH, 0001H = 49H)

In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the
stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the
value 3521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack
location 0001H (because the two-byte instruction format was used). The PC is then loaded with
the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first
example, if program address 0040H contains 35H and program address 0041H contains 21H, the
statement "CALL #40H" produces the same result as in the second example.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-29

COM

Complement

COM

dst

Operation:

dst

NOT dst

The contents of the destination location are complemented (one's complement); all "1s" are
changed to "0s", and vice-versa.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R1 = 07H and register 07H = 0F1H:

COM

R1 = 0F8H

COM

@R1

R1 = 07H, register 07H = 0EH

In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-30

Compare

dst,src

Operation:

dst src

The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.

Flags:

C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst |

src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 02H and R2 = 03H:

R1,R2

Set the C and S flags

Destination working register R1 contains the value 02H and source register R2 contains the
value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1
value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S
are "1".

Given: R1 = 05H and R2 = 0AH:

R1,R2

UGE,SKIP

INC

SKIP

R3,R1

In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-31

CPIJE

Compare, Increment, and Jump on Equal

CPIJE

dst,src,RA

Operation:

If dst src = "0", PC

PC + RA

Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is "0",
the relative address is added to the program counter and control passes to the statement whose
address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before
the next instruction is executed.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 02H:

CPIJE R1,@R2,SKIP

R2 = 04H, PC jumps to SKIP location

In this example, working register R1 contains the value 02H, working register R2 the value 03H,
and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that
the memory location must be within the allowed range of + 127 to 128.)

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-32

CPIJNE

Compare, Increment, and Jump on Non-Equal

CPIJNE

dst,src,RA

Operation:

If dst src "0", PC

PC + RA

Ir + 1

The source operand is compared to (subtracted from) the destination operand. If the result is not
"0", the relative address is added to the program counter and control passes to the statement
whose address is now in the program counter; otherwise the instruction following the CPIJNE
instruction is executed. In either case the source pointer is incremented by one before the next
instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.

Example:

Given: R1 = 02H, R2 = 03H, and register 03H = 04H:

CPIJNE

R1,@R2,SKIP

R2 = 04H, PC jumps to SKIP location

Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal,
the relative address is added to the PC and the PC then jumps to the memory location pointed to
by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to 128.)

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-33

Decimal Adjust

dst

Operation:

dst

DA dst

The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table
indicates the operation performed. (The operation is undefined if the destination operand was not
the result of a valid addition or subtraction of BCD digits):

Instruction

Carry

Before DA

Bits 47

Value (Hex)

H Flag

Before DA

Bits 03

Value (Hex)

Number Added

to Byte

Carry

After DA

ADD

ADC

00 = 00

SUB

FA = 06

SBC

A0 = 60

9A = 66

Flags:

C: Set if there was a carry from the most significant bit; cleared otherwise (see table).
Z: Set if result is "0"; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-36

DECW

Decrement Word

DECW

dst

Operation:

dst

dst 1

The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:

DECW RR0

R0 = 12H, R1 = 33H

DECW @R2

In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word
and decrements the value of R1 by one, leaving the value 33H.

NOTE:

A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW
instruction. To avoid this problem, we recommend that you use DECW as shown in the following
example:

LOOP: DECW RR0

R2,R1

R2,R0

NZ,LOOP

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-38

DIV

Divide (Unsigned)

DIV

dst,src

Operation:

dst ÷ src

dst (UPPER)

REMAINDER

dst (LOWER)

QUOTIENT

The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)
is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of
the destination. When the quotient is

, the numbers stored in the upper and lower halves of

the destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.

Flags:

C: Set if the V flag is set and quotient is between 2

and 2

1; cleared otherwise.

Z: Set if divisor or quotient = "0"; cleared otherwise.
S: Set if MSB of quotient = "1"; cleared otherwise.
V: Set if quotient is

or if divisor = "0"; cleared otherwise.

D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

26/10

NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.

Examples:

Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:

DIV

RR0,R2

R0 = 03H, R1 = 40H

DIV

RR0,@R2

R0 = 03H, R1 = 20H

DIV

RR0,#20H

R0 = 03H, R1 = 80H

In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains
the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the
destination register RR0 (R0) and the quotient in the lower half (R1).

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-39

DJNZ

Decrement and Jump if Non-Zero

DJNZ

r,dst

Operation:

r 1

If r

0, PC

PC + dst

The working register being used as a counter is decremented. If the contents of the register are
not logic zero after decrementing, the relative address is added to the program counter and
control passes to the statement whose address is now in the PC. The range of the relative
address is +127 to 128, and the original value of the PC is taken to be the address of the
instruction byte following the DJNZ statement.

NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at

the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

r | opc

dst

8 (jump taken)

8 (no jump)

r = 0 to F

Example:

Given: R1 = 02H and LOOP is the label of a relative address:

SRP

#0C0H

DJNZ

R1,LOOP

DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the
destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.

The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative
address specified by the LOOP label.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-41

ENTER

Enter

ENTER

Operation:

SP 2

@SP

@IP

IP + 2

This instruction is useful when implementing threaded-code languages. The contents of the
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the
instruction pointer. The program memory word that is pointed to by the instruction pointer is
loaded into the PC, and the instruction pointer is incremented by two.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

opc

Example:

The diagram below shows one example of how to use an ENTER statement.

0050

0022

Data

Address

Data

0040

40
41
42
43

Enter
Address H
Address L
Address H

Address

Data

1F
01
10

Memory

0043

0020

20
21
22

IPH
IPL
Data

Address

Data

0110

40
41
42
43

Enter
Address H
Address L
Address H

Address

Data

1F
01
10

Memory

00
50

Stack

110

Routine

Before

After

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-44

INC

Increment

INC

dst

Operation:

dst

dst + 1

The contents of the destination operand are incremented by one.

Flags:

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

dst | opc

r = 0 to F

opc

dst

Examples:

Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

INC

R0 = 1CH

INC

00H

INC

@R0

R0 = 1BH, register 01H = 10H

In the first example, if destination working register R0 contains the value 1BH, the statement
"INC R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the
value of register 1BH from 0FH to 10H.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-45

INCW

Increment Word

INCW

dst

Operation:

dst

dst + 1

The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value that is incremented by one.

Flags:

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:

INCW RR0

R0 = 1AH, R1 = 03H

INCW @R1

In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H
in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the
value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.

NOTE:

A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the
following example:

LOOP:

INCW

RR0

R2,R1

R2,R0

NZ,LOOP

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-46

IRET

Interrupt Return

IRET

IRET (Normal)

IRET (Fast)

Operation:

FLAGS

@SP

SP + 1

FLAGS

FLAGS'

@SP

FIS

SP + 2

SYM(0)

This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the
fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast
interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.

Flags:

All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

IRET

(Normal)

Bytes

Cycles

Opcode (Hex)

opc

10 (internal stack)

12 (internal stack)

IRET

(Fast)

Bytes

Cycles

Opcode (Hex)

opc

Example:

In the figure below, the instruction pointer is initially loaded with 100H in the main program
before interrupts are enabled. When an interrupt occurs, the program counter and instruction
pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return
address. The last instruction in the service routine normally is a jump to IRET at address FFH.
This causes the instruction pointer to be loaded with 100H "again" and the program counter to
jump back to the main program. Now, the next interrupt can occur and the IP is still correct at
100H.

IRET

Interrupt
Service
Routine

JP to FFH

FFH

100H

FFFFH

NOTE:

In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay
attention to the order of the last two instructions. The IRET cannot be immediately proceeded by
a clearing of the interrupt status (as with a reset of the IPR register).

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-47

Jump

cc,dst

(Conditional)

dst

(Unconditional)

Operation:

If cc is true, PC

dst

The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the
PC.

Flags:

No flags are affected.

Format:

(1)

(2)

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

cc | opc

dst

ccD

cc = 0 to F

opc

dst

IRR

NOTES:
1.

The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

In the first byte of the three-byte instruction format (conditional jump), the condition code and the
opcode are both four bits.

Examples:

Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

C,LABEL_W

LABEL_W = 1000H, PC = 1000H

@00H

PC = 0120H

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the
statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents
of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-48

Jump Relative

cc,dst

Operation:

If cc is true, PC

PC + dst

If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed. (See list of condition
codes).

The range of the relative address is +127, 128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.

Flags:

No flags are affected.

Format:

(1)

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

cc | opc

dst

ccB

cc = 0 to F

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each

four bits.

Example:

Given: The carry flag = "1" and LABEL_X = 1FF7H:

C,LABEL_X

PC = 1FF7H

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program
instruction following the JR would be executed.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-51

LDB

Load Bit

LDB

dst,src.b

LDB

dst.b,src

Operation:

dst(0)

src(b)

dst(b)

src(0)

The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the
source is loaded into the specified bit of the destination. No other bits of the destination are
affected. The source is unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | b | 0

src

opc

src | b | 1

dst

NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the

bit address 'b' is three bits, and the LSB address value is one bit in length.

Examples:

Given: R0 = 06H and general register 00H = 05H:

LDB

R0,00H.2

R0 = 07H, register 00H = 05H

LDB

00H.0,R0

R0 = 06H, register 00H = 04H

In the first example, destination working register R0 contains the value 06H and the source
general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.

In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in
general register 00H.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-52

LDC/LDE

Load Memory

LDC/LDE

dst,src

Operation:

dst

src

This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory.
The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd
number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

Irr

opc

src | dst

Irr

opc

dst | src

XS [rr]

opc

src | dst

XS [rr]

opc

dst | src

XL [rr]

opc

src | dst

XL [rr]

opc

dst | 0000

opc

src | 0000

opc

dst | 0001

10.

opc

src | 0001

NOTES:
1.

The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 01.

For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one
byte.

For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two
bytes.

The DA and r source values for formats 7 and 8 are used to address program memory; the second set
of values, used in formats 9 and 10, are used to address data memory.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-53

LDC/LDE

Load Memory

LDC/LDE

(Continued)

Examples:

Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

LDC

R0,@RR2

; R0

contents of program memory location 0104H

; R0 = 1AH, R2 = 01H, R3 = 04H

LDE

R0,@RR2

; R0

contents of external data memory location 0104H

; R0 = 2AH, R2 = 01H, R3 = 04H

LDC

(note)

@RR2,R0

; 11H (contents of R0) is loaded into program memory
; location 0104H (RR2),
; working registers R0, R2, R3

no change

LDE

@RR2,R0

; 11H (contents of R0) is loaded into external data memory
; location 0104H (RR2),
; working registers R0, R2, R3

no change

LDC

R0,#01H[RR2]

; R0

contents of program memory location 0105H

; (01H + RR2),
; R0 = 6DH, R2 = 01H, R3 = 04H

LDE

R0,#01H[RR2]

; R0

contents of external data memory location 0105H

; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H

LDC

(note)

#01H[RR2],R0

; 11H (contents of R0) is loaded into program memory location
; 0105H (01H + 0104H)

LDE

#01H[RR2],R0

; 11H (contents of R0) is loaded into external data memory
; location 0105H (01H + 0104H)

LDC

R0,#1000H[RR2] ; R0

contents of program memory location 1104H

; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H

LDE

R0,#1000H[RR2] ; R0

contents of external data memory location 1104H

; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H

LDC

R0,1104H

; R0

contents of program memory location 1104H, R0 = 88H

LDE

R0,1104H

; R0

contents of external data memory location 1104H,

; R0 = 98H

LDC

(note)

1105H,R0

; 11H (contents of R0) is loaded into program memory location
; 1105H, (1105H)

11H

LDE

1105H,R0

; 11H (contents of R0) is loaded into external data memory
; location 1105H, (1105H)

11H

NOTE: These instructions are not supported by masked ROM type devices.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-54

LDCD/LDED

Load Memory and Decrement

LDCD/LDED

dst,src

Operation:

dst

src

rr 1

These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:

LDCD

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is decremented by one

; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6

RR6 1)

LDED

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is decremented by one (RR6

RR6 1)

; R8 = 0DDH, R6 = 10H, R7 = 32H

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-55

LDCI/LDEI

Load Memory and Increment

LDCI/LDEI

dst,src

Operation:

dst

src

rr + 1

These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler
makes 'Irr' even for program memory and odd for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

Irr

Examples:

Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

LDCI

R8,@RR6

; 0CDH (contents of program memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6

RR6 + 1)

; R8 = 0CDH, R6 = 10H, R7 = 34H

LDEI

R8,@RR6

; 0DDH (contents of data memory location 1033H) is loaded

; into R8 and RR6 is incremented by one (RR6

RR6 + 1)

; R8 = 0DDH, R6 = 10H, R7 = 34H

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-56

LDCPD/LDEPD

Load Memory with Pre-Decrement

LDCPD/
LDEPD

dst,src

Operation:

rr 1

dst

src

These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is
first decremented. The contents of the source location are then loaded into the destination
location. The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for external data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src | dst

Irr

Examples:

Given: R0 = 77H, R6 = 30H, and R7 = 00H:

LDCPD

@RR6,R0

; (RR6

RR6 1)

; 77H (contents of R0) is loaded into program memory location
; 2FFFH (3000H 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH

LDEPD

@RR6,R0

; (RR6

RR6 1)

; 77H (contents of R0) is loaded into external data memory
; location 2FFFH (3000H 1H)
; R0 = 77H, R6 = 2FH, R7 = 0FFH

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-57

LDCPI/LDEPI

Load Memory with Pre-Increment

LDCPI/
LDEPI

dst,src

Operation:

rr + 1

dst

src

These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is
first incremented. The contents of the source location are loaded into the destination location.
The contents of the source are unaffected.

LDCPI refers to program memory and LDEPI refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src | dst

Irr

Examples:

Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:

LDCPI

@RR6,R0

; (RR6

RR6 + 1)

; 7FH (contents of R0) is loaded into program memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H

LDEPI

@RR6,R0

; (RR6

RR6 + 1)

; 7FH (contents of R0) is loaded into external data memory
; location 2200H (21FFH + 1H)
; R0 = 7FH, R6 = 22H, R7 = 00H

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-58

LDW

Load Word

LDW

dst,src

Operation:

dst

src

The contents of the source (a word) are loaded into the destination. The contents of the source
are unaffected.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

opc

dst

src

IML

Examples:

Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,
register 01H = 02H, register 02H = 03H, and register 03H = 0FH:

LDW

RR6,RR4

R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH

LDW

00H,02H

LDW

RR2,@R7

R2 = 03H, R3 = 0FH,

LDW

04H,@01H

LDW

RR6,#1234H

R6 = 12H, R7 = 34H

LDW

02H,#0FEDH

In the second example, please note that the statement "LDW 00H,02H" loads the contents of
the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in
general register 00H and the value 0FH in register 01H.

The other examples show how to use the LDW instruction with various addressing modes and
formats.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-59

MULT

Multiply (Unsigned)

MULT

dst,src

Operation:

dst

src

The 8-bit destination operand (even register of the register pair) is multiplied by the source
operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination
address. Both operands are treated as unsigned integers.

Flags:

C: Set if result is

255; cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.
S: Set if MSB of the result is a "1"; cleared otherwise.
V: Cleared.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

Examples:

Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:

MULT

00H, 02H

MULT

00H, @01H

MULT

00H, #30H

In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in
the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-62

Logical OR

dst,src

Operation:

dst

dst OR src

The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and
register 08H = 8AH:

R0,R1

R0 = 3FH, R1 = 2AH

R0,@R2

R0 = 37H, R2 = 01H, register 01H = 37H

00H,01H

01H,@00H

00H,#02H

In the first example, if working register R0 contains the value 15H and register R1 the value
2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the
result (3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing
modes and formats.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-64

POPUD

Pop User Stack (Decrementing)

POPUD

dst,src

Operation:

dst

src

IR 1

This instruction is used for user-defined stacks in the register file. The contents of the register file
location addressed by the user stack pointer are loaded into the destination. The user stack
pointer is then decremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

Example:

Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and
register 02H = 70H:

POPUD

02H,@00H

If general register 00H contains the value 42H and register 42H the value 6FH, the statement
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The
user stack pointer is then decremented by one, leaving the value 41H.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-65

POPUI

Pop User Stack (Incrementing)

POPUI

dst,src

Operation:

dst

src

IR + 1

The POPUI instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user stack pointer are loaded into the destination. The user
stack pointer is then incremented.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

src

dst

Example:

Given: Register 00H = 01H and register 01H = 70H:

POPUI

02H,@00H

If general register 00H contains the value 01H and register 01H the value 70H, the statement
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user
stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-66

PUSH

Push To Stack

PUSH

src

Operation:

SP 1

@SP

src

A PUSH instruction decrements the stack pointer value and loads the contents of the source
(src) into the location addressed by the decremented stack pointer. The operation then adds the
new value to the top of the stack.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

src

8 (internal clock)

8 (external clock)

8 (internal clock)

8 (external clock)

Examples:

Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:

PUSH

40H

PUSH

@40H

In the first example, if the stack pointer contains the value 0000H, and general register 40H the
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It
then loads the contents of register 40H into location 0FFFFH and adds this new value to the top
of the stack.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-67

PUSHUD

Push User Stack (Decrementing)

PUSHUD

dst,src

Operation:

IR 1

dst

src

This instruction is used to address user-defined stacks in the register file. PUSHUD decrements
the user stack pointer and loads the contents of the source into the register addressed by the
decremented stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst

src

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:

PUSHUD @00H,01H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user
stack pointer.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-68

PUSHUI

Push User Stack (Incrementing)

PUSHUI

dst,src

Operation:

IR + 1

dst

src

This instruction is used for user-defined stacks in the register file. PUSHUI increments the user
stack pointer and then loads the contents of the source into the register location addressed by
the incremented user stack pointer.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst

src

Example:

Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:

PUSHUI

@00H,01H

If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H
register value, 05H, is then loaded into the location addressed by the incremented user stack
pointer.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-70

RET

Return

RET

Operation:

@SP

SP + 2

The RET instruction is normally used to return to the previously executing procedure at the end
of a procedure entered by a CALL instruction. The contents of the location addressed by the
stack pointer are popped into the program counter. The next statement that is executed is the
one that is addressed by the new program counter value.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode (Hex)

opc

8 (internal stack)

10 (internal stack)

Example:

Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:

RET

PC = 101AH, SP = 00FEH

The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte
of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 00FEH.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-71

Rotate Left

dst

Operation:

dst (7)

dst (0)

dst (7)

dst (n + 1)

dst (n), n = 06

The contents of the destination operand are rotated left one bit position. The initial value of bit 7
is moved to the bit zero (LSB) position and also replaces the carry flag.

Flags:

C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

00H

@01H

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-72

RLC

Rotate Left Through Carry

RLC

dst

Operation:

dst (0)

dst (7)

dst (n + 1)

dst (n), n = 06

The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

Flags:

rotation; cleared otherwise.

D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

RLC

00H

RLC

@01H

In the first example, if general register 00H has the value 0AAH (10101010B), the statement
"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag
and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-73

Rotate Right

dst

Operation:

dst (0)

dst (7)

dst (0)

dst (n

)

dst (n + 1), n = 06

The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:

00H

@01H

In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-74

RRC

Rotate Right Through Carry

RRC

dst

Operation:

dst (7)

dst (0)

dst (n)

dst (n + 1), n = 06

The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit
7 (MSB).

Flags:

C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during

rotation; cleared otherwise.

D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

RRC

00H

RRC

@01H

In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")
replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new
value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both
cleared to "0".

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-77

SBC

Subtract With Carry

SBC

dst,src

Operation:

dst

dst src c

The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.

Flags:

C: Set if a borrow occurred (src

dst); cleared otherwise.

Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign

of the result is the same as the sign of the source; cleared otherwise.

D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise, indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:

SBC

R1,R2

R1 = 0CH, R2 = 03H

SBC

R1,@R2

R1 = 05H, R2 = 03H, register 03H = 0AH

SBC

01H,02H

SBC

01H,@02H

SBC

01H,#8AH

In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-79

SRA

Shift Right Arithmetic

SRA

dst

Operation:

dst (7)

dst (0)

dst (n)

dst (n + 1), n = 06

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.

Flags:

C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst

opc

dst

Examples:

Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

SRA

00H

SRA

@02H

In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C
flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves
the value 0CDH (11001101B) in destination register 00H.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-80

SRP/SRP0/SRP1

Set Register Pointer

SRP

src

SRP0

src

SRP1

src

Operation:

If src (1) = 1 and src (0) = 0 then: RP0 (37)

src (37)

If src (1) = 0 and src (0) = 1 then: RP1 (37)

src (37)

If src (1) = 0 and src (0) = 0 then: RP0 (47)

src (47),

RP0 (3)

RP1 (47)

src (47),

RP1 (3)

The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 37 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.

Flags:

No flags are affected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

src

opc

src

Examples:

The statement

SRP #40H

sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.

The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to
68H.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-82

SUB

Subtract

SUB

dst,src

Operation:

dst

dst src

The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.

Flags:

C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the

sign of the result is of the same as the sign of the source operand; cleared otherwise.

D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;

set otherwise indicating a "borrow".

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst |

src

opc

src

dst

opc

dst

src

Examples:

Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

SUB

R1,R2

R1 = 0FH, R2 = 03H

SUB

R1,@R2

R1 = 08H, R2 = 03H

SUB

01H,02H

SUB

01H,@02H

SUB

01H,#90H

SUB

01H,#65H

In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.

INSTRUCTION SET

S3P80C5/C80C5/C80C8

6-84

TCM

Test Complement Under Mask

TCM

dst,src

Operation:

(NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:

TCM

R0,R1

R0 = 0C7H, R1 = 02H, Z = "1"

TCM

R0,@R1

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

TCM

00H,01H

TCM

00H,@01H

TCM

00H,#34

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-85

Test Under Mask

dst,src

Operation:

dst AND src

This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:

R0,R1

R0 = 0C7H, R1 = 02H, Z = "0"

R0,@R1

R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"

00H,01H

00H,@01H

00H,#54H

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.

S3P80C5/C80C5/C80C8

INSTRUCTION SET

6-87

XOR

Logical Exclusive OR

XOR

dst,src

Operation:

dst

dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever
the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Flags:

C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.

Format:

Bytes

Cycles

Opcode

(Hex)

Addr Mode

dst src

opc

dst | src

opc

src

dst

opc

dst

src

Examples:

Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:

XOR

R0,R1

R0 = 0C5H, R1 = 02H

XOR

R0,@R1

R0 = 0E4H, R1 = 02H, register 02H = 23H

XOR

00H,01H

XOR

00H,@01H

XOR

00H,#54H

In the first example, if working register R0 contains the value 0C7H and if register R1 contains
the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0
value and stores the result (0C5H) in the destination register R0.

S3P80C5/C80C5/C80C8

CLOCK CIRCUITS

7-1

CLOCK CIRCUITS

OVERVIEW

The clock frequency generated for the S3P80C5/C80C5/C80C8 by an external crystal, or supplied by an external
clock source, can range from 1MHz to 4 MHz. The maximum CPU clock frequency, as determined by CLKCON
register settings, is 4 MHz. The X

and X

OUT

pins connect the external oscillator or clock source to the on-chip

clock circuit.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

-- External crystal or ceramic resonator oscillation source (or an external clock)

-- Oscillator stop and wake-up functions

-- Programmable frequency divider for the CPU clock (f

OSC

divided by 1, 2, 8, or 16)

-- Clock circuit control register, CLKCON

OUT

Figure 7-1. Main Oscillator Circuit

(External Crystal or Ceramic Resonator)

OUT

External

Clock

Open Pin

Figure 7-2. External Clock Circuit

CLOCK CIRCUITS

S3P80C5/C80C5/C80C8

7-2

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

-- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by Power On

Reset operation or by a non-vectored interrupt - interrupt with reset (INTR). To enter the Stop mode,
STOPCON (STOP Control register) has to be loaded with value, #0A5H before STOP instruction execution.
After recovering from the Stop mode by reset or interrupt, STOPCON register is automatically cleared.

-- In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the

interrupt structure, timer 0, and counter A. Idle mode is released by a reset or by an interrupt (external or
internally generated).

Main
OSC

STOP

Instruction

Noise

filter

Oscillator

Stop

Oscillator

Wake-up

INT Pin

(1)

1/16

1/2

1/8

U
X

CLKCON.3,.4

STOPCON

CPU
Clock

NOTES:
1. An external interrupt with an RC-delay noise filter (for S3C80C5/C80C8/,
INT0-4) is fiexed to release Stop mode and "wake up" the main
oscillator.
2. Because the S3C80C5/C80C8 has no subsystem clock, the 3-bit CLKCON
signature code (CLKCON.2-CLKCON.0) is no meaning.

Figure 7-3. System Clock Circuit Diagram

S3P80C5/C80C5/C80C8

CLOCK CIRCUITS

7-3

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in set 1, address D4H. It is read/write addressable and
has the following functions:

-- Oscillator frequency divide-by value

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode
release. (This is called the "IRQ wake-up" function.) The IRQ wake-up enable bit is CLKCON.7. In
S3P80C5/C80C5/C80C8, this bit is not valid any more. Actually bit 7, 6, 5, 2, 1, and 0 are no meaning in
S3P80C5/C80C5/C80C8.

After a reset, the main oscillator is activated, and the f

OSC

/16 (the slowest clock speed) is selected as the CPU

clock. If necessary, you can then increase the CPU clock speed to f

OSC

, f

OSC

/2, or f

OSC

/8.

System Clock Control Register (CLKCON)

D4H, Set 1, R/W

MSB

LSB

Divide-by selection bits for
CPU clock frequency:
00 = f

OSC

/16

01 = f

OSC

10 = f

OSC

11 = f

OSC

(non-divided)

Not used

Figure 7-4. System Clock Control Register (CLKCON)

S3P80C5/C80C5/C80C8

RESET

and POWER-DOWN

8-1

RESET

and POWER-DOWN

SYSTEM RESET

S3P80C5/C80C5/C80C8 has four different system reset sources as followings:

-- Low Voltage Detect (LVD)

-- Internal POR circuit

-- INTR (Interrupt with

RESET

)

-- Basic Timer (Watchdog timer)

STOPCON

Noise

Filter

LVD

Stop

INTR

POR

BT(WDT)

Enable/Disable

Figure 8-1. Reset Block Diagram

LVD RESET

The Low Voltage detect circuit is built on the S3P80C5/C80C5/C80C8 product for system reset not in stop mode.
When the operating status is not stop mode it detects a slope of V

by comparing the voltage at V

with V

LVD

(Low level Detect Voltage). The reset pulse is generated by the rising slope of V

. While the voltage at V

rising up and passing V

LVD

, the reset pulse is occurred at the moment "V

LVD

". This function is disabled

when the operating state is "stop mode" to reduce the current consumption under 1 uA instead of 6 uA.

RESET

and POWER-DOWN

S3P80C5/C80C5/C80C8

8-2

INTERRUPT WITH RESET(INTR)

A non vectored interrupt called Interrupt with reset (INTR) is built in
S3C80C5/C80C8 to release stop status with system reset. When a falling/rising edge occurs at Port 0 during stop
mode, INTR signal is generated and it makes the system reset pulse. An INTR signal is generated relating to
interaction between Port 0 and operating status. It is enabled by STOP status and occurs by falling/rising edge at
port0. So only when the chip status is "STOP", it is available. If the operating status is not stop status INTR does
not occurs.

NOTE

This INTR is supplementary function to make system reset for an application which is using " stop mode"
like remote controller. If an application which is not using "stop mode" , INTR function can be discarded.

WATCHDOG TIMER RESET

The S3P80C5/C80C5/C80C8 build a watch-dog timer that can recover to normal operation from abnormal
function. Watchdog timer generates a system reset signal if not clearing a BT-Basic Counter within a specific
time by program. System reset can return to the proper operation of chip.

POWER-ON RESET(POR)

The power-on reset circuit is built on the S3P80C5/C80C5/C80C8 product. During a power-on reset, the voltage
at V

goes to High level and the Schmitt trigger input of POR circuit is forced to Low level and then to High

level. The power-on reset circuit makes a reset signal whenever the power supply voltage is powering-up and the
Schmitt trigger input senses the Low level. This on-chip POR circuit consists of an internal resistor, an internal
capacitor, and a Schmitt trigger input transistor.

System Reset

R : On-Chip Resistor
C : On-Chip Capacitor

Schmitt Trigger Inverter

Figure 8-2. Power-on Reset Circuit

S3P80C5/C80C5/C80C8

RESET

and POWER-DOWN

8-3

Voltage [V]

Time

Reset pulse

Reset Pulse Width

= 0.85 V

= 0.4 V

Rising Time)

If Va voltage is under the 0.4 V

, Reset pulse signal is gernerated.

If Va voltage is over than 0.4 VDD, Reset pulse is not gernerated.

Figure 8-3. Timing Diagram for Power-on Reset Circuit

SYSTEM RESET OPERATION

System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal
CPU and peripheral modules. This procedure brings the S3P80C5/C80C5/C80C8 into a known operating status.
To allow time for internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level
for a minimum time interval after the power supply comes within tolerance. The minimum required reset
operation for a oscillation stabilization time is 16 oscillation clocks. All system and peripheral control registers are
then reset to their default hardware values (see Tables 5-1).

In summary, the following sequence of events occurs during a reset operation:

-- All interrupts are disabled.

-- The watchdog function (basic timer) is enabled.

-- Ports 0, 1 and 2 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.

-- Peripheral control and data register settings are disabled and reset to their default hardware values (see

Table 5-1).

-- The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

-- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM

location 0100H (and 0101H) is fetched and executed.

RESET

and POWER-DOWN

S3P80C5/C80C5/C80C8

8-4

HARDWARE RESET VALUES

Tables 5-1 list the reset values for CPU and system registers, peripheral control registers, and peripheral data
registers following a reset operation. The following notation is used to represent reset values:

-- A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.

-- An 'x' means that the bit value is undefined after a reset.

-- A dash ('-') means that the bit is either not used or not mapped (but a 0 is read from the bit position)

Table 8-1. Set 1 Register Values After Reset

Register Name

Mnemonic

Address

Bit Values After Reset

Dec

Hex

Timer 0 counter (read-only)

T0CNT

208

D0H

Timer 0 data register

T0DATA

209

D1H

Timer 0 control register

T0CON

210

D2H

Basic timer control register

BTCON

211

D3H

Clock control register

CLKCON

212

D4H

System flags register

FLAGS

213

D5H

RP0

214

D6H

RP1

215

D7H

Location D8H (SPH) is not mapped.

Stack pointer (low byte)

SPL

217

D9H

Instruction pointer (high byte)

IPH

218

DAH

Instruction pointer (low byte)

IPL

219

DBH

Interrupt request register (read-only)

IRQ

220

DCH

Interrupt mask register

IMR

221

DDH

System mode register

SYM

222

DEH

223

DFH

Port 0 data register

224

E0H

Port 1 data register

225

E1H

Port 2 data register

226

E2H

Location E3HE6H is not mapped.

Port 0 pull-up enable register

P0PUR

231

E7H

Port 0 control register (high byte)

P0CONH

232

E8H

Port 0 control register (low byte)

P0CONL

233

E9H

S3P80C5/C80C5/C80C8

RESET

and POWER-DOWN

8-5

Table 8-1. Set 1 Register Values After Reset (Continued)

Register Name

Mnemonic

Address

Bit Values After Reset

Dec

Hex

Port 1 control register (high byte)

P1CONH

234

EAH

Port 1 control register (low byte)

P1CONL

235

EBH

Port 1 pull-up enable register

P1PUR

236

ECH

Location EDHEFH is not mapped.

Port 2 control register

P2CON

240

F0H

Port 0 interrupt enable register

P0INT

241

F1H

Port 0 interrupt pending register

P0PND

242

F2H

Counter A control register

CACON

243

F3H

Counter A data register (high byte)

CADATAH

244

F4H

Counter A data register (low byte)

CADATAL

245

F5H

Timer 1 counter register (high byte)

T1CNTH

246

F6H

Timer 1 counter register (low byte)

T1CNTL

247

F7H

Timer 1 data register (high byte)

T1DATAH

248

F8H

Timer 1 data register (low byte)

T1DATAL

249

F9H

Timer 1 control register

T1CON

250

FAH

Stop control register

STOPCON

251

FBH

Locations FCH is not mapped.

Basic timer counter

BTCNT

253

FDH

External memory timing register

EMT

254

FEH

Interrupt priority register

IPR

255

FFH

NOTES:
1. Although the SYM register is not used for the S3P80C5/C80C5/C80C8, SYM.5

should always be "0". If you accidentally write a 1 to this bit during normal operation, a system malfunction may occur.

Except for T0CNT, IRQ, T1CNTH, T1CNTL, and BTCNT, which are read-only, all registers in set 1 are

read/write addressable.
3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.
4. Interrupt pending flags are noted by shaded table cells.

RESET

and POWER-DOWN

S3P80C5/C80C5/C80C8

8-6

POWER-DOWN MODES

STOP MODE

Stop mode is invoked by stop control register (STOPCON) setting and the instruction STOP. In Stop mode, the
operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply
current is reduced to less than 3 uA at 5.5 V. All system functions stop when the clock "freezes,"

Stop mode can be released of two ways : by an INTR (Interrupt with Reset) or by a POR (Power On Reset).

USING POR TO RELEASE STOP MODE

Stop mode is released when the reset signal goes active by power on reset (POR): all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are unknown
states. When the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by
fetching the program instruction stored in ROM location 0100H.

USING AN INTR TO RELEASE STOP MODE

Stop mode is released when INTR (Interrupt with Reset) occurs. INTR occurs when falling/rising edge is detected
at P0 during stop mode and it make system reset.

NOTE

1. Do not use stop mode if you are using an external clock source because X

input must be cleared

internally to V

to reduce current leakage.

2. STOP mode always be released by the system reset (INTR or POR) so the system register value and
control register value are initialized as reset value. And when the reset occurs from INTR, the prime
register value will be retained but it will be unknown states if it occurs from POR. So an application
which is using stop mode should be added specific S/W which divide the system reset into STOP
mode releasing or power on reset. Following Programming Tip can be useful for more
understanding.

S3P80C5/C80C5/C80C8

RESET

and POWER-DOWN

8-7

PROGRAMMING TIP -- To Divide STOP Mode Releasing and POR.

This example shows how to enter the stop mode and how to know it is stop mode releasing or power on

RESET

ORG

0100H

; Reset address

START

;

BTCON,#03h

; enable basic timer counter.

SPL,#0FFH

; Initialize the system register

CLR

SYM

CLR

EMT

CLR

IPR

·
·

P0CONH,#00H

; Initialize the control register

P0CONL,#00H

P0PUR,#0FFH

CHECK_RAM:

; Check the RAM data whether it is stop mode releasing

; or Power On RESET

R0,#0BFH

; If Power On Reset , go to POR_RESET

CHK_R

R0,@R0

;

NE,POR_RESET

DEC

R0,#0B0H

UGE, CHK_R

STOP_RESET:

; STOP mode releasing.

MAIN

;

POR_RESET LD

R0,#0FFH

;Power On Reset

;CHECK RAM data are failed so clear all RAM data.

RAM_CLR

CLR

@R0

DJNJ

R0,RAMCLR

R0,#0BFH

;Initialize the CHECK RAM data as default value .

S3P80C5/C80C5/C80C8

RESET

and POWER-DOWN

8-9

IDLE MODE

Idle mode is invoked by the instruction IDLE (OPCODE 6FH). In Idle mode, CPU operations are halted while
some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU and from
all but the following peripherals, which remain active:

-- Interrupt logic

-- Timer 0

-- Timer 1

-- Counter A

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slowest clock because of the hardware
reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the
only way you can release Idle mode.

2. Activate any enabled interrupt ; internal or external. When you use an interrupt to release Idle mode, the 2-bit

CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The
interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately
following the one which initiated Idle mode is executed.

NOTE

Only external interrupts with an RC delay built in to the pin circuit can be used to release Stop mode
without reset. To release Idle mode, you can use either an external interrupt or an internally-generated
interrupt.

S3P80C5/C80C5/C80C8

I/O PORTS

9-1

I/O PORTS

OVERVIEW

The S3P80C5/C80C5/C80C8 microcontroller has three bit-programmable I/O ports, P0P2. Two ports, P0-P1,
are 8-bit ports and P2 is a 3-bit port. This gives a total of 19 I/O pins in the S3P80C5/C80C5/C80C8"s 24-pin
package. Each port is bit-programmable and can be flexibly configured to meet application design requirements.
The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.

For IR universal remote controller applications, ports 0, and1 are usually configured to the keyboard matrix and
port 2 is used to transmit the remote controller carrier signal or to indicate operating status by turning on a LED.

Table 9-1 gives you a general overview of S3P80C5/C80C5/C80C8 I/O port functions.

Table 9-1. S3P80C5/C80C5/C80C8 Port Configuration Overview

Port

Configuration Options

8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling
edges, rising edges, or both edges; all P0 pin circuits have noise filters and interrupt
enable/disable (P0INT) and pending control (P0PND); Pull-up resistors can be assigned to
individual P0 pins using P0PUR register settings. Specially Interrupt with Reset(INTR) is
assigned to release stop mode with system reset.

8-bit general-purpose I/O port; Input, open-drain output, or push-pull output. Pull-up resistors
can be assigned to individual P1 pins using P1PUR register settings.

3-bit I/O port; input mode with or without pull-up, push-pull or open-drain output mode. REM
and T0PWM can be assigned. Port 2 pins have high current drive capability to support LED
applications. The port 2 data register contains three status bits: three for P2.0, P2.1 and P2.2
and one for remote controller carrier signal on/off status.

I/O PORTS

S3P80C5/C80C5/C80C8

9-2

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all three S3C80C5/C80C8 port data registers. Data
registers for ports 0, and 1 have the general format.

NOTE

The data register for port 2, P2, contains three bits for P2.0, P2.1 and P2.2, and an additional status bit
for carrier signal on/off.

Table 9-2. Port Data Register Summary

Register Name

Mnemonic

Decimal

Hex

R/W

Port 0 data register

224

E0H

R/W

Port 1 data register

225

E1H

R/W

Port 2 data register

226

E2H

R/W

Because port 2 is a 3-bit I/O port, the port 2 data register only contains values for P2.0, P2.1 and P2.2. The P2
register also contains values for P2.0, P2.1 and P2.2. The P2 register also contains a special carrier on/off
bit(P2.5). See the port 2 description for details. All other S3P80C5/C80C5/C80C8 I/O ports are 8-bit.

PULL-UP RESISTOR ENABLE REGISTERS

NOTE:

Pull-up resistors can be assigned to the port 2 pins, P2.0, P2.1 and
P2.2 by marking the appropriate the port 2 control register,P2CON.

Port0 Pull-up Resistor Enable Register (P0PUR)

E7H, R/W

MSB

LSB

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

Pull-up resistor enable bit:
0 = Enable pull-up resistor

1 = Disable pull-up resistor

Figure 9-1. S3P80C5/C80C5/C80C8 I/O Port 0 Data Register Format

I/O PORTS

S3P80C5/C80C5/C80C8

9-4

PORT 0

Port 0 is a general-purpose, 8-bit I/O port. It is bit-programmable. Port 0 pins are accessed directly by read/write
operations to the port 0 data register, P0 (set 1, E0H). The P0 pin circuits support pull-up resistor assignment
using P0PUR register settings and all pins have noise filters for external interrupt inputs.

Two 8-bit control registers are used to configure port 0 pins: P0CONH (set 1, E8H) for the upper nibble pins,
P0.7P0.4, and P0CONL (set 1, E9H) for lower nibble pins, P0.3P0.0. Each control register byte contains four
bit-pairs and each bit-pair configures one pin (see Figures 9-2 and 9-3). A hardware reset clears all P0 control
and data registers to '00H'.

A separate register, the port 0 interrupt control register, P0INT (set 1, F1H), is used to enable and disable
external interrupt input. You can poll the port 0 interrupt pending register, P0PND to detect and clear pending
conditions for these interrupts.

The lower-nibble pins, P0.3P0.0, are used for INT3INT0 input (IRQ6), respectively. The upper nibble pins,
P0.7P0.4, are all used for INT4 input (IRQ7). Interrupts that are detected at any of these four pins are processed
using the same vector address (E8H).

Port 0 , P0.0P0.7, is assigned interrupt with reset(INTR) to release stop mode with system reset.

Port 0 Control Register, High Byte (P0CONH)

E8H, Set 1, R/W

MSB

LSB

P0.7/INT4

P0.4/INT4

P0.6/INT4

P0.5/INT4

P0CONH Pin Configureation Settings:

00
01
10
11

Input mode; interrupt on falling edges
Input mode; interrupt on rising and falling edges
Push-pull output mode
Input mode; interrupt on rising edges

Figure 9-3. Port 0 High-Byte Control Register (P0CONH)

S3P80C5/C80C5/C80C8

I/O PORTS

9-5

Port 0 Control Register, Low Byte (P0CONL)

E9H, Set 1, R/W

MSB

LSB

P0.3/INT3

P0.0/INT0

P0.2/INT2

P0.1/INT1

P0CONL Pin Configureation Settings:

00
01
10
11

Input mode; interrupt on falling edges
Input mode; interrupt on rising and falling edges
Push-pull output mode
Input mode; interrupt on rising edges

Figure 9-4. Port 0 Low-Byte Control Register (P0CONL)

PORT 0 INTERRUPT ENABLE REGISTER (P0INT)

The port 0 interrupt control register, P0INT, is used to enable and disable external interrupt input at individual P0
pins (see Figure 10-5). To enable a specific external interrupt, you set its P0INT.n bit to "1". You must also be
sure to make the correct settings in the corresponding port 0 control register (P0CONH, P0CONL).

PORT 0 INTERRUPT PENDING REGISTER (P0PND)

The port 0 interrupt pending register, P0PND, contains pending bits (flags) for each port 0 interrupt (see Figure
10-6). When a P0 external interrupt is acknowledged by the CPU, the service routine must clear the pending
condition by writing a "0" to the appropriate pending flag in the P0PND register (Writing a "1" to the pending bit
has no effect).

NOTE

A hardware reset(INTR, POR) clears the P0INT and P0PND registers to '00H'. For this reason, the
application program's initialization routine must enable the required external interrupts for port 0, and for
the other I/O ports.

S3P80C5/C80C5/C80C8

I/O PORTS

9-7

PORT 1

Port 1 is a bit-programmable 8-bit I/O port. Port 1 pins are accessed directly by read/write operations to the port 1
data register, P1 (set 1, E1H).

To configure port 1, the initialization routine writes the appropriate values to the two port 1 control registers:
P1CONH (set 1, EAH) for the upper nibble pins, P1.7P1.4, and P1CONL (set 1, EBH) for the lower nibble pins,
P1.3P1.0. Each 8-bit control register contains four bit-pairs and each 2-bit value configures one port pin (see
Figures 9-6 and 9-7).

Following a hardware reset, the port 1 control registers are cleared to '00H', configuring port 0 initially to Input
mode.

To assign pull-up resistors to P1 pins, you make the appropriate settings to the port 1 pull-up resistor enable
register, P1PUR.

Port 1 Control Register, High Byte (P1CONH)

EAH, Set 1, R/W

MSB

LSB

P1.7

P1.4

P1.6

P1.5

P1CONH Pin Configureation Settings:

00
01
10
11

Input mode
Open-drain output mode
Push-pull output mode
Invalid setting

Figure 9-7. Port 1 High-Byte Control Register (P1CONH)

S3P80C5/C80C5/C80C8

I/O PORTS

9-9

PORT 2

Port 2 is a bit-programmable 3-bit I/O port. Port 2 pins are accessed directly by read/write operations to the port 2
data register, P2 (set 1, E2H). You can configure port 2 pins individually to Input mode, open-drain output mode,
or push-pull output mode.

P2.0, P2.1 and P2.2 are configured by writing 6-bit data value to the port 2 control register, P2CON. You can
configure these pins to support input functions (Input mode, with or without pull-up, for T0CK) or output functions
(push-pull or open-drain output mode for REM and timer 0 PWM).

Port 2 pins have high current drive capability to support LED applications.

A reset operation clears P2CON to '00H', selecting Input mode as the initial port 2 function.

Port 2 Control Register (P2CON)

F0H, R/W

MSB

LSB

P2.2

P2.1

P1.0

P2.1 Alternative Function Enable

0
1

Normal I/O Function
REM/T0CK

P2.0 Alternative Function Enable

0
1

Normal I/O Function
T0PWM

P2CON Pin Configuration Setting:

00
01
10
11

C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input mode with pull-up

Figure 9-9. Port 2 Control Register (P2CON)

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

10-1

BASIC TIMER and TIMER 0

MODULE OVERVIEW

The S3P80C5/C80C5/C80C8 has two default timers: an 8-bit basic timer and one 8-bit general-purpose
timer/counter. The 8-bit timer/counter is called timer 0.

Basic Timer (BT)

You can use the basic timer (BT) in two different ways:

-- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction, or

-- To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1,
address D3H, and is read/write addressable using Register addressing mode.

A system reset clears BTCON. This enables the watchdog function and selects a basic timer clock frequency of
f

OSC

/4096. To disable the watchdog function, you must write the signature code '1010B' to the basic timer

register control bits BTCON.7BTCON.4. For more reliability, we recommend to use the Watch-dog timer
function in remote controller and hand-held product application.

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

10-3

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by enabling the watchdog function.
A reset clears BTCON to '00H', automatically enabling the watchdog timer function. A reset also selects the CPU
clock (as determined by the current CLKCON register setting),divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must
prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must
be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always
broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

TIMER 0 CONTROL REGISTER (T0CON)

You use the timer 0 control register, T0CON, to

-- Select the timer 0 operating mode (interval timer)

-- Select the timer 0 input clock frequency

-- Clear the timer 0 counter, T0CNT

-- Enable the timer 0 overflow interrupt or timer 0 match interrupt

-- Clear timer 0 match interrupt pending conditions

T0CON is located in set 1, at address D2H, and is read/write addressable using Register addressing mode.

A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency
of f

OSC

/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal

operation by writing a "1" to T0CON.3.

The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address FAH. When a timer 0
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.

To enable the timer 0 match interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a match
interrupt pending condition, the application program polls T0CON.0. When a "1" is detected, a timer 0 match
interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by
software by writing a "0" to the timer 0 interrupt pending bit, T0CON.0.

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

10-5

TIMER 0 FUNCTION DESCRIPTION

Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)

The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match
interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0, but is
assigned the separate vector address, FCH.

A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.
The T0INT pending condition must, however, be cleared by the application's interrupt service routine by writing a
"0" to the T0CON.0 interrupt pending bit.

Interval Timer Mode

In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)
and clears the counter.

If, for example, you write the value `10H' to T0DATA and `0BH' to T0CON, the counter will increment until it
reaches `10H'. At this point, the T0 interrupt request is generated, the counter value is reset, and counting
resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).

Interrupt

Enable/Disable

(T0CON.1)

Pending

(T0CON.0)

CTL

P2.0

T0CON.5
T0CON.4

Match Signal
T0CON.3

IRQ0(INT)

R (Clear)

CLK

Match

Data Register

Buffer Register

Comparator

Counter

Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode

BASIC TIMER and TIMER 0

S3P80C5/C80C5/C80C8

10-6

Pulse Width Modulation Mode

Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at `FFH', and then continues incrementing from `00H'.

Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used
in PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference
data value is less than or equal to (

) the counter value and then the pulse is held to High level for as long as

the data value is greater than ( > ) the counter value. One pulse width is equal to t

CLK

256 (see Figure 11-4).

Interrupt

Enable/Disable

(T0CON.1)

CTL

P2.0/
T0PWM

T0CON.5
T0CON.4

Match Signal
T0CON.3

IRQ0(T0INT)

IRQ0 (T0OVF)

CLK

Match

Data Register

Buffer Register

Comparator

Counter

T0OVF

(T0CON.0)

High level when
data > counter;
Low level when
data < counter

NOTE: Interrupts are usually not used when timer 0 is configurared to operate in PWM mode

PND

Figure 10-4. Simplified Timer 0 Function Diagram: PWM Mode

S3P80C5/C80C5/C80C8

BASIC TIMER AND TIMER 0

10-9

Programming Tip -- Programming Timer 0

This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and
determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:

-- Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds

-- Oscillation frequency is 4 MHz

-- General register 60H (page 0)

60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0

interrupt

ORG

0FAH

; Timer 0 overflow interrupt

VECTOR

T0OVER

ORG

0FCH

; Timer 0 match/capture interrupt

VECTOR

T0INT

ORG

0100H

RESET

; Disable all interrupts

BTCON,#0AAH

; Disable the watchdog timer

CLKCON,#18H

; Select non-divided clock

CLR

SYM

; Disable global and fast interrupts

CLR

SPL

; Stack pointer low byte

"0"

; Stack area starts at 0FFH

T0CON,#4BH

; Write '01001011B'

; Input clock is f

OSC

/256

; Interval timer mode

; Enable the timer 0 interrupt

; Disable the timer 0 overflow interrupt

T0DATA,#5DH

; Set timer interval to 4 milliseconds

; (4 MHz/256)

(93 + 1) = 0.166 kHz (6 ms)

SRP

#0C0H

; Set register pointer

0C0H

; Enable interrupts

S3P80C5/C80C5/C80C8

TIMER 1

11-1

TIMER 1

OVERVIEW

The S3C80C5/C80C8 microcontroller has a 16-bit timer/counter called timer 1 (T1). For universal remote
controller applications, timer 1 can be used to generate the envelope pattern for the remote controller signal.
Timer 1 has the following components:

-- One control register, T1CON (set 1, FAH, R/W)

-- Two 8-bit counter registers, T1CNTH and T1CNTL (set 1, F6H and F7H, read-only)

-- Two 8-bit reference data registers, T1DATAH and T1DATAL (set 1, F8H and F9H, R/W)

-- A 16-bit comparator

You can select one of the following clock sources as the timer 1 clock:

-- Oscillator frequency (f

OSC

) divided by 4, 8, or 16

-- Internal clock input from the counter A module (counter A flip/flop output)

You can use Timer 1 in two ways:

-- As a normal free run counter, generating a timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time

intervals.

-- To generate a timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit timer 1 count value matches the

16-bit value written to the reference data registers.

In the S3C80C5/C80C8 interrupt structure, the timer 1 overflow interrupt has higher priority than the timer 1
match.

TIMER 1

S3P80C5/C80C5/C80C8

11-2

TIMER 1 OVERFLOW INTERRUPT

Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the
16-bit up counter. When you set the timer 1 overflow interrupt enable bit, T1CON.2, to "1", the overflow interrupt
is generated each time the 16-bit up counter reaches `FFFFH'. After the interrupt request is generated, the
counter value is automatically cleared to `00H' and up counting resumes. By writing a "1" to T1CON.3, you can
clear/reset the 16-bit counter value at any time during program operation.

TIMER 1 MATCH INTERRUPT

Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value
matches the value that is written to the timer 1 reference data registers, T1DATAH and T1DATAL. When a
match condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is
cleared, and up counting resumes from `00H'.

In match mode, program software can poll the timer 1 match interrupt pending bit, T1CON.0, to detect when a
timer 1 match interrupt pending condition exists (T1CON.0 = "1"). When the interrupt request is acknowledged by
the CPU and the service routine starts, the interrupt service routine for vector F6H must clear the interrupt
pending condition by writing a "0" to T1CON.0.

Interrupt

Enable/Disable

(T1CON.2)

Pending

(T1CON.0)

CTL

T1CON.5
T1CON.4

Match Signal
T1CON.3

IRQ1(T1INT)

R (Clear)

CLK

Match

Timer 1 Data High/Low

Buffer Register

Timer 1 High/Low

Buffer Register

16-Bit Comparator

16-Bit UP Counter

(Read-Only)

Figure 11-1. Simplified Timer 1 Function Diagram: Interval Timer Mode

TIMER 1

S3P80C5/C80C5/C80C8

11-4

TIMER 1 CONTROL REGISTER (T1CON)

The timer 1 control register, T1CON, is located in set 1, FAH, and is read/write addressable. T1CON contains
control settings for the following T1 functions:

-- Timer 1 input clock selection

-- Timer 1 operating mode selection

-- Timer 1 16-bit down counter clear

-- Timer 1 overflow interrupt enable/disable

-- Timer 1 match interrupt enable/disable

-- Timer 1 interrupt pending control (read for status, write to clear)

A reset operation clears T1CON to `00H', selecting f

OSC

divided by 4 as the T1 clock, configuring timer 1 as a

normal interval timer, and disabling the timer 1 interrupts.

Timer 1 Control Register (T1CON)

FAH, R/W

MSB

LSB

Timer 1 counter clear bit:
0 = No effect
1 = Clear the timer 1 counter (when write)

Timer 1 input clock selection bits:
00 = f

OSC

01 = f

OSC

10 = f

OSC

/16

11 = Internal clock (T-F/F)

Timer 1 operating mode selection bits:
00 = Interval mode
01 = Overflow mode (OVF interrupt can occur)
01 = Overflow mode (OVF interrupt can occur)
01 = Overflow mode (OVF interrupt can occur)

Timer 1 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt

Timer 1 match interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt

Timer 1 match interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (write)
1 = Interrupt is pending

Figure 11-3. Timer 1 Control Register (T1CON)

S3P80C5/C80C5/C80C8

COUNTER A

12-3

COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in set 1, bank 0, F3H, and is read/write addressable. CACON
contains control settings for the following functions (see Figure 12-2):

-- Counter A clock source selection

-- Counter A interrupt enable/disable

-- Counter A interrupt pending control (read for status, write to clear)

-- Counter A interrupt time selection

Counter A Control Register (CACON)

F3H, Set 1, R/W

MSB

LSB

Counter A input clock
selection bits:
00 = f

OSC

01 = f

OSC

10 = f

OSC

11 = f

OSC

Counter A output flip-flop
control bit:
0 = T-FF is Low
1 = T-FF is High

Counter A mode selection bit:
0 = One-shot mode
1 = Repeating mode

Counter A interrupt selection bits:
00 = Elapsed time for Low data value
01 = Elapsed time for High data value
10 = Elapsed time for Low and High
data values
11 = Invalid setting

Counter A interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt

Counter A start/stop bit:
0 = Stop counter A
1 = Start counter A

Figure 12-2. Counter A Control Register (CACON)

COUNTER A

S3P80C5/C80C5/C80C8

12-4

Counter A Data Low-Byte Register (CADATAL)

F5H, Set 1, R/W

MSB

LSB

Reset Value : FFh

Counter A Data High-Byte Register (CADATAH)

F4H, Set 1, R/W

MSB

LSB

Reset Value : FFh

Figure 12-3. Counter A Registers

COUNTER A PULSE WIDTH CALCULATIONS

LOW

HIGH

LOW

To generate the above repeated waveform consisted of low period time, t

LOW

, and high period time, t

HIGH

When CAOF = 0,
t

LOW

= (CADATAL + 2) x 1/fxx, 0H < CADATAL < 100H, where fx = The selected clock.

HIGH

= (CADATAH + 2) x 1/fxx, 0H < CADATAH < 100H, where fx = The selected clock.

When CAOF = 1,
t

LOW

= (CADATAH + 2) x 1/fxx, 0H < CADATAH < 100H, where fx = The selected clock.

HIGH

= (CADATAL + 2) x 1/fxx, 0H < CADATAL < 100H, where fx = The selected clock.

To make t

LOW

= 24 us and t

HIGH

= 15 us. f

OSC

= 4 MHz, fx = 4 MHz/4 = 1 MHz

[Method 1] When CAOF = 0,

LOW

= 24 us = (CADATAL + 2) /fx = (CADATAL + 2)

1us, CADATAL = 22.

HIGH

= 15 us = (CADATAH + 2) /fx = (CADATAH + 2)

1us, CADATAH = 13.

[Method 2] When CAOF = 1,

HIGH

= 15 us = (CADATAL + 2) /fx = (CADATAL + 2)

1us, CADATAL = 13.

LOW

= 24 us = (CADATAH + 2) /fx = (CADATAH + 2)

1us, CADATAH = 22.

COUNTER A

S3P80C5/C80C5/C80C8

12-6

PROGRAMMING TIP -- To Generate 38 kHz, 1/3duty Signal Through P2.1

This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source,
and CADATAH and CADATAL to make a 38 kHz,1/3 Duty carrier frequency. The program parameters are:

17.59

8.795

37.9 kHz 1/3 Duty

-- Counter A is used in repeat mode

-- Oscillation frequency is 4 MHz (0.25

-- CADATAH = 8.795

s / 0.25

s = 35.18, CADATAL = 17.59

s / 0.25

s = 70.36

-- Set P2.1 C-MOS push-pull output and CAOF mode.

ORG

0100H

; Reset address

START

CADATAL,#(70-2)

; Set 17.5

CADATAH,#(35-2)

; Set 8.75

;

P2CON,#10101010B

; Set P2 to C-MOS push-pull output.

; Set P2.1 to REM output

;

CACON,#00000110B

; Clock Source

OSC

; Disable Counter A interrupt.

; Select repeat mode for Counter A.

; Start Counter A operation.

; Set Counter A Output Flip-flop(CAOF) high.

;

P2,#20H

; Set P2.5(Carrier On/Off) to high.

; This command generates 38 kHz, 1/3duty pulse signal
; through P2.1

;

S3P80C5/C80C5/C80C8

COUNTER A

12-7

PROGRAMMING TIP -- To Generate a One Pulse Signal Through P2.1

This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source,
and CADATAH and CADATAL to make a 40

s width pulse. The program parameters are:

-- Counter A is used in one shot mode

-- Oscillation frequency is 4 MHz (1 clock = 0.25

-- CADATAH = 40

s / 0.25

s = 160, CADATAL = 1

-- Set P2.1 C-MOS push-pull output and CAOF mode.

ORG

0100H

; Reset address

START

CADATAH,# (160-2)

; Set 40

CADATAL,# 1

; Set any value except 00H

;

P2CON,#10101010B

; Set P2 to C-MOS push-pull output.

; Set P2.1 to REM output

;

CACON,#00000001B

; Clock Source

OSC

; Disable Counter A interrupt.

; Select one shot mode for Counter A.

; Stop Counter A operation.

; Set Counter A Output flip-flop (CAOF) high

P2,#20H

; Set P2.5(Carrier On/Off) to high.

Pulse_out:

CACON,#00000101B

; Start Counter A operation

; to make the pulse at this point.

; After the instruction is executed, 0.75

s is required

; before the falling edge of the pulse starts.

ELECTRICAL DATA

S3P80C5/C80C5/C80C8

13-

Table 13-1. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Unit

Supply voltage

0.3 to + 6.5

Input voltage

0.3 to

+ 0.3

Output voltage

All output pins

0.3 to V

+ 0.3

Output current High

One I/O pin active

All I/O pins active

Output current Low

One I/O pin active

+ 30

Total pin current for ports 0, 1, and 2

+ 100

Total pin current for port 3

+ 40

Operating
temperature

40 to + 85

Storage
temperature

STG

65 to + 150

Table 13-2. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 2.0 V to 3.6 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Operating Voltage

OSC

4MHz

(Instruction clock = 0.67 MHz)

1.7

3.6

Input High
voltage

IH1

All input pins except V

IH2

and V

IH3

0.8 V

IH2

0.3

Input Low voltage

IL1

All input pins except V

IL2

and V

IL3

0.2 V

IL2

0.3

Output High
voltage

OH1

= 2.4 V, I

= 6 mA

Port 2.1 only, T

= 25

0.7

OH2

= 2.4 V, I

= 2.2mA

Port 2.0, 2.2, T

= 25

0.7

OH3

= 2.4 V, I

= 1 mA

All output pins except Port2,

= 25

1.0

S3P80C5/C80C5/C80C8

ELECTRICAL DATA

13-

Table 13-2. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 2.0 V to 3.6 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Output Low
voltage

OL1

= 2.4 V, I

= 12 mA, port

2.1 only, T

= 25

0.4

0.5

OL2

= 2.4 V, I

= 5 mA

Port 2.0,2.2, T

= 25

0.4

0.5

OL3

= 1 mA

Ports 0 and 1, T

= 25

0.4

1.0

Input High
leakage current

LIH1

= V

All input pins except X

and

OUT

µA

LIH2

= V

, X

and X

OUT

Input Low
leakage current

LIL1

= 0 V

All input pins except X

, X

OUT

µA

LIL2

= 0 V

and X

OUT

Output High
leakage current

LOH

OUT

= V

All output pins

µA

Output Low
leakage current

LOL

OUT

= 0 V

All output pins

µA

Pull-up resistors

= 2.4V, V

= 0 V;

= 25

C , Ports 0-2

Supply current

(note)

DD1

= 3.6 V

10%

4-MHz crystal

2.6

DD2

Idle mode;
V

= 3.6 V

10 %

4-MHz crystal

0.7

2.0

DD3

Stop mode;
V

= 3.6 V

NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.

ELECTRICAL DATA

S3P80C5/C80C5/C80C8

13-

Table 13-3. Characteristics of Low Voltage Detect circuit

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Hysteresys Voltage of LVD
(Slew Rate of LVD)

300

Low level detect voltage
(S3C80C5/C80C8)

LVD

1.70

1.90

2.1

Table 13-4. Data Retention Supply Voltage in Stop Mode

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply
voltage

DDDR

1.0

3.6

Data retention supply
current

DDDR

= 1.0 V

Stop mode

µA

Table 13-5. Input/output Capacitance

= 40

C to + 85

C, V

0 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input
capacitance

f = 1 MHz; unmeasured pins
are connected to V

Output
capacitance

OUT

I/O capacitance

Table 13-6. A.C. Electrical Characteristics

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Interrupt input,
High, Low width

INTH

INTL

P0.0P0.7, V

3.6

200

300

ELECTRICAL DATA

S3P80C5/C80C5/C80C8

13-

Table 13-8. Oscillation Stabilization Time

= 40

C + 85

C, V

= 3.6 V)

Oscillator

Test Condition

Min

Typ

Max

Unit

Main crystal

OSC

> 400 kHz

Main ceramic

Oscillation stabilization occurs when V

is equal

to the minimum oscillator voltage range.

External clock
(main system)

input High and Low width (t

, t

)

500

Oscillator
stabilization
wait time

WAIT

when released by a reset

(1)

OSC

WAIT

when released by an interrupt

(2)

NOTES:
1.

OSC

is the oscillator frequency.

The duration of the oscillation stabilization time (t

WAIT

) when it is released by an interrupt is determined by the setting

in the basic timer control register, BTCON.

1.33 MHz

250 kHz

8.32 kHz

Supply Voltage (V)

Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, 16)
A 1.7 V:

4 MHz

b 2.0 V:

8 MHz

1.00 MHz

500 kHz

670 kHz

Instruction

Clock

8 MHz

6 MHz

4 kHz

Instruction
Clock

400 kHz

Figure 13-2. Operating Voltage Range of S3P80C5/C80C5/C80C8

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales
representative. Samsung sales offices are listed on the back cover of this book.)

NOTE : Please one more check whether the selected device is S3C80A4/C80A8/C80A5 or S3C80B4/C80B8/C80B5.

S3C8 SERIES MASK ROM ORDER FORM

Product description:

Device Number: S3C80C5 S3C80C8

S3C__________- ___________(write down the ROM code number)

(note)

Product Order Form:

Package

Pellet Wafer

Package Type: __________

Package Marking (Check One):

Standard

Custom A

Custom B

(Max 10 chars)

(Max 10 chars each line)

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

@ YWW

Device Name

SEC

Device Name

@ YWW

Delivery Dates and Quantities:

Deliverable

Required Delivery Date

Quantity

Comments

ROM code

Not applicable

See ROM Selection Form

Customer sample

Risk order

See Risk Order Sheet

Please answer the following questions:

For what kind of product will you be using this order?

New product

Upgrade of an existing product

Replacement of an existing product

Other

If you are replacing an existing product, please indicate the former product name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Development system

Technical support

Delivery on time

Used same micom before

Quality of documentation

Samsung reputation

Mask Charge (US$ / Won):

____________________________

Customer Information:

Company Name:

___________________ Telephone number

_________________________

Signatures:

________________________

__________________________________

(Person placing the order)

(Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung
sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE : Please one more check whether the selected device is S3C80A4/C80A8/C80A5 or S3C80B4/C80B8/C80B5.

S3C8 SERIES

REQUEST FOR PRODUCTION AT CUSTOMER RISK

Customer Information:

Company Name:

________________________________________________________________

Department:

________________________________________________________________

Telephone Number:

__________________________

Fax: _____________________________

Date:

__________________________

Risk Order Information:

Device Number: S3C80C5 S3C80C8

S3C__________- ___________(write down the ROM code number)

(note)

Package:

Number of Pins: ____________

Package Type: _____________________

Intended Application:

________________________________________________________________

Product Model Number:

________________________________________________________________

Customer Risk Order Agreement:

We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk
order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume
responsibility for any and all production risks involved.

Order Quantity and Delivery Schedule:

Risk Order Quantity:

_____________________ PCS

Delivery Schedule:

Delivery Date (s)

Quantity

Comments

Signatures:

_______________________________

_______________________________________

(Person Placing the Risk Order) (SEC Sales Representative)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung
sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

S3C80C5/C80C8

MASK OPTION SELECTION FORM

Device Number: S3C80C5 S3C80C8

S3C8__________- ___________(write down the ROM code number)

(note)

Attachment (Check one):

Diskette

PROM

Customer Checksum:

________________________________________________________________

Company Name:

________________________________________________________________

Signature (Engineer):

________________________________________________________________

Please answer the following questions:

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Caller ID

LCD Game

Industrials

Home Appliance

Office Automation

Remocon

Other

Please describe in detail its application

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung
sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

S3C8 SERIES OTP FACTORY WRITING ORDER FORM (1/2)

Product Description:

Device Number: S3P80C5

S3P8__________- ___________(write down the ROM code number)

(note)

Product Order Form:

Package

Pellet

Wafer

If the product order form is package:

Package Type: _____________________

Package Marking (Check One):

Standard

Custom A

Custom B

(Max 10 chars)

(Max 10 chars each line)

@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly

@ YWW

Device Name

SEC

Device Name

@ YWW

Delivery Dates and Quantity:

ROM Code Release Date

Required Delivery Date of Device

Quantity

Please answer the following questions:

What is the purpose of this order?

New product development

Upgrade of an existing product

Replacement of an existing microcontroller

Other

If you are replacing an existing microcontroller, please indicate the former microcontroller name

(

)

What are the main reasons you decided to use a Samsung microcontroller in your product?

Please check all that apply.

Price

Product quality

Features and functions

Development system

Technical support

Delivery on time

Used same micom before

Quality of documentation

Samsung reputation

Customer Information:

Company Name:

___________________ Telephone number

_________________________

Signatures:

________________________

__________________________________

(Person placing the order) (Technical Manager)

(For duplicate copies of this form, and for additional ordering information, please contact your local Samsung
sales representative. Samsung sales offices are listed on the back cover of this book.)

NOTE: Please one more check whether the selected device is S3P80A4/P80A8/P80A5 or S3P80B4/P80B8/P80B5.

S3C80C5/C80C8

OTP FACTORY WRITING ORDER FORM (2/2)

Device Number: S3P80C5

S3P8__________- ___________(write down the ROM code number)

(note)

Customer Checksums:

_______________________________________________________________

Company Name:

________________________________________________________________

Signature (Engineer):

________________________________________________________________

Read Protection

(1)

Yes

Please answer the following questions:

Are you going to continue ordering this device?

Yes

If so, how much will you be ordering? _________________pcs

Application (Product Model ID: _______________________)

Audio

Video

Telecom

LCD Databank

Caller ID

LCD Game

Industrials

Home Appliance

Office Automation

Remocon

Other

Please describe in detail its application

__________________________________________________________________________

NOTES
1.

Once you choose a read protection, you cannot read again the programming code from the EPROM.

OTP Writing will be executed in our manufacturing site.

The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors
occurred from the writing program.

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3C80C5

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3C80C5

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3C80C5