S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PRODUCT OVERVIEW

1-1

PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung's S3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range
of integrated peripherals and various mask-programmable ROM sizes. Important CPU features include:

-- Efficient register-oriented architecture

-- Selectable CPU clock sources

-- Idle and Stop power-down mode release by interrupt

-- Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.

S3C80E5/C80E7 MICROCONTROLLER

The S3C80E5/C80E7 single-chip CMOS
microcontroller is fabricated using a highly
advanced CMOS process, based on Samsung's
newest CPU architecture.

The S3C80E5/C80E7 is the microcontroller which
has 16/24-Kbyte mask-programmable ROM. The
S3P80E5/P80E7 is the microcontroller which has
16/24-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung
engineers developed the S3C80E5/C80E7 by
integrating the following peripheral modules with the
powerful SAM87 core:

-- Four programmable I/O ports, including three

8-bit ports and one 2-bit port, for a total of 26
pins.

-- Internal LVD circuit and twelve bit-

programmable pins for external interrupts.

-- One 8-bit basic timer for oscillation stabilization

and watchdog functions (system reset).

-- One 8-bit timer/counter and one 16-bit

timer/counter with selectable operating modes.

-- One 8-bit counter with auto-reload function and

one-shot or repeat control.

The S3C80E5/C80E7 is a versatile general-purpose
microcontroller which is especially suitable for use
as unified remote transmitter controller. It is
currently available in a 32-pin SOP and SDIP
package for S3C80E5 and S3C80E7. And available
in 40 DIP package only for S3C80E7.

OTP

The S3P80E5/P80E7 is an OTP (One Time Programmable) version of the S3C80E5/C80E7 microcontroller. The
S3P80E5/P80E7 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of a
masked ROM. The S3P80E5/P80E7 is comparable to the S3C80E5/C80E7, both in function and in pin
configuration.

PRODUCT OVERVIEW

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

1-2

FEATURES

CPU

SAM87 CPU core

Memory

16-Kbyte internal program memory (ROM):
S3C80E5

24-Kbyte internal program memory (ROM):
S3C80E7

256-byte internal (RAM): 800080FFH

Data memory: 317-byte internal register file

Instruction Set

78 instructions

IDLE and STOP instructions added for power-
down modes

Instruction Execution Time

750 ns at 8 MHz f

OSC

(minimum)

Interrupts

Six interrupt levels and 18 interrupt sources

15 vectors (14 sources have a dedicated vector
address and four sources share a single vector)

Fast interrupt processing feature (for one
selected interrupt level)

I/O Ports

Three 8-bit I/O ports (P0P2) and one 2-bit port
(P3) for a total of 26 bit-programmable pins

Twelve input pins for external interrupts

Timers and Timer/Counters

One programmable 8-bit basic timer (BT) for
oscillation stabilization control or watchdog timer
(software reset) function

One 8-bit timer/counter (Timer 0) with three
operating modes; Interval, Capture, and PWM

One 16-bit timer/counter (Timer 1) with two
operating modes; Interval and Capture

Carrier Frequency Generator

One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)

Back-up mode

When reset pin is low level or when V

is lower

than V

LVD

, the chip enters back-up mode to

reduce current consumption.

Low Voltage Detect Circuit

Low voltage detect for reset or back-up mode
input.

· Low level detect voltage :

2.2 V (Typ) 100 mV/+ 200 mV

Operating Temperature Range

C to + 85

Operating Voltage Range

2.0 V to 5.5 V at 4 MHz f

OSC

2.1 V to 5.5 V at 8 MHz f

OSC

Package Type

32-pin SOP

32-pin SDIP

40-pin DIP

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PRODUCT OVERVIEW

1-3

BLOCK DIAGRAM

I/O PORT and INTERRUPT

CONTROL

SAM87

CPU

INTERNAL BUS

8-BIT

BASIC

TIMER

PORT2

OUT

PROGRAM

MEMORY

(16/24-Kbyte Program
Memory and 256-Byte

Program RAM)

317-BYTE

FILE

P2.0P2.3
(INT5INT8)
P2.4P2.7

PORT 0

P1.0P1.7

PORT 1

8-BIT

TIMER/

COUNTER

16-BIT

TIMER/

COUNTER

CARRIER

GENERATOR

(COUNTER A)

RESET

TEST

PORT 3

P3.1/REM/T0CK

P3.0/T0PWM/
T0CAP/T1CAP

P0.0P0.7

(INT0INT4)

MAIN

OSC

LVD

Figure 1-1. Block Diagram

PRODUCT OVERVIEW

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

1-4

PIN ASSIGNMENTS

OUT

TEST

P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4

P3.1/REM/T0CK
P3.0/T0PWM/T0CAP/T1CAP
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

S3C80E5
S3C80E7

32-SOP/SDIP

(Top View)

RESET/BACK-UP MODE

Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package)

OUT

TEST

NC
NC

P2.0/INT5
P2.1/INT6
P2.2/INT7
P2.3/INT8
P0.0/INT0
P0.1/INT1
P0.2/INT2
P0.3/INT3

NC
NC

P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4

P3.1/REM/T0CK

P3.0/T0PWM/T0CAP/T1CAP
NC
NC
P2.7
P2.6
P2.5
P2.4
P1.7
P1.6
P1.5
P1.4
NC
NC
P1.3
P1.2
P1.1
P1.0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

S3C80E5
S3C80E7

40-DIP

(Top View)

RESET/BACK-UP MODE

Figure 1-3. Pin Assignment (40-Pin DIP Package)

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PRODUCT OVERVIEW

1-5

Table 1-1. Pin Descriptions

Pin

Names

Pin

Type

Pin

Description

Circuit

Type

Pin No.

(32-pin)

Pin No.

(40-pin)

Shared

Functions

P0.0P0.7

I/O

I/O port with bit-programmable pins.
Configurable to input or push-pull output
mode. Pull-up resistors are assignable by
software. Pins can be assigned individually
as external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt
pending control.

916

1114,

1720

INT0INT4

P1.0P1.7

I/O

I/O port with bit-programmable pins.
Configurable to C-MOS input mode or
output mode. Pin circuits are either push-
pull or n-channel open-drain type. Pull-up
resistors are assignable by software.

1724

2124,

2730

P2.0P2.3
P2.4P2.7

I/O

General-purpose I/O port with bit-
programmable pins. Configurable to C-
MOS input mode, push-pull output mode, or
n-channel open-drain output mode. Pull-up
resistors are assignable by software. Lower
nibble pins, P2.3P2.0, can be assigned as
external interrupt inputs with noise filters,
interrupt enable/disable, and interrupt
pending control.

3
4

58,

2528

710,

3134

INT5INT8

P3.0
P3.1

I/O

2-bit I/O port with bit-programmable pins.
Configurable to C-MOS input mode, push-
pull output mode, or n-channel open-drain
output mode. Pull-up resistors are
assignable by software. The two port 3 pins
have high current drive capability.

29
30

T0PWM/

T0CAP/
T1CAP/

REM/T0CK

, X

OUT

System clock input and output pins

2, 3

RESET/

BACK-UP

MODE

System reset signal input pin and back-up
mode input pin. The pin circuit is a C-MOS
input.

TEST

Test signal input pin (for factory use only;
must be connected to V

Power supply input pin

Ground pin

PRODUCT OVERVIEW

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

1-6

PIN CIRCUITS

PULL-UP RESISTOR

(Typical 21 K

)

VDD

I/O

DATA

PULL-UP

ENABLE

NORMAL

INPUT

OUTPUT

DISABLE

INTERRUPT INPUT

IRQ6,7 (INT0-4)

Oscillator Release (SED and R circuit)

STOP

NOISE

FILTER

To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5
has a special logic_ SED and R circuit

related to P0 and P1. This is a specific function for key

input/output of universal remote controller. When these ports (P0, P1) are used as a normal
input pin, unexpected stop mode recovery can occur by input level switching. Hence, the user
should be aware of input level switching, if P0 and P1 are to be used as normal input ports.

NOTE:

Figure 1-4. Pin Circuit Type 1 (Port 0)

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PRODUCT OVERVIEW

1-7

PULL-UP RESISTOR

(Typical 21 K

)

VDD

I/O

DATA

PULL-UP

ENABLE

OUTPUT

DISABLE

NORMAL INPUT

Oscillator Release (SED and R circuit)

STOP

NOISE

FILTER

To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5
has a special logic

SED and R circuit

related to P0 and P1. This is a specific function for key

input/output of universal remote controller. When these ports (P0, P1) are used as a normal
input pin, unexpected stop mode releasing can occur by input level switching. Hence, the user
should be aware of input level switching, if P0 and P1 are to be used as normal input ports.

NOTE:

Figure 1-5. Pin Circuit Type 2 (Port 1)

PRODUCT OVERVIEW

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

1-10

PULL-UP RESISTOR

(Typical 21 K

)

VDD

I/O

DATA

PULL-UP

ENABLE

OUTPUT

DISABLE

OPEN-DRAIN

NORMAL INPUT

NOISE
FILTER

ALTERNATIVE

INPUT

M
U

PORT 3 DATA

ALTERNATIVE

OUTPUT

SELECT

Figure 1-8. Pin Circuit Type 5 (P 3)

BACK-UP MODE

SYSTEM

RESET

RESET/

BACK-UP

MODE

NOISE

FILTER

Figure 1-9. Pin Circuit Type 6 (

RESET

BACK-UP MODE

)

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

ELECTRICAL DATA

14-1

ELECTRICAL DATA

OVERVIEW

In this section, the S3C80E5/C80E7 electrical characteristics are presented in tables and graphs. The information
is arranged in the following order:

-- Absolute maximum ratings

-- D.C. electrical characteristics

-- Characteristics of low voltage detect circuit

-- Data retention supply voltage in Stop mode

-- Stop mode release timing when initiated by an external interrupt

-- Stop mode release timing when initiated by a

RESET

-- Stop mode release timing when initiated by a LVD

-- I/O capacitance

-- A.C. electrical characteristics

-- Input timing for external interrupts (port 0, P2.3P2.0)

-- Input timing for

RESET

-- Oscillation characteristics

-- Oscillation stabilization time

-- Operating voltage range

ELECTRICAL DATA

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

14-2

Table 14-1. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Unit

Supply voltage

0.3 to + 6.5

Input voltage

0.3 to

+ 0.3

Output voltage

All output pins

0.3 to V

+ 0.3

Output current High

One I/O pin active

All I/O pins active

Output current Low

One I/O pin active

+ 30

Total pin current for ports 0, 1, and 2

+ 100

Total pin current for port 3

+ 40

Operating
temperature

40 to + 85

Storage
temperature

STG

65 to + 150

Table 14-2. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Operating Voltage

OSC

8 MHz

(Instruction clock = 1.33 MHz)

2.1

5.5

OSC

4 MHz

(Instruction clock = 0.67 MHz)

2.0

5.5

Input High

IH1

All input pins except V

IH2

and V

IH3

0.8 V

voltage

IH2

RESET

0.85 V

IH3

0.3

Input Low voltage

IL1

All input pins except V

IL2

and V

IL3

0.2 V

IL2

RESET

0.4 V

IL3

0.3

Output High
voltage

OH1

= 2.4 V; I

= 6 mA

Port 3.1 only; T

= 25

0.7

OH2

= 2.4 V; I

= 3 mA

Port 3.0 only; T

= 25

0.7

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

ELECTRICAL DATA

14-3

Table 14-2. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Output High
voltage

OH3

= 5 V; I

= 3 mA

Port 2.7 only; T

= 25

0.25

= 2 V; I

= 1 mA

Port 2.7 only; T

= 25

OH4

= 3.0 V; I

= 1 mA

All output pins except P3 and P2.7
port; T

= 25

Output Low
voltage

OL1

= 2.4 V; I

= 15 mA

Port 3.1 only; T

= 25

0.4

0.5

OL2

= 2.4 V; I

= 5 mA

Port 3.0 only; T

= 25

0.4

0.5

OL3

= 1 mA

Port 0, 1, and 2; T

= 25

0.4

Input High
leakage current

LIH1

= V

All input pins except X

and X

OUT

µA

LIH2

= V

, X

IN,

and X

OUT

Input Low
leakage current

LIL1

= 0 V

All input pins except X

, X

OUT

and

RESET

µA

LIL2

= 0 V

and X

OUT

Output High
leakage current

LOH

OUT

= V

All output pins

µA

Output Low
leakage current

LOL

OUT

= 0 V

All output pins

µA

Pull-up resistors

= 0 V; V

= 2.4 V

= 25

C; Ports 03

= 5.5 V

ELECTRICAL DATA

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

14-4

Table 14-2. D.C. Electrical Characteristics (Concluded)

= 40

C to + 85

C, V

= 2 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Supply current

(note)

DD1

Operating mode
V

= 5 V

10 %

8 MHz crystal

4 MHz crystal

4.5

DD2

Idle mode
V

= 5 V

10 %

8 MHz crystal

1.8

3.5

4 MHz crystal

1.6

DD3

Stop mode
V

= 6.0 V

= 5.5 V

= 3.3 V

= 0.7 V

1.0

1.5

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

Table 14-3. Characteristics of Low Voltage Detect Circuit

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Hysteresys Voltage of
LVD(Slew Rate of LVD)

LVDCON = 10001111B

100

Low level detect voltage

LVD

LVDCON = 10001111B

2.10

2.20

2.40

NOTE: The reset values of bit 1 and bit 0 are in a unknown status, so is recommended to input the value #8FH in LVDCON

for typical V

LVD

(2.2 V 100/+200 mV).

Table 14-4. Data Retention Supply Voltage in Stop Mode

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply
voltage

DDDR

1.0

5.5

Data retention supply
current

DDDR

= 1.0 V

Stop mode

µA

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

ELECTRICAL DATA

14-5

EXT

INT

EXECUTION OF

STOP INSTRUCTION

LVD

DATA RETENTION MODE

STOP MODE

NORMAL
OPERATING
MODE

WAIT

0.2 V

0.8 V

IDLE MODE

(Basic Timer active)

~ ~

Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt

RESET

EXECUTION OF

STOP INSTRUCTION

DATA RETENTION MODE

STOP MODE

NORMAL
OPERATING
MODE

WAIT

OSCILLATION

STABILIZATION

TIME

RESET

OCCURS

~ ~

NOTE: t

WAIT

is the same as 4096 x 16 x

LVD

1/f

OSC

Figure 14-2. Stop Mode Release Timing When Initiated by a

RESET

ELECTRICAL DATA

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

14-6

EXECUTION OF

STOP INSTRUCTION

DDDR

BACK-UP MODE

STOP MODE

NORMAL
OPERATING
MODE

WAIT

OSCILLATION

STABILIZATION

~ ~

DATA RETENTION MODE

RESET OCCUR

LVD

NOTE: t

WAIT

is the same as 4096 x 16 x 1/f

OSC

Figure 14-3. Stop Mode Release Timing When Initiated by a LVD

Table 14-5. Input/output Capacitance

= 40

C to + 85

C, V

0 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input capacitance

f = 1 MHz; unmeasured pins
are connected to V

Output capacitance

OUT

I/O capacitance

Table 14-6. A.C. Electrical Characteristics

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Interrupt input, High,
Low width

INTH

INTL

P0.0P0.7, P2.3P2.0
V

= 5 V

200

300

RESET

input Low

width

RSL

Input
V

= 5 V

1000

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

ELECTRICAL DATA

14-7

INTL

INTH

0.8 V

0.2 V

NOTE: The unit t

CPU

means one CPU clock period.

Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3P2.0)

Back-Up Mode (STOP MODE)

RESET

OCCRURRS

OSCILLATION
STABILIZATION
TIME

NORMAL
OPERATING
MODE

WAIT

NORMAL
OPERATING
MODE

NOTE: t

WAIT

is the same as 4096 x 16 x 1/f

OSC

Figure 14-5. Input Timing for

RESET

ELECTRICAL DATA

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

14-8

Table 14-7. Oscillation Characteristics

= 40

C + 85

Oscillator

Clock Circuit

Conditions

Min

Typ

Max

Unit

Crystal

OUT

CPU clock oscillation
frequency

MHz

Ceramic

OUT

CPU clock oscillation
frequency

MHz

External clock

S3C80E5

S3C80E7

EXTERNAL

CLOCK

OPEN PIN

OUT

input frequency

MHz

Table 14-8. Oscillation Stabilization Time

= 40

C + 85

C, V

= 4.5 V to 5.5 V)

Oscillator

Test Condition

Min

Typ

Max

Unit

Main crystal

OSC

> 400 kHz

Main ceramic

Oscillation stabilization occurs when V

is equal

to the minimum oscillator voltage range.

External clock
(main system)

input High and Low width (t

, t

)

500

Oscillator
stabilization

WAIT

when released by a reset

(1)

OSC

Wait time

WAIT

when released by an interrupt

(2)

NOTES:
1.

OSC

is the oscillator frequency.

The duration of the oscillation stabilization time (t

WAIT

) when it is released by an interrupt is determined by the setting

in the basic timer control register, BTCON.

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

MECHANICAL DATA

15-1

MECHANICAL DATA

OVERVIEW

The S3C80E5/C80E7 microcontroller is currently available in 32-pin SOP and SDIP package. The S3C80E7 is
also available in 40 DIP package.

8°

0.25

+0.10
- 0.05

8.34

± 0.2

0.90

± 0.20

10.02

± 0.1

#16

#32

#17

32-SOP-450A

12.00

± 0.2

NOTE:

Dimensions are in millimeters.

19.90

± 0.05

0.10 MAX

0.05 MIN

2.00

± 0.1

2.30MAX

(0.43)

0.40

± 0.1

1.27

Figure 15-1. 32-Pin SOP Package Mechanical Data

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

S3P80E5/P80E7 OTP

16-1

S3P80E5/P80E7 OTP

OVERVIEW

The S3P80E5/P80E7 single-chip CMOS microcontroller is the OTP (One Time Programmable)

version of the

S3C80E5/C80E7microcontroller. It has an on-chip EPROM instead of a masked ROM.

The S3P80E5/P80E7 is fully compatible with the S3C80E5/C80E7, both in function and in pin configuration.
Because of its simple programming requirements, the S3P80E5/P80E7 is ideal as an evaluation chip for the
S3C80E5/C80E7.

A14

(2)

OUT

MODE/TEST

PGM/P2.0/INT5

MEM_REG/P2.1/INT6

A8/P2.2/INT7
A9/P2.3/INT8
A0/P0.0/INT0
A1/P0.1/INT1
A2/P0.2/INT2
A3/P0.3/INT3
A4/P0.4/INT4
A5/P0.5/INT4
A6/P0.6/INT4
A7/P0.7/INT4

P3.1/REM/T0CK/ CE

P3.0/T0PWM/T0CAP/T1CAP/ OE
P2.7/ A13
P2.6/ A12
P2.5/ A11
P2.4/ A10
P1.7/ D7
P1.6/ D6
P1.5/ D5
P1.4/ D4
P1.3/ D3
P1.2/ D2
P1.1/ D1
P1.0/ D0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

S3P80E5
S3P80E7

32-SOP/SDIP

(Top View)

RESET/V

NOTES:
1. The bolds indicate an OTP pin name.
2. The address line 14 (A14) be used only for S3P80E7.

Figure 16-1. S3P80E5/P80E7 Pin Assignments of 32SOP/32SDIP

S3P80E5/P80E7 OTP

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

16-2

A14/X

OUT

MODE/TEST

NC
NC

PGM/P2.0/INT5

MEM_REG/P2.1/INT6

A8/P2.2/INT7
A9/P2.3/INT8
A0/P0.0/INT0
A1/P0.1/INT1
A2/P0.2/INT2
A3/P0.3/INT3

NC
NC

A4/P0.4/INT4
A5/P0.5/INT4
A6/P0.6/INT4
A7/P0.7/INT4

P3.1/REM/T0CK/ CE
P3.0/T0PWM/T0CAP/T1CAP/OE
NC
NC
P2.7/A13
P2.6/A12
P2.5/A11
P2.4/A10
P1.7/D7
P1.6/D6
P1.5/D5
P1.4/D4
NC
NC
P1.3/D3
P1.2/D2
P1.1/D1
P1.0/D0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

S3P80E5
S3P80E7

40-DIP

(Top View)

RESET/V

NOTES:
1. The bolds indicate an OTP pin name.
2. The address line 14 (A14) be used only for S3P80E7.

Figure 16-2. S3P80E5/P80E7 Pin Assignments of 40DIP

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

S3P80E5/P80E7 OTP

16-3

Table 16-1. 32 SOP/SDIP Pin Descriptions Used to Read/Write the EPROM

Pin Name

Pin No.

I/O

Function

A0A14

3, 7 6, 2528

Address lines to read/write EPROM

D0D7

1724

I/O

8-bit data input/output lines to read/write EPROM

MODE

Select EPROM mode.

Chip enable (Connect to V

, when read/write EPROM)

Output enable

PGM

EPROM Program enable

MEM_

REG

Select Memory space of EPROM

Supply voltage (normally 5 V)

EPROM Program/Verify voltage (normally 12.5 V)

GROUND

System Clock input pin

CHARACTERISTICS OF EPROM OPERATION

When +12.5 V is supplied to V

and MODE pins of the S3P80E5/P80E7, the EPROM programming mode is

entered. The operating mode (read, write) is selected according to the input signals to the pins listed in Table 16-
2 as below.

Table 16-2. Operating Mode Selection Criteria

MODE

PGM

MEM

Mode

5 V

12.5 V

READ

PROGRAM

PROGRAM VERIFY

NOTE: "0" means Low level; "1" means High level.

S3P80E5/P80E7 OTP

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

16-4

MODE

-
-

A14

-
-

OED

ACC

OEW

OEH

12.5V

Figure 16-3. OTP Read Timing

Table 16-3. OTP Read Characteristics

= 25

C ± 5

C, V

= 5 V ± 5 %, V

= 12.5 V ± 0.25V)

Parameter

Symbol

Min

Typ

Max

Units

Address to Output Delay

ACC

to Address Delay

OED

Pulse Width

OEW

Output hold from

whichever occurs first

OEH

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

S3P80E5/P80E7 OTP

16-5

PGM

-
-

A14

-
-

OEW

OEH

Data In Stable

Data Out Valid

PROGRAM VERIFY

PROGRAM

MODE

Figure 16-4. Program Memory Write Timing

Table 16-4. OTP Program/Program Verify Characteristics

= 25

C ± 5

C, V

= 5 V ± 5 %, V

= 12.5 V ± 0.25 V)

Parameter

Symbol

Min

Typ

Max

Units

Setup Time

µs

Data Setup Time

Data Hold Time

PGM

Pulse Width

300

500

Data Valid from

Pulse Width

OEW

Output Enable to Output Float
Delay

OEH

130

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

S3P80E5/P80E7 OTP

16-7

Table 16-5. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Operating Voltage

OSC

8 MHz

(Instruction clock = 1.33 MHz)

2.1

5.5

OSC

4 MHz

(Instruction clock = 0.67 MHz)

2.0

5.5

Input High

IH1

All input pins except V

IH2

and V

IH3

0.8 V

voltage

IH2

RESET

0.85 V

IH3

0.3

Input Low voltage

IL1

All input pins except V

IL2

and V

IL3

0.2 V

IL2

RESET

0.4 V

IL3

0.3

Output High
voltage

OH1

= 2.4 V; I

= 6 Ma

Port 3.1 only; T

= 25

0.7

OH2

= 2.4 V; I

= 3 mA

Port 3.0 only; T

= 25

0.7

Output High
voltage

OH3

= 5 V; I

= 3 mA

Port 2.7 only; T

= 25

0.25

= 2 V; I

= 1 mA

Port 2.7 only; T

= 25

OH4

= 3.0 V; I

= 1 mA

All output pins except P3 and P2.7
port; T

= 25

Output Low
voltage

OL1

= 2.4 V; I

= 15 mA

Port 3.1 only; T

= 25

0.4

0.5

OL2

= 2.4 V; I

= 5 mA

Port 3.0 only; T

= 25

0.4

0.5

OL3

= 1 mA

Port 0, 1, and 2; T

= 25

0.4

Input High
leakage current

LIH1

= V

All input pins except X

and X

OUT

µA

LIH2

= V

, X

and X

OUT

S3P80E5/P80E7 OTP

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

16-8

Table 16-5. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 2.0 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Low
leakage current

LIL1

= 0 V

All input pins except X

, X

OUT

, and

RESET

µA

LIL2

= 0 V

and X

OUT

Output High
leakage current

LOH

OUT

= V

All output pins

µA

Output Low
leakage current

LOL

OUT

= 0 V

All output pins

µA

Pull-up resistors

= 0 V; V

= 2.4 V

= 25

C; Ports 03

= 5.5 V

Supply current

(note)

DD1

Operating mode
V

= 5 V

10 %

8 MHz crystal

4 MHz crystal

4.5

DD2

Idle mode
V

= 5 V

10 %

8 MHz crystal

1.8

3.5

4 MHz crystal

1.6

DD3

Stop mode;
V

= 6.0 V

= 5.5 V

= 3.3 V

= 0.7 V

1.0

1.5

NOTE: Supply current does not include the current drawn through internal pull-up resistors or external output current loads.

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