S3C8478/C8475/P8475
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
SAM87RC PRODUCT FAMILY
Samsung's new SAM87RC family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a
wide range of integrated peripherals, and various mask-programmable ROM sizes.
Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RC
microcontrollers have an external interface that provides access to external memory and other peripheral
devices.
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
one interrupt level at a time.
S3C8478/C8475 MICROCONTROLLER
The S3C8478/C8475 single-chip 8-bit microcontroller is designed for useful 10-bit resolution A/D converter,
UART, PWM application field. Its powerful SAM87RC CPU architecture includes. The internal register file is
logically expanded to increase the on-chip register space.
The S3C8478/C8475 has 8/16K bytes of on-chip program ROM. Following Samsung's modular design approach,
the following peripherals are integrated with the SAM87RC core:
-- Large number of programmable I/O ports (42 SDIP: 34 pins, 44 QFP: 36 pins)
-- One asynchronous UART module
-- Analog-to-digital converter with eight input channels and 10-bit resolution
-- One 8-bit basic timer for watchdog function
-- One 8-bit timer/counter with three operating modes (Timer 0)
-- One general-purpose 16-bit timer/counters with three operating modes (Timer 1)
The S3C8478/C8475 is a versatile general-purpose microcontroller that is ideal for use in a wide range of
electronics applications requiring complex timer/counter, PWM, capture, and UART.
It is available in a 42-pin SDIP or 44-pin QFP package.
OTP
The S3C8475 is an OTP (One Time Programmable) version of the S3C8478/C8475 microcontroller. The
S3C8475 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of a masked ROM.
The S3C8475 is comparable to the S3C8478/C8475, both in function in D.C. electrical characteristics and in pin
configuration.
PRODUCT OVERVIEW
S3C8478/C8475/P8475
1-2
FEATURES
CPU
SAM87RC CPU core
Memory
272-byte general purpose register area
8/16K-byte internal program memory
Instruction Set
79 instructions
IDLE and STOP instructions added for
power-down modes
Instruction Execution Time
333 ns at 12 MHz f
OSC
(minimum)
Interrupts
14 interrupt sources and 14 vectors
Eight interrupt levels
Fast interrupt processing
General I/O
Five I/O ports (total 36 pins)
Four bit-programmable ports
Two n-channel open-drain output port
Timer/Counters
One 8-bit basic timer for watchdog function
One 8-bit timer/counter with three operating
modes (timer 0)
One 16-bit general-purpose timer/counters with
three operation modes (timer 1)
UART
One UART module
Full duplex serial I/O interface with three UART
modes
A/D Converter
Eight analog input pins
10-bit conversion resolution
20 s conversion time (10 MHz CPU clock)
Buzzer Frequency Output
200 Hz to 20 kHz signal can be generated
Oscillator Frequency
1 MHz to 12 MHz external crystal oscillator
Maximum 12 MHz CPU clock
Operating Temperature Range
40
C to + 85
C
Operating Voltage Range
1.8 V to 5.5 V
Package Types
42-pin SDIP, 44-pin QFP
S3C8478/C8475/P8475
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Basic
Timer
P1.3/BUZ
P1.5/TxD
P1.4/RxD
ADC0-ADC7
T1(CAP)
T1(PWM)
T0(CAP)
T0(PWM)
X
OUT
X
IN
OSC
BUZ
UART
ADC
Timer 1
Timer 0
P1.0-P1.5
T0, T1CK, T1,
BUZ, RxD, TxD
Port 0
P0.0-P0.7
Port I/O and Interrupt
Control
8/16-Kbyte
ROM
272-byte
Register
File
SAM87RC CPU
Port 1
Port 2
P2.0-P2.7
INT0-INT7
Port 3
P3.0-P3.7
ADC0-ADC7
Port 4
P4.0-P4.3
P4.4-P4.5
Figure 1-1. Block Diagram
PRODUCT OVERVIEW
S3C8478/C8475/P8475
1-4
PIN ASSIGNMENTS
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P4.3
P4.2
V
DD
V
SS
X
OUT
X
IN
TEST
P4.1
P4.0
RESET
P2.0/INT0
P2.1/INT1
P2.2/INT2
S3C8478
S3C8475
42-SDIP
(Top-View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P1.0/T0 (CAP/PWM)
P1.1/T1CK
P1.2/T1 (CAP/PWM)
P1.3/BUZ
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AV
SS
AV
REF
P2.7/INT7
P2.6/INT6
P2.5/INT5
P2.4/INT4
P2.3/INT3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
S3C8478/C8475/P8475
PRODUCT OVERVIEW
1-5
P0.1
P0.0
P4.3
P4.2
V
DD
V
SS
X
OUT
X
IN
TEST
P4.1
P4.0
S3C8478
S3C8475
44-QFP
(Top-View)
1
2
3
4
5
6
7
8
9
10
11
P4.4
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0/T0(CAP/PWM)
P1.1/T1CK
P1.2/T1(CAP/PWM)
P1.3/BUZ
44
43
42
41
40
39
38
37
36
35
34
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AV
SS
33
32
31
30
29
28
27
26
25
24
23
RESET
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P4.5
AV
REF
12
13
14
15
16
17
18
19
20
21
22
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
PRODUCT OVERVIEW
S3C8478/C8475/P8475
1-6
Table 1-1. S3C8478/C8475 Pin Descriptions
Pin
Name
Pin
Type
Pin Description
Circuit
Number
Pin
Number
Share
Pins
P0.0P0.7
I/O
Nibble-programmable I/O port for Schmitt trigger
input or push-pull, open-drain output. Pull-up
resistors are assignable by software.
E
8-1
(2-1,
43-38)
P1.0P1.5
I/O
Bit-programmable I/O port for Schmitt trigger input
or push-pull output. Pull-up resistors are assignable
by software. Port 1 pin can also by used as
alternative function (T0, T1CK, T1, BUZ, RxD, TxD)
D
42-37
(37-32)
T0, T1CK,
T1, BUZ,
RxD, TxD
P2.0P2.7
I/O
Bit-programmable I/O port for Schmitt trigger input
or push-pull output. Pull-up resistors are assignable
by software. Port 2 pins can also be used as
external interrupt.
D
19-26
(13-20)
INT0-
INT7
P3.0P3.7
I/O
Bit-programmable I/O port for Schmitt trigger input
or push-pull output. Pull-up resistors are assignable
by software. Port 3 pins can also be used as A/D
converter by software.
F
29-36
(24-31)
ADC0-
ADC7
P4.0P4.3
I/O
Bit-programmable I/O port for Schmitt trigger input
or push-pull, open-drain output. Pull-up resistors are
assingable by software.
E
17-16,
10-9
(11-10,
4-3)
P4.4P4.5
O
Push-pull output only
C
(44, 21)
X
IN,
X
OUT
Crystal or ceramic oscillator signal for system clock.
14, 13
(8, 7)
RESET
I
System reset signal input pin.
B
18 (12)
TEST
I
Test signal input pin (for factory use only; muse be
connected to V
SS
)
15 (9)
AV
REF,
AV
SS
A/D converter reference voltage input and ground
27, 28
(22, 23)
V
DD,
V
SS
Voltage input pin and ground
11, 12
(5, 6)
T0
I/O
Timer 0 capture input or PWM output pin
D
42 (37)
P1.0
T1CK
I
Timer 1 external clock input pin
D
41 (36)
P1.1
T1
I/O
Timer 1 capture input or PWM output pin
D
40 (35)
P1.2
BUZ
O
200Hz-20kHz frequency output for buzzer sound
D
39 (34)
P1.3
RxD
I/O
UART receive and transmit input or output
D
38 (33)
P1.4
TxD
O
UART transmit output
D
37 (32)
P1.5
INT0-INT7
I
External interrupt input
E
19-26
(13-20)
P2.0-P2.7
ADC0-
ADC7
I
A/D converter input
F
29-36
(24-31)
P3.0-P3.7
NOTE: Pin numbers shown in parentheses "( )" are for the 44-pin QFP package.
S3C8478/C8475/P8475
PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
P-Channel
N-Channel
In
V
DD
Figure 1-4. Pin Circuit Type A
Schmitt Trigger
In
V
DD
Pull-Up
Resistor
Figure 1-5. Pin Circuit Type B
P-Channel
N-Channel
V
DD
Out
Output
DIsable
Data
Figure 1-6. Pin Circuit Type C
Output
DIsable
Pull-up
Enable
In/Out
Circuit
Type C
V
DD
Data
Data
Figure 1-7. Pin Circuit Type D
PRODUCT OVERVIEW
S3C8478/C8475/P8475
1-8
Schmitt Trigger
N-CH
V
DD
Pull-up
Enable
V
DD
In/Out
PNE
47 K
P-CH
Output
DIsable
Data
Figure 1-8. Pin Circuit Type E
Output
DIsable
Pull-up
Enable
In/Out
Circuit
Type C
V
DD
Data
Data
TO ADC
Figure 1-9. Pin Circuit Type F
S3C8478/C8475/P8475
ELECTRICAL DATA
14-1
14
ELECTRICAL DATA
OVERVIEW
In this chapter, S3C8478/C8475 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
-- Absolute maximum ratings
-- Input/output capacitance
-- D.C. electrical characteristics
-- A.C. electrical characteristics
-- Oscillation characteristics
-- Oscillation stabilization time
-- Data retention supply voltage in stop mode
-- UART timing characteristics in mode 0
-- A/D converter electrical characteristics
ELECTRICAL DATA
14-2
Table
1. Absolute Maximum Ratings
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply Voltage
V
DD
0.3 to + 6.5
V
Input Voltage
V
I
All ports
0.3 to V
DD
+ 0.3
V
Output Voltage
V
O
All output ports
0.3 to V
DD
+ 0.3
V
Output Current High
I
OH
One I/O pin active
18
mA
All I/O pins active
60
Output Current Low
I
OL
One I/O pin active
+ 30
mA
Total pin current for ports 1, 2, and 3
+ 100
Total pin current for ports 0 and 4
+ 200
Operating
Temperature
T
A
40 to + 85
C
Storage Temperature
T
STG
65 to + 150
C
S3C8478/C8475/P8475
ELECTRICAL DATA
14-3
Table 14-2. D.C. Electrical Characteristics
(T
A
=
-
40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input High
Voltage
V
IH1
Ports 0, 1, 2, 3 ,4
and
RESET
V
DD
= 2.7 to 5.5 V
0.8 V
DD
V
DD
V
V
IH3
X
IN,
and X
OUT
V
DD
0.1
Input Low
Voltage
V
IL1
Ports 0, 1, 2, 3, 4
and
RESET
V
DD
= 2.7 to 5.5 V
0.2
V
DD
V
V
IL3
X
IN
and X
OUT
0.1
Output High
V
OH
I
OH
= 1 mA
V
DD
= 4.5 to 5.5 V
V
DD
1.0
Voltage
Ports 0, 1, 2, 3, 4
Output Low
Voltage
V
OL1
I
OL
= 15 mA
V
DD
= 4.5 to 5.5 V
0.4
2.0
V
Port 0, and 4
V
OL2
I
OL
= 4 mA
V
DD
= 4.5 to 5.5 V
0.4
2.0
V
Ports 1, 2, and 3
Input High
Leakage Current
I
LIH1
All input pins except
I
LIH2
and
RESET
V
IN
= V
DD
1
uA
I
LIH2
X
IN,
and X
OUT
V
IN
= V
DD
20
Input Low
Leakage Current
I
LIL1
All input pins except
I
LIL2
V
IN
= 0 V
1
uA
I
LIL2
X
IN,
and X
OUT
V
IN
= 0 V
20
Output High
Leakage Current
I
LOH
All output pins
V
OUT
= V
DD
2
uA
Output Low
Leakage Current
I
LOL
All output pins
V
OUT
= 0 V
2
uA
Pull-up Resistor
R
P1
V
IN
= 0 V, Ports 0-4 V
DD
= 5 V
30
47
70
K
R
P1
RESET
V
DD
= 5 V
100
200
350
Supply Current
I
DD1
RUM mode
12 MHz CPU clock
V
DD
= 4.5 to 5.5 V
10
20
mA
3 MHz CPU clock
V
DD
= 1.8 to 2.2 V
1.1
3
I
DD2
Idle mode
12 MHz CPU clock
V
DD
= 4.5 to 5.5 V
4
8
3 MHz CPU clock
V
DD
= 1.8 to 2.2 V
0.6
1.5
I
DD3
Stop mode
V
DD
= 4.5 to 5.5 V
0.1
5
uA
V
DD
= 1.8 to 2.2 V
0.1
3
ELECTRICAL DATA
S3C8478/C8475/P8475
14-4
Table 14-3. A.C. Electrical Characteristics
(T
A
=
-
40
C to + 85
C, V
DD
= 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt Input
High, Low Width
t
INTH
,
t
INTL
Ports 2
V
DD
= 5 V
10 %
200
ns
RESET
Input
Low Width
t
RSL
Input
V
DD
= 5 V
10 %
1
s
t
INTH
t
INTL
0.8 V
DD
0.2 V
DD
t
RST
Figure 14-1. Input Timing Measurement Points
S3C8478/C8475/P8475
ELECTRICAL DATA
14-5
Table 14-4. Oscillation Characteristics
(T
A
= 40
C + 85
C)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Main Crystal or
V
DD
= 4.5 V to 5.5 V
1
12
MHz
Ceramic
V
DD
= 2.7 V to 4.5 V
8
X
IN
C1
C2
X
OUT
V
DD
= 1.8 V to 2.7 V
3
External Clock
V
DD
= 4.5 V to 5.5 V
1
12
MHz
(Main System)
V
DD
= 2.7 V to 4.5 V
8
X
IN
X
OUT
V
DD
= 1.8 V to 2.7 V
3
ELECTRICAL DATA
S3C8478/C8475/P8475
14-6
CPU Clock
2 MHz
Main Oscillator Frequency
(Divided by 4)
1
2
3
4
5
6
7
Supply Voltage (V)
CPU clock = 1/n x oscillator frequency (n = 4, 8 or 64)
4 MHz
6 MHz
8 MHz
10 MHz
12 MHz
1.8 V 2.7 V
Figure 14-2. Operating Voltage Range
Table 14-5. Oscillation Stabilization Time
(T
A
= 40
C + 85
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Main Crystal
f
OSC
> 1.0 kHz;
20
ms
Main Ceramic
Oscillation stabilization occurs when V
DD
is equal
to the minimum oscillator voltage range.
10
ms
External Clock
(Main System)
X
IN
input High and Low width (t
XH
, t
XL
)
25
500
ns
Oscillator
t
WAIT
when released by a reset
(1)
2
16
/f
OSC
ms
Stabilization
Wait Time
t
WAIT
when released by an interrupt
(2)
ms
NOTES:
1.
f
OSC
is the oscillator frequency.
2.
The duration of the oscillator stabilization wait time, t
WAIT
, when it is released by an interrupt is determined by the
settings in the basic timer control register, BTCON.
S3C8478/C8475/P8475
ELECTRICAL DATA
14-7
Table 14-6. UART Timing Characteristics in Mode 0 (10 MHz)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V, Load capacitance = 80 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Serial port clock cycle time
t
SCK
500
t
CPU
6
700
ns
Output data setup to clock rising edge
t
S1
300
t
CPU
5
Clock rising edge to input data valid
t
S2
300
Output data hold after clock rising edge
t
H1
t
CPU
50
t
CPU
Input data hold after clock rising edge
t
H2
0
Serial port clock High, Low level width
t
HIGH,
t
LOW
200
t
CPU
3
400
NOTES:
1.
All timings are in nanoseconds (ns) and assume a 10-MHz CPU clock frequency.
2.
The unit t
CPU
means one CPU clock period.
t
HIGH
0.8 V
DD
0.2 V
DD
t
LOW
t
SCK
Figure 14-3. Waveform for UART Timing Characteristics
ELECTRICAL DATA
S3C8478/C8475/P8475
14-8
NOTE
:
The symbols shown in this diagram are defined as follows:
t
SCK
Serial port clock cycle time
t
S1
Output data setup to clock rising edge
t
S2
Clock rising edge to input data valid
t
H1
Output data hold after clock rising edge
t
H2
Input data hold after clock rising edge
DATA
OUT
D0
D1
D2
D3
D4
D5
D6
D7
t
SCK
SHIFT
CLOCK
t
S1
t
H1
DATA
IN
t
S2
t
H2
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Figure 14-4. A.C. Timing Waveform for the UART Module
S3C8478/C8475/P8475
ELECTRICAL DATA
14-9
Table 14-7. Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data Retention
Supply Voltage
V
DDDR
Stop mode
1.8
5.5
V
Data Retention
Supply Current
I
DDDR
Stop mode, V
DDDR
= 1.8 V
0.1
5
A
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
NOTE: t
WAIT
is the same as 4096 x 16 x 1/f
OSC
.
Execution of
STOP Instrction
RESET
occurs
~ ~
V
DDDR
~ ~
Stop Mode
Oscillation
Stabilzation
Time
Data Retention Mode
t
WAIT
RESET
V
DD
Normal
Operating
Mode
Figure 14-5. Stop Mode Release Timing When Initiated by a Reset
A = 0.2 V
DD
B = 0.4 V
DD
C = 0.6 V
DD
D = 0.8 V
DD
V
DD
V
OUT
V
SS
V
IN
A
B
C
D
Figure 14-6. Schmitt Trigger Input Characteristics
ELECTRICAL DATA
S3C8478/C8475/P8475
14-10
Table 14-8. A/D Converter Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.7 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Total accuracy
V
DD
= 5.12 V
3
LSB
Integral linearity
error
ILE
CPU clock = 8 MHz
AV
REF
= 5.12 V
2
Differential
linearity error
DLE
AV
SS
= 0 V
1
Offset error of
top
EOT
1
3
Offset error of
bottom
EOB
1
2
Conversion
time
(1)
t
CON
f
OSC
= 10 MHz
(3)
20
s
Analog input
voltage
V
IAN
AV
SS
AV
REF
V
Analog input
impedance
R
AN
2
M
ADC reference
voltage
AV
REF
2.5
V
DD
V
ADC reference
ground
AV
SS
V
SS
V
SS
+ 0.3
V
Analog input
current
I
ADIN
AV
CC
= V
CC
= 5 V
10
A
Analog block
current
(2)
I
ADC
AV
CC
= V
CC
= 5 V
1
3
mA
AV
CC
= V
CC
= 3 V
0.5
1.5
AV
CC
= V
CC
= 5 V
power down mode
100
500
nA
NOTES:
1.
"Conversion time" is the time required from the moment a conversion operation starts until it ends.
2.
I
ADC
is operating current during A/D conversion.
3.
f
OSC
is the main oscillator clock.
S3C8478/C8475/P8475
ELECTRICAL DATA
14-11
.
.
.
.
.
11 1111 1111
11 1111 1110
11 1111 1101
V
(K-1)
00 0000 0010
00 0000 0001
00 0000 0000
AV
SS
V
EOB
V
2
V
(K)
V
EOT
AV
REF
Analog Input
Digital Output
1LSB = (V
EOT
-V
EOB
)/1022
DLE(K) = {(V
(K)
-V
(K-1)
)-1LSB}/1LSB
ILE(K) = {V
(K)
-(1LSB x K + V
EOB
)}/1LSB
DLE = MAX{DLE(K)}
ILE = MAX{ILE(K)}
Figure 14-7. Definition of DLE and ILE
S3C8478/C8475/P8475
MECHANICAL DATA
15-1
15
MECHANICAL DATA
OVERVIEW
This section contains the following information about the device package:
-- Package dimensions in millimeters
-- Pad diagram
NOTE: Dimensions are in millimeters.
39.50 MAX
39.10
0.2
0.50
0.1
1.778
(1.77)
0.51 MIN
3.30
0.3
3.50
0.2
5.08 MAX
42-SDIP-600
0-15
1.00
0.1
0.25
+ 0.1
- 0.05
15.24
14.00
0
.2
#42
#22
#21
#1
Figure 15-1. 42-SDIP-600 Package Dimensions
MECHANICAL DATA
S3C8478/C8475/P8475
15-2
44-QFP-1010
#44
NOTE: Dimensions are in millimeters.
10.00
0.2
13.20
0.3
10.00
0.2
13.20
0.3
#1
0.35
+ 0.10
- 0.05
0.80
(1.00)
0.10 MAX
0.80 0.20
0.05 MIN
2.05
0.10
2.30 MAX
0.15
+ 0.10
- 0.05
0-8
Figure 15-2. 44-QFP-1010 Package Dimensions
S3C8478/C8475/P8475
S3P8475 OTP
16-1
16
S3P8475 OTP
OVERVIEW
The S3P8475 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the
S3C8478/C8475 microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is
accessed by serial data format.
The S3P8475 is fully compatible with the S3C8478/C8475, both in function in D.C. electrical characteristics and
in pin configuration. Because of its simple programming requirements, the S3P8475 is ideal as an evaluation
chip for the S3C8478/C8475.
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
SDAT/P4.3
SCLK/P4.2
V
DD
/V
DD
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST
P4.1
P4.0
RESET
RESET
/
RESET
P2.0/
INT0
P2.1/INT1
P2.2/INT2
S3P8475
(42-SDIP)
Top-View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P1.0/T0(CAP/PWM)
P1.1/T1CK
P1.2/T1(CAP/PWM)
P1.3/BUZ
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AV
SS
AV
REF
P2.7/INT7
P2.6/INT6
P2.5/INT5
P2.4/INT4
P2.3/INT3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
NOTE:
The bolds indicate an OTP pin name.
Figure 16-1. S3P8475 Pin Assignments (42-SDIP Package)
S3P8475 OTP
S3C8478/C8475/P8475
16-2
P0.1
P0.0
SDAT/P4.3
SCLK/P4.2
V
DD
/V
DD
V
SS
/V
SS
X
OUT
X
IN
V
PP
/TEST
P4.1
P4.0
S3P8475
(44-QFP)
Top-View
1
2
3
4
5
6
7
8
9
10
11
P4.4
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0/T0(CAP/PWM)
P1.1/T1CK
P1.2/T1(CAP/PWM)
P1.3/BUZ
44
43
42
41
40
39
38
37
36
35
34
P1.4/RxD
P1.5/TxD
P3.7/ADC7
P3.6/ADC6
P3.5/ADC5
P3.4/ADC4
P3.3/ADC3
P3.2/ADC2
P3.1/ADC1
P3.0/ADC0
AV
SS
33
32
31
30
29
28
27
26
25
24
23
RESET
RESET
/
RESET
P2.0/INT0
P2.1/INT1
P2.2/INT2
P2.3/INT3
P2.4/INT4
P2.5/INT5
P2.6/INT6
P2.7/INT7
P4.5
AV
REF
12
13
14
15
16
17
18
19
20
21
22
NOTE:
The bolds indicate an OTP pin name.
Figure 16-2. S3P8475 Pin Assignments (44-QFP Package)
S3C8478/C8475/P8475
S3P8475 OTP
16-3
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P4.3
SDAT
9(3)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P4.2
SCLK
10(4)
I
Serial clock pin. Input only pin.
TEST
V
PP
14(16)
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is aplied, OTP is in reading mode.
(Option)
RESET
RESET
18(12)
I
Chip Initialization
V
DD
/V
SS
V
DD
/V
SS
11(5)/12(6)
Logic power supply pin. V
DD
should be tied to
+5 V during programming.
NOTE: ( ) means 44 QFP package.
Table 16-2. Comparison of S3C8475 and S3C8478/C8475 Features
Characteristic
S3C8475
S3C8478/C8475
Program Memory
16-Kbyte EPROM
8/16-Kbyte mask ROM
Operating Voltage (V
DD
)
1.8 V to 5.5 V
1.8 V to 5.5 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(EA) = 12.5 V
Pin Configuration
42 SDIP/44 QFP
42 SDIP/44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3C8475, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/
MEM
MEM
ADDRESS
(A15A0)
R/W
MODE
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
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