S3C9424/C9428/P9428
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A address/data bus architecture and a large number of bit-configurable I/O ports provide a flexible programming
environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating
modes are included to support real-time operations.
S3C9424/C9428/P9428 MICROCONTROLLER
The S3C9424/C9428/P9428 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87Ri CPU core. The S3C9424/C9428/P9428 is a versatile microcontroller, with its
A/D converter, SIO, IIC and a zero-crossing detection capability it can be used in a wide range of general
purpose applications.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9424/C9428/P9428 have 4K-byte or
8K-byte of program memory on-chip (ROM) and 208-bytes of general purpose register area RAM.
Using the SAM87Ri design approach, the following peripherals were integrated with the SAM87Ri core:
Four configurable I/O ports (24 pins)
Nine interrupt sources with one vector and one interrupt level
Two 8-bit timer/counter with various operating modes
Analog to digital converter with 12 input channels and 10-bit resolution
One synchronous SIO module
One IIC module
Two 12-bit PWM output
The S3C9424/C9428/P9428 microcontroller is ideal for use in a wide range of electronic applications requiring
simple timer/counter, PWM, ADC, SIO, IIC, ZCD and capture functions. S3C9424/C9428/P9428 is available in a
28/32-pin SOP and a 30-pin SDIP package.
OTP
The S3P9428 is an OTP (One Time Programmable) version of the S3C9424/C9428 microcontroller. The
S3P9428 has on-chip 8-K-byte one-time-programmable EPROM instead of masked ROM. The S3P9428 is fully
compatible with the S3C9424/C9428, in function, in D.C. electrical characteristics and in pin configuration.
PRODUCT OVERVIEW
S3C9424/C9428/P9428
1-2
FEATURES
CPU
SAM87RI CPU core
Memory
208-byte general purpose register area (RAM)
4K/8K byte internal program memory (ROM)
Instruction Set
41 instructions
The SAM87RI core provides all the SAM87 core
instruction except the word-oriented instruction,
multiplication, division, and some one-byte
instruction
Instruction Execution Time
375 ns at 16 MHz fosc(minimum)
Interrupts
9 interrupt sources and 1 vector
One interrupt level
General I/O
Four I/O ports (total 24pins)
Bit programmable ports
Serial I/O
One synchronous serial I/O module
Selectable transmit and receive rates
Multi-Master IIC-Bus
Serial peripheral interface
Zero-Crossing Detection Circuit
Zero crossing detection circuit that generates a
digital signal in synchronism with an AC signal
input
Built-in reset Circuit (LVD)
Low voltage detector for safe reset
Timer/Counters
One 8-bit basic timer for watchdog function
One 8-bit timer/counter with three operating
mode
One 8-bit timer/counter
PWM module
12-bit PWM 2-ch (Max: 250KHz)
6-bit base + 6-bit extension frame
One 8-bit timer/counter
A/D Converter
12 analog input pins
10-bit conversion resolution
Buzzer Frequency Range
200 Hz to 20 kHz signal can be generated
Oscillator Freqeuncy
1-MHz to 16-MHz external crystal oscillator
Maximum 16-MHz CPU clock
RC: 4MHz(typ)
Operating Temperature Range
40
C to + 85
C
Operating Voltage Range
3.0 V to 5.5 V (LVD)
1.8 V to 5.5 V (No LVD)
OTP Interface Protocol Spec
Serial OTP
Package Types
S3C9424/C9428
32-pin SOP-450 (3V LVD)
30-pin SDIP-400 (3V LVD)
28-pin SOP-375
S3C9424/C9428/P9428
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Port 0
4K/8K ROM
208-Byte
Register File
Port 1
Timer 1
Basic
Timer
Timer 0
OSC
ADC
BUZ
PWM
P0.0-P0.7
SCK,SO, SI, AD8-AD11
Port 2
Port 3
ZCD
IIC
SIO
P1.0-P1.3
T0, BUZ, INT0, INT1
Port I/O and Interrupt
Control
SAM87RI CPU
X
IN
X
OUT
T0 (CAP)
T0(PWM)
AD0-AD11
P1.1/BUZ
P0.7/PWM0
P1.3/PWM1
P2.0-P2.7
AD0-AD7
P3.0-P3.3
ZCD
P2.7/SCLK
P2.6/SDAT
P0.0/SCK
P0.1/SO
P0.2/SI
Figure 1-1. Block Diagram
PRODUCT OVERVIEW
S3C9424/C9428/P9428
1-4
PIN ASSIGNMENTS
S3C9424/C9428
32-SOP
(Top View)
V
SS
X
IN
X
OUT
TEST
P0.1/SO
P0.0/SCK
RESET
P3.0
P3.2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AV
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
DD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AV
REF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Figure 1-2. Pin Assignment Diagram (32-Pin SOP Package)
S3C9424/C9428/P9428
PRODUCT OVERVIEW
1-5
PIN ASSIGNMENTS (Continued)
V
SS
X
IN
X
OUT
TEST
P0.1/SO
P0.0/SCK
RESET
RESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AV
SS
V
DD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AV
REF
S3C9424/C9428
30-SDIP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Figure 1-3. Pin Assignment Diagram (30-Pin SDIP Package)
S3C9424/C9428
28-SOP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
X
IN
X
OUT
TEST
P0.1/SO
P0.0/SCK
RESET
RESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AV
SS
V
DD
P0.2/SI
P0.3/CLO
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AV
REF
Figure 1-4. Pin Assignment Diagram (28-Pin SOP Package)
PRODUCT OVERVIEW
S3C9424/C9428/P9428
1-6
PIN DESCRIPTIONS
Table 1-1. S3C9424/C9428/P9428 Pin Descriptions
Pin
Names
Pin
Type
Pin Description
Pin
Type
Share
Pins
P0.0-P0.7
I/O
Bit-programmable I/O port for Schmitt trigger input or push-
pull, open-drain output. Pull-up resistors are assignable by
software.
E
E-1
SCK,SO,SI
, CLO,
AD8-AD11
P1.0-P1.3
I/O
Bit-programmable I/O port for Schmitt trigger input or push-
pull output.
Pull-up resistors are assignable by software. Port 1 pins can
also be used as alternative functions.
D
T0/ZCD
BUZ
INT0
INT1
P2.0-P2.7
I/O
Bit-programmable I/O port for Schmitt trigger input or push-
pull, open drain output. Pull up resistors are assignable by
software. Port 2 can also be used as external interrupt, A/D
input.
E-1
AD0-AD7
P3.0-P3.3
O
Push-pull or open-drain output port.
Pull-up resistors are assignable by software.
E-2
X
IN
, X
OUT
Crystal/ceramic, or RC oscillator signal for system clock.
RESET
I
System
RESET
signal input pin.
B
TEST
I
Test signal input pin (for factory use only: must be connected
to V
SS
)
AV
REF
, AV
SS
A/D converter reference voltage input and ground
V
DD
, V
SS
Voltage input pin and ground
SCK
I/O
Serial interface clock input or output
E
P0.0
SO
O
Serial data output
E
P0.1
SI
I
Serial data output
E
P0.2
CLO
O
System clock output port
E
P0.3
SCLK
SDAT
I/O
IIC CLOCK
IIC DATA
E-1
P2.7
P2.6
BUZ
O
200 Hz-20 kHz frequency output for buzzer sound.
D
P1.1
ZCD
I
Zero crossing detector input
D
P1.0
T0
I/O
Timer 0 capture input or 10-bit PWM output
D
P1.0
INT0
INT1
I
External interrupt input
D
P1.2
P1.3
PWM0
PWM1
O
12-bit PWM output
E-1
D
P0.7
P1.3
AD0-AD11
I
A/D converter input
E-1
P2.0-P2.7
P0.4-P0.7
S3C9424/C9428/P9428
PRODUCT OVERVIEW
1-7
PIN CIRCUITS
P-Channel
N-Channel
In
V
DD
Figure 1-5. Pin Circuit Type A
Last Developing: 99.02.02
In
V
DD
Pull-Up
Resistor
Figure 1-6. Pin Circuit Type B
P-Channel
N-Channel
V
DD
Out
Output
DIsable
Data
Figure 1-7. Pin Circuit Type C
I/O
Output
DIsable
Data
Circuit
Type C
Resistor
Enable
V
DD
Data
P-Channel
Pull-up
Resistor
Figure 1-8. Pin Circuit Type D
PRODUCT OVERVIEW
S3C9424/C9428/P9428
1-8
V
DD
Pull-up
Enable
V
DD
I/O
PNE
Output
Disable
Data
P-CH
Pull-up
Resistor
Input
N-CH
Figure 1-9. Pin Circuit Type E
V
DD
Pull-up
Enable
V
DD
I/O
PNE
Output
Disable
Data
P-CH
Pull-up
Resistor
Input
N-CH
Analog Input
Figure 1-10. Pin Circuit Type E-1
V
DD
Pull-up
Enable
V
DD
Out
PNE
Data
47K
Output
Disable
Figure 1-11. Pin Circuit Type E-2
S3C9424/C9428/P9428
ELECTRICAL DATA
16-1
16
ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9424/C9428/P9428 electrical characteristics are presented in tables and graphs:
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- A.C. electrical characteristics
-- Operating Voltage Range
-- Schmitt trigger input characteristics
-- Oscillator characteristics
-- Oscillation stabilization time
-- Data retention supply voltage in Stop mode
-- Stop mode release timing when initiated by a
RESET
-- Power-on
RESET
circuit characteristics
-- A/D converter electrical characteristics
-- Zero-crossing detector
-- Zero Crossing Waveform Diagram
ELECTRICAL DATA
S3C9424/C9428/P9428
16-2
Table 16-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
0.3 to + 6.5
V
Input voltage
V
I
All input ports
0.3 to V
DD
+ 0.3
V
Output voltage
V
O
All output ports
0.3 to V
DD
+ 0.3
V
Output current
I
OH
One I/O pin active
25
mA
high
All I/O pins active
80
Output current
I
OL
One I/O pin active
+ 30
mA
low
Total pin current for ports 1, 2, 3
+ 100
Total pin current for ports 0
+ 200
Operating
temperature
T
A
40 to + 85
C
Storage
temperature
T
STG
65 to + 150
C
S3C9424/C9428/P9428
ELECTRICAL DATA
16-3
Table 16-2. D.C. Electrical Characteristics(30SDIP, 32SOP)
(T
A
= 40
C to + 85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input high
voltage
V
IH1
Ports 0, 1, 2 and
RESET
V
DD
= 3.0 to 5.5 V
0.8 V
DD
V
DD
V
V
IH3
X
IN
and X
OUT
V
DD
0.1
Input low
voltage
V
IL1
Ports 0, 1, 2 and
RESET
V
DD
= 3.0 to 5.5 V
0.2 V
DD
V
V
IL2
X
IN
and X
OUT
0.1
Output high
voltage
V
OH
I
OH
= 10 mA
ports 0-3
V
DD
= 4.5 to 5.5 V
V
DD
1.5
V
DD
0.4
V
Output low
voltage
V
OL
I
OL
= 25 mA
port 0-3
V
DD
= 4.5 to 5.5 V
0.4
2.0
V
Input high
leakage current
I
LIH1
All input pins except
I
LIH2
V
IN
= V
DD
1
A
I
LIH2
X
IN
, X
OUT
V
IN
= V
DD
20
Input low
leakage current
I
LIL1
All input pins except
I
LIL2
and
RESET
V
IN
= 0 V
1
A
I
LIL2
X
IN
, X
OUT
V
IN
= 0 V
20
Output high
leakage current
I
LOH
All output pins
V
OUT
= V
DD
2
A
Output low
leakage current
I
LOL
All output pins
V
OUT
= 0 V
2
A
Pull-up resistor
R
P
V
IN
= 0 V Port 0-2
V
DD
= 5 V
30
47
70
K
RESET
V
DD
= 5 V
100
200
350
Supply current
I
DD1
RUN mode 16-MHz
CPU clock
V
DD
= 4.5 to 5.5 V
11
20
mA
4-MHz CPU clock
V
DD
= 3 V
1.5
4
I
DD2
Idle mode 16-MHz
CPU clock
V
DD
= 4.5 to 5.5 V
3
8
4-MHz CPU clock
V
DD
= 3.3 V
0.5
2
I
DD3
Stop mode
V
DD
= 4.5 to 5.5 V
65
100
A
V
DD
= 3.3 V
45
80
NOTE: D.C. electrical values for Supply current (I
DD1
to I
DD3
) do not include current drawn through internal pull-up
resisters, output port drive current, ZCD and ADC.
ELECTRICAL DATA
S3C9424/C9428/P9428
16-4
Table 16-3. D.C. Electrical Characteristics (28SOP)
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input high
voltage
V
IH1
Ports 0, 1, 2 and
RESET
V
DD
= 1.8 to 5.5 V
0.8 V
DD
V
DD
V
V
IH3
X
IN
and X
OUT
V
DD
0.1
Input low
voltage
V
IL1
Ports 0, 1, 2 and
RESET
V
DD
= 1.8 to 5.5 V
0.2 V
DD
V
V
IL2
X
IN
and X
OUT
0.1
Output high
voltage
V
OH
I
OH
= 10 mA
ports 0-3
V
DD
= 4.5 to 5.5 V
V
DD
1.0
V
DD
0.4
V
Output low
voltage
V
OL
I
OL
= 25 mA
port 0-3
V
DD
= 4.5 to 5.5 V
0.4
2.0
V
Input high
leakage current
I
LIH1
All input pins except
I
LIH2
V
IN
= V
DD
1
A
I
LIH2
X
IN
, X
OUT
V
IN
= V
DD
20
Input low
leakage current
I
LIL1
All input pins except
I
LIL2
and
RESET
V
IN
= 0 V
1
A
I
LIL2
X
IN
, X
OUT
V
IN
= 0 V
20
Output high
leakage current
I
LOH
All output pins
V
OUT
= V
DD
2
A
Output low
leakage current
I
LOL
All output pins
V
OUT
= 0 V
2
A
Pull-up resistor
R
P
V
IN
= 0 V Port 0-2
V
DD
= 5 V
30
47
70
K
RESET
V
DD
= 5 V
100
200
350
Supply current
I
DD1
RUN mode 16-MHz
CPU clock
V
DD
= 4.5 to 5.5 V
11
20
mA
3-MHz CPU clock
V
DD
= 1.8 to 2.2 V
1
3
I
DD2
Idle mode 16-MHz
CPU clock
V
DD
= 4.5 to 5.5 V
3
9
3-MHz CPU clock
V
DD
= 1.8 to 2.2 V
0.3
1.0
I
DD3
Stop mode
V
DD
= 4.5 to 5.5 V
0.1
5
A
V
DD
= 3 V
V
DD
= 1.8 to 2.2 V
NOTE: D.C. electrical values for Supply current (I
DD1
to I
DD3
) do not include current drawn through internal pull-up
resisters, output port drive current, ZCD and ADC.
S3C9424/C9428/P9428
ELECTRICAL DATA
16-5
Table 16-4. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt input
high, low width
t
INTH
,
t
INTL
Port 1v(INT0, INT1)
V
DD
= 5V
10%
200
ns
RESET
input
low width
t
RSL
Input
V
DD
= 5V
10%
1
us
0.8 V
DD
0.2 V
DD
t
INTL
t
INTH
t
RSL
1/t
CPU
NOTE:
The unit tcpu means one CPU clock period.
Figure 16-1. Input Timing Measurement Points
ELECTRICAL DATA
S3C9424/C9428/P9428
16-6
CPU Clock
16MHz
8MHz
4MHz
3MHz
2MHz
1MHz
1
2
3
4
5
6
7
2.7
5.5
Supply Voltage (V)
1.8
4.5
Figure 16-2. Operating Voltage Range (KS86C4204/C4208)
0.3 V
DD
A = 0.2 V
DD
B = 0.4 V
DD
C = 0.6 V
DD
D = 0.8 V
DD
V
OUT
A
0.7 V
DD
V
DD
V
SS
B
C
D
V
IN
Figure 16-3. Schimtt Trigger Input Characteristic Diagram
S3C9424/C9428/P9428
ELECTRICAL DATA
16-7
Table 16-5. Oscillator Characteristics (30SDIP, 32SOP)
(T
A
= 40
C to + 85
C)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Main crystal or
ceramic
X
IN
X
OUT
C1
C2
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 4.5 V
1
1
16
8
MHz
External clock
(Main system)
X
IN
X
OUT
V
DD
= 4.5 to 5.5 V
V
DD
= 3.0 to 4.5 V
1
1
16
8
RC oscillator
X
IN
X
OUT
R
V
DD
= 4.75 to 5.25 V
Tolerance: 10%
4
Table 16-6. Oscillation Stabilization Time (28SOP)
(T
A
= 40
C to + 85
C)
Oscillator
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Main crystal or
ceramic
X
IN
X
OUT
C1
C2
V
DD
= 4.5 to 5.5 V
V
DD
= 2.7 to 4.5 V
V
DD
= 1.8 to 2.7 V
1
1
1
16
8
3
MHz
External clock
(Main system)
X
IN
X
OUT
V
DD
= 4.5 to 5.5 V
V
DD
= 2.7 to 4.5 V
VDD = 1.8 to 2.7 V
1
1
1
16
8
3
RC oscillator
X
IN
X
OUT
R
V
DD
= 4.75 to 5.25 V
Tolerance: 10%
4
ELECTRICAL DATA
S3C9424/C9428/P9428
16-8
Table 16-7. Oscillation Stabilization Time
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
Main crystal
fosc > 1.0 MHz
20
ms
Main ceramic
Oscillation stabilization occurs when V
DD
is equal
to the minimum oscillator voltage range.
10
External clock
(main system)
X
IN
input high and low width (t
XH
, t
XL
)
25
500
ns
Oscillator
stabilization
t
WAIT
when released by a reset
(1)
2
16
/fosc
ms
wait time
t
WAIT
when released by an interrupt
(2)
NOTES:
1.
fosc is the oscillator frequency.
2.
The duration of the oscillator stabilization wait time, t
WAIT
, when it is released by an interrupt is determined by the
setting in the basic timer control register, BTCON.
S3C9424/C9428/P9428
ELECTRICAL DATA
16-9
Table 16-8. Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C, V
DD
= 1.8 V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention
supply voltage
V
DDDR
Stop mode
1.8
5.5
V
Data retention
supply current
I
DDDR
Stop mode; V
DDDR
= 1.8 V
0.1
5
A
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Data Retention Mode
~
~ ~
V
DDDR
Execution Of
Stop Instrction
V
DD
Normal
Operating
Mode
Oscillation
Stabilization Time
~
Stop Mode
Internal
RESET
Operation
RESET
t
WAIT
NOTE:
t
WAIT
is the same as 4096 x 16 x 1/fosc
0.8 V
DD
0.2 V
DD
Figure 16-4. Stop Mode Release Timing When Initiated by a
RESET
RESET
ELECTRICAL DATA
S3C9424/C9428/P9428
16-10
Table 16-9. Power-on
RESET
RESET
Circuit Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 3.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Power-on reset
voltage high
V
DDH
3.0
5.5
V
Power-on reset
voltage low
V
DDL
0
2.6
3.0
V
Power supply
voltage rise time
t
r
10
(1)
us
Power supply
voltage off time
t
off
0.5
s
Power-on reset circuit
I
DDPR
V
DD
= 5 V
10%
65
100
A
cunsumption current
(2)
V
DD
= 3.3 V
45
80
NOTES:
1.
216/fx (= 6.55 ms at fx = 10 MHz)
2.
Current consumed when power-on reset circuit is provided internally.
V
DD
V
DDH
V
DDL
t
off
t
r
Figure16-5. Power-on
RESET
RESET
Timing
S3C9424/C9428/P9428
ELECTRICAL DATA
16-11
Table 16-10. A/D Converter Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 1.8/3.0 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Total accuracy
V
DD
= 5.12 V
CPU clock = 10 MHz
AV
REF
= 5.12 V
AV
SS
= 0 V
3
LSB
Integral linearity error
ILE
"
2
LSB
Differential linearity error
DLE
"
1
Offset error of top
EOT
"
1
3
Offset error of bottom
EOB
"
1
2
Conversion time
(1)
t
CON
fosc = 10 MHz
20
s
Analog input voltage
V
IAN
AV
SS
AV
REF
V
Analog input impedance
R
AN
2
M
ADC reference voltage
AV
REF
2.5
V
DD
V
ADC reference ground
AV
SS
V
SS
V
SS
+
0.3
V
Analog input current
I
ADIN
AV
REF
= V
DD
= 5 V
10
A
ADC block
I
ADC
AV
REF
= V
DD
= 5 V
1
3
mA
current
(2)
AV
REF
= V
DD
= 3 V
0.5
1.5
AV
REF
= V
DD
= 5 V
Power down mode
100
500
nA
NOTES:
1.
`Conversion time' is the time required from the moment a conversion operation starts until it ends.
2.
I
ADC
is operating current during A/D conversion.
11 1111 1111
11 1111 1110
11 1111 1101
.
.
.
.
.
.
.
00 0000 0010
00 0000 0001
00 0000 0000
V
EOB
AV
SS
V
2
V
(K-1)
V
(K)
V
EOT
AV
REF
Analog Input
Digital Output
Figure 16-6. Definition of DLE and ILE
ELECTRICAL DATA
S3C9424/C9428/P9428
16-12
Table 16-11. Zero Crossing Detector
(T
A
= 40
C to + 85
C, V
DD
= 4.5 V to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Zero-crossing
detection input
voltage
V
ZC
AC connection
c = 0.1
F
1.0
3.0
Vp-p
Zero-crossing
detection accuracy
V
AZC
f
ZC
= 60 Hz
(sine wave)
V
DD
= 5 V
f
OSC
= 10 MHz
150
mV
Zero-crossing
detection input
frequency
f
ZC
40
200
Hz
1/fzc
V
AZC
ZCINT
AC input
V
AZ(P-P)
Figure 16-7. Zero Crossing Waveform Diagram
S3C9424/C9428/P9428
MECHANICAL DATA
17-1
17
MECHANICAL DATA
OVERVIEW
The S3C9424/C9428 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package
(32-SOP-450A) and a 28-pin SOP package (28-SOP-375). Package dimensions are shown in Figures 17-1, 17-2,
and 17-3
NOTE: Dimensions are in millimeters.
27.88MAX
27.48
0.2
1.778
(1.30)
0.51 MIN
3.30
0.3
3.81
0.2
5.08 MAX
0-15
1.12
0.1
0.25
+ 0.1
- 0.05
10.16
#30
#16
#15
#1
30-SDIP-400
0.56
0.1
8.94
0.2
Figure 17-1. 30-Pin SDIP Package Dimensions
MECHANICAL DATA
S3C9424/C9428/P9428
17-2
32-SOP-450A
#1
#16
#17
#32
2.40 MAX
(0.43)
0.05 MIN
1.27
NOTE: Dimensions are in millimeters
19.90
0.2
0.40
0.1
12.00
0
.3
2.00
0
.2
11.43
0-8
8.34
0
.2
0.78
0
.2
0.20
+ 0.1
- 0.05
Figure 17-2. 32-SOP-450A Package Dimensions
S3C9424/C9428/P9428
MECHANICAL DATA
17-3
28-SOP-375
#1
#14
#15
#28
NOTE: Dimensions are in millimeters
10.45
0
.3
7.70
0
.2
0.60
0
.2
0.15
+ 0.10
- 0.05
2.50 MAX
(0.56)
0.05 MIN
17.62
0.2
0.41
0.1
2.15
0
.1
18.02 MAX
1.27
9.53
8
Figure 17-3. 28-SOP-375 Package Dimensions
S3C9424/C9428/P9428
S3P9428 OTP
18-1
18
S3P9428 OTP
OVERVIEW
The S3P9428 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the
S3C9424/C9428 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9428 is fully compatible with the S3C9424/C9428, both in function and in pin configuration. Because of
its simple programming requirements, the S3P9428 is ideal for use as an evaluation chip for the
S3C9424/C9428.
NOTE:
The bolds indicate an OTP pin name.
V
SS
X
IN
X
OUT
TEST/V
PP
P0.1/SO
P0.0/SCK
RESET
RESET
P3.0
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AV
SS
V
DD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AV
REF
S3P9428
30-SDIP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Figure 18-1. Pin Assignment Diagram (30-Pin SDIP Package)
S3P9428 OTP
S3C9424/C9428/P9428
18-2
NOTE:
The bolds indicate an OTP pin name.
S3P9428
32-SOP
(Top View)
V
SS
X
IN
X
OUT
TEST/V
PP
P0.1/SO
P0.0/SCK
RESET
RESET
P3.0
P3.2
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AV
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
DD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P3.1
P3.3
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AV
REF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Figure 18-2. Pin Assignment Diagram (32-Pin SOP Package)
NOTE:
The bolds indicate an OTP pin name.
S3P9428
28-SOP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
SS
X
IN
X
OUT
TEST/V
PP
P0.1/SO
P0.0/SCK
RESET
RESET
P2.0/AD0
P2.1/AD1
P2.2/AD2
P2.3/AD3
P2.4/AD4
P2.5/AD5
AV
SS
V
DD
P0.2/SI/SCL
P0.3/CLO/SDA
P0.4/AD8
P0.5/AD9
P0.6/AD10
P0.7/AD11/PWM0
P1.0/T0/ZCD
P1.1/BUZ
P1.2/INT0
P1.3/INT1/PWM1
P2.7/AD7/SCLK
P2.6/AD6/SDAT
AV
REF
Figure 18-3. Pin Assignment Diagram (28-Pin SOP Package)
S3C9424/C9428/P9428
S3P9428 OTP
18-3
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.3
SDAT
S3P9428
- 30 SDIP: 28
- 32 SOP: 30
I/O
Serial data pin (output when reading, Input
when writing) Input and push-pull output
port can be assigned
P0.2
SCLK
S3P9428
- 30 SDIP: 29
- 32 SOP: 31
I
Serial clock pin (input only pin)
TEST
V
PP
(TEST)
4
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. (Option)
RESET
RESET
7
I
Chip Initialization
V
DD
/V
SS
V
DD
/V
SS
S3P9428
- 30 SDIP: 30/1
- 32 SOP: 32/1
I
Logic power supply pin.
Table 18-2. Comparison of S3P9428 and S3C9424/C9428 Features
Characteristic
S3P9428
S3C9424/C9428
Program Memory
8-Kbyte EPROM
4/8-Kbyte mask ROM
Operating Voltage (V
DD
)
3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
3.0 V to 5.5 V (28 SOP: 1.8 V to 5.5)
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST) = 12.5 V
Pin Configuration
30 SDIP/32 SOP/28SOP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the S3P9428, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
V
DD
V
pp
(TEST)
REG/
MEM
MEM
ADDRESS
(A15-A0)
R/W
MODE
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
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