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ADC <op1>, <op2>

<op1>:

GPR

<op2>: adr:8, GPR

Operation:

<op1>

<op1> + <op2> + C

ADC adds the values of <op1> and <op2> and carry (C) and stores the result back into <op1>

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

ADC

R0, 80h

// If eid = 0, R0

R0 + DM[0080h] + C

// If eid = 1, R0

R0 + DM[IDH:80h] + C

ADC

R0,

R0 + R1 + C

ADD

R0,

ADC

R1,

In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of "ADD R0, R2" is not zero, Z flag can be set to `1' if the result
of "ADC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit addition, take care of the change of Z flag.

Format:

ADD <op1>, <op2>

<op1>:

GPR

<op2>: adr:8, #imm:8, GPR, @idm

Operation:

<op1>

ADD adds the values of <op1> and <op2> and stores the result back into <op1>.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

Given: IDH:IDL0 = 80FFh, eid = 1

ADD

R0, 80h

// R0

R0 + DM[8080h]

ADD

R0, #12h

// R0

R0 + 12h

ADD

R1, R2

// R1

R1 + R2

ADD

R0, @ID0 + 2

// R0

R0 + DM[80FFh], IDH

81h, IDL0

01h

ADD

R0, @[ID0 � 3]

// R0

R0 + DM[80FCh], IDH

80h, IDL0

FCh

ADD

R0, @[ID0 + 2]!

// R0

R0 + DM[8101h], IDH

80h, IDL0

FFh

ADD

R0, @[ID0 � 2]!

// R0

R0 + DM[80FDh], IDH

80h, IDL0

FFh

In the last two instructions, the value of IDH:IDL0 is not changed. Refer to Table 7-5 for more
detailed explanation about this addressing mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)

Format:

AND <op1>, <op2>

<op1>:

GPR

<op2>: adr:8, #imm:8, GPR, @idm

Operation:

<op1>

AND performs bit-wise AND on the values in <op1> and <op2> and stores the result in <op1>.

Flags:

Z: set if result is zero. Reset if not.

N: set if the MSB of result is 1. Reset if not.

Example:

Given: IDH:IDL0 = 01FFh, eid = 1

AND

R0,

7Ah

R0 & DM[017Ah]

AND

R1,

#40h

R1 & 40h

AND

R0,

R0 & R1

AND

R1, @ID0 + 3

// R1

R1 & DM[01FFh], IDH:IDL0

0202h

AND

R1, @[ID0 � 5]

// R1

R1 & DM[01FAh], IDH:IDL0

01FAh

AND

R1, @[ID0 + 7]!

// R1

R1 & DM[0206h], IDH:IDL0

01FFh

AND

R1, @[ID0 � 2]!

// R1

R1 & DM[01FDh], IDH:IDL0

01FFh

In the first instruction, if eid bit in SR0 is zero, register R0 has garbage value because data memory
DM[0051h-007Fh] are not mapped in S3CB205/FB205. In the last two instructions, the value of
IDH:IDL0 is not changed. Refer to Table 7-5 for more detailed explanation about this addressing
mode.
idm = IDx+offset:5, [IDx-offset:5], [IDx+offset:5]!, [IDx-offset:5]! (IDx = ID0 or ID1)

Format:

AND SR0, #imm:8

Operation:

SR0

SR0 & imm:8

AND SR0 performs the bit-wise AND operation on the value of SR0 and imm:8 and stores the

result in SR0.

Flags:

�

Example:

Given: SR0 = 11000010b

nIE

EQU ~02h

nIE0

EQU ~40h

nIE1

EQU ~80h

AND SR0, #nIE | nIE0 | nIE1

AND SR0, #11111101b

In the first example, the statement "AND SR0, #nIE|nIE0|nIE1" clear all of bits of the global interrupt,
interrupt 0 and interrupt 1. On the contrary, cleared bits can be set to `1' by instruction "OR SR0,
#imm:8". Refer to instruction OR SR0 for more detailed explanation about enabling bit.

In the second example, the statement "AND SR0, #11111101b" is equal to instruction DI, which is
disabling interrupt globally.

Format:

BANK #imm:2

Operation:

SR0[4:3]

imm:2

Flags:

�

For explanation of the CalmRISC banked register file and its usage, please refer to chapter 3.

Example:

BANK

// Select register bank 1

R0, #11h

// Bank1's R0

11h

BANK

// Select register bank 2

R1, #22h

// Bank2's R1

22h

Format:

BITC adr:8.bs

bs: 3-digit bit specifier

Operation:

((adr:8) ^ (2**bs)) if (TF == 0)

(adr:8)

((adr:8) ^ (2**bs)) if (TF == 1)

BITC complements the specified bit of a value read from memory and stores the result in R3 or

back into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.

Flags:

Z: set if result is zero. Reset if not.

Since the destination register R3 is fixed, it is not specified explicitly.

Example:

Given: IDH = 01, DM[0180h] = FFh, eid = 1

BMC

BITC 80h.0

FEh, DM[0180h] = FFh

BMS

BITC 80h.1

DM[0180h]

FDh

Format:

BITR adr:8.bs

bs: 3-digit bit specifier

Operation:

((adr:8) & ((11111111)

- (2**bs))) if (TF == 0)

(adr:8)

((adr:8) & ((11111111)

- (2**bs))) if (TF == 1)

BITR resets the specified bit of a value read from memory and stores the result in R3 or back

into memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.

Flags:

Z: set if result is zero. Reset if not.

Since the destination register R3 is fixed, it is not specified explicitly.

Example:

Given: IDH = 01, DM[0180h] = FFh, eid = 1

BMC

BITR 80h.1

FDh, DM[0180h] = FFh

BMS

BITR 80h.2

DM[0180h]

FBh

Format:

BITS adr:8.bs

bs: 3-digit bit specifier.

Operation:

((adr:8) | (2**bs)) if (TF == 0)

(adr:8)

((adr:8) | (2**bs)) if (TF == 1)

BITS sets the specified bit of a value read from memory and stores the result in R3 or back into

memory, depending on the value of TF. TF is set or clear by BMS/BMC instruction.

Flags:

Z: set if result is zero. Reset if not.

Since the destination register R3 is fixed, it is not specified explicitly.

Example:

Given: IDH = 01, DM[0180h] = F0h, eid = 1

BMC

BITS 80h.1

0F2h, DM[0180h] = F0h

BMS

BITS 80h.2

DM[0180h]

F4h

Format:

BITT adr:8.bs

bs: 3-digit bit specifier.

Operation:

~((adr:8) & (2**bs))

BITT tests the specified bit of a value read from memory.

Flags:

Z: set if result is zero. Reset if not.

Example:

Given: DM[0080h] = F7h, eid = 0

BITT

80h.3

// Z flag is set to `1'

Z, %1

// Jump to label %1 because condition is true.

�

BITS 80h.3

NOP

�

!" #

Format:

BMS/BMC

Operation:

BMC/BMS clears (sets) the TF bit.

0 if BMC

1 if BMS

TF is a single bit flag which determines the destination of bit operations, such as BITC, BITR, and
BITS.

Flags:

�

BMC/BMS are the

only instructions that modify the content of the TF bit.

Example:

BMS

// TF

BITS

81h.1

BMC

BITR

81h.2

R0,

$"$ %$&$'

Format:

CALL cc:4, imm:20

CALL

imm:12

2(0G33@ / #7;'0G33

0G33@#A '-/0G33 30G33#A

Example:

CALL

C, Wait

// HS[sptr][15:0]

current PC + 2, sptr

sptr + 2

�

// 2-word instruction

�

CALL

0088h

// HS[sptr][15:0]

current PC + 1, sptr

sptr + 2

�

// 1-word instruction

�

Wait: NOP

// Address at 0088h

NOP

RET

$"$

Format:

CALLS imm:12

Operation:

HS[sptr][15:0]

current PC + 1, sptr

sptr + 2 if the program size is less than 64K word.

HS[sptr][19:0]

current PC + 1, sptr

sptr + 2 if the program size is equal to or over 64K word.

PC[11:0]

imm:12

CALLS unconditionally calls a subroutine residing at the address specified by imm:12.

Flags:

�

Example:

CALLS Wait

�

Wait: NOP

NOP

RET

Because this is a 1-word instruction, the saved returning address on stack is (PC + 1).

(

Format:

CLD imm:8, <op>

<op>:

GPR

Operation:

(imm:8)

<op>

CLD loads the value of <op> into (imm:8), where imm:8 is used to access the external

coprocessor's address space.

Flags:

�

Example:

AH EQU

00h

AL EQU

01h

BH EQU

02h

BL EQU

03h

�

CLD

AH, R0

// A[15:8]

CLD

AL,

A[7:0]

CLD

BH,

B[15:8]

CLD

BL,

B[7:0]

The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.

Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.

( )

Format:

CLD <op>, imm:8

<op>: GPR

Operation:

<op>

(imm:8)

CLD loads a value from the coprocessor, whose address is specified by imm:8.

Flags:

Z: set if the loaded value in <op1> is zero. Reset if not.

N: set if the MSB of the loaded value in <op1> is 1. Reset if not.

Example:

AH EQU

00h

AL EQU

01h

BH EQU

02h

BL EQU

03h

�

CLD

R0, AH

// R0

A[15:8]

CLD

R1,

A[7:0]

CLD

R2,

B[15:8]

CLD

R3,

B[7:0]

The registers A[15:0] and B[15:0] are Arithmetic Unit (AU) registers of MAC816.

Above instructions generate SYSCP[7:0], nCLDID and CLDWR signals to access MAC816.

Format:

COM <op>

<op>:

GPR

Operation:

<op>

~<op>

COM takes the bit-wise complement operation on <op> and stores the result in <op>.

Flags:

Z: set if result is zero. Reset if not.

N: set if the MSB of result is 1. Reset if not.

Example:

Given: R1 = 5Ah

COM R1

A5h, N flag is set to `1'

Format:

COM2 <op>

<op>:

GPR

Operation:

<op>

~<op> + 1

COM2 computes the 2's complement of <op> and stores the result in <op>.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: set if result is negative.

Example:

Given: R0 = 00h, R1 = 5Ah

COM2

00h, Z and C flags are set to `1'.

COM2

A6h, N flag is set to `1'.

Format:

COMC <op>

<op>:

GPR

Operation:

<op>

~<op> + C

COMC takes the bit-wise complement of <op>, adds carry and stores the result in <op>.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.

Example:

If register pair R1:R0 is a 16-bit number, then the 2's complement of R1:R0 can be obtained by

COM2 and COMC as following.

COM2

COMC

Note that Z flag do not exactly reflect result of 16-bit operation. For example, if 16-bit register pair
R1: R0 has value of FF01h, then 2's complement of R1: R0 is made of 00FFh by COM2 and COMC.
At this time, by instruction COMC, zero (Z) flag is set to `1' as if the result of 2's complement for
16-bit number is zero. Therefore when programming 16-bit comparison, take care of the change of
Z flag.

Format:

COP #imm:12

Operation:

COP passes imm:12 to the coprocessor by generating SYSCP[11:0] and nCOPID signals.

Flags:

�

Example:

COP

#0D01h

// generate 1 word instruction code(FD01h)

COP

#0234h

// generate 1 word instruction code(F234h)

The above two instructions are equal to statement "ELD A, #1234h" for MAC816 operation. The
microcode of MAC instruction "ELD A, #1234h" is "FD01F234", 2-word instruction. In this, code `F'
indicates `COP' instruction.

Format:

CP <op1>, <op2>

<op1>:

GPR

<op2>: adr:8, #imm:8, GPR, @idm

Operation:

<op1> + ~<op2> + 1

CP compares the values of <op1> and <op2> by subtracting <op2> from <op1>. Contents of <op1>
and <op2> are not changed.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero (i.e., <op1> and <op2> are same). Reset if not.

V: set if overflow is generated. Reset if not.

N: set if result is negative. Reset if not.

Example:

Given: R0 = 73h, R1 = A5h, IDH:IDL0 = 0123h, DM[0123h] = A5, eid = 1

R0, 80h

// C flag is set to `1'

R0, #73h

// Z and C flags are set to `1'

R0, R1

// V flag is set to `1'

R1, @ID0

// Z and C flags are set to `1'

R1, @[ID0 � 5]

R2, @[ID0 + 7]!

R2, @[ID0 � 2]!

Format:

CPC <op1>, <op2>

<op1>:

GPR

<op2>: adr:8, GPR

Operation:

<op1>

<op1> + ~<op2> + C

CPC compares <op1> and <op2> by subtracting <op2> from <op1>. Unlike CP, however, CPC

adds (C - 1) to the result. Contents of <op1> and <op2> are not changed.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: set if result is negative. Reset if not.

Example:

If register pair R1:R0 and R3:R2 are 16-bit signed or unsigned numbers, then use CP and CPC

to compare two 16-bit numbers as follows.

R0, R1

CPC

R2, R3

Because CPC considers C when comparing <op1> and <op2>, CP and CPC can be used in pair to
compare 16-bit operands. But note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit comparison, take care of the change of Z flag.

Format:

DEC <op>

<op>:

GPR

Operation:

<op>

<op> + 0FFh

DEC decrease the value in <op> by adding 0FFh to <op>.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: set if result is negative. Reset if not.

Example:

Given: R0 = 80h, R1 = 00h

DEC

7Fh, C, V and N flags are set to `1'

DEC

FFh, N flags is set to `1'

Format:

DECC <op>

<op>:

GPR

Operation:

<op>

<op> + 0FFh + C

DECC decrease the value in <op> when carry is not set. When there is a carry, there is no

change in the value of <op>.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: set if result is negative. Reset if not.

Example:

If register pair R1:R0 is 16-bit signed or unsigned number, then use DEC and DECC to
decrement 16-bit number as follows.

DEC R0

DECC

Note that zero (Z) flag do not exactly reflect result of 16-bit operation. Therefore when programming
16-bit decrement, take care of the change of Z flag.

"&$%$&$'

Format:

Operation:

Disables interrupt globally. It is same as "AND SR0, #0FDh" .

instruction

sets bit1 (ie: global interrupt enable) of SR0 register to "0"

Flags:

�

Example:

Given: SR0 = 03h

SR0

SR0 & 11111101b

DI instruction clears SR0[1] to `0', disabling interrupt processing.

- "&$%$&$'

Format:

Operation:

Enables interrupt globally. It is same as "OR SR0, #02h" .

instruction

sets the bit1 (ie: global interrupt enable) of SR0 register to "1"

Flags:

�

Example:

Given: SR0 = 01h

SR0

SR0 | 00000010b

The statement "EI" sets the SR0[1] to `1', enabling all interrupts.

&. %$&$'

Format:

IDLE

Operation:

The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue.
Idle mode can be released by an interrupt or reset operation.
The IDLE instruction is a pseudo instruction. It is assembled as "SYS #05H", and this generates the
SYSCP[7-0] signals. Then these signals are decoded and the decoded signals

execute the idle

operation.

Flags:

�

(23? *% ( 23?

Example:

IDLE

NOP

�

The IDLE instruction stops the CPU clock but not the system clock.

Format:

INC <op>

<op>:

GPR

Operation:

<op>

<op> + 1

INC increase the value in <op>.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.

Example:

Given: R0 = 7Fh, R1 = FFh

INC

80h, V flag is set to `1'

INC

00h, Z and C flags are set to `1'

Format:

INCC <op>

<op>:

GPR

Operation:

<op>

<op> + C

INCC increase the value of <op> only if there is carry. When there is no carry, the value of

<op> is not changed.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

If register pair R1:R0 is 16-bit signed or unsigned number, then use INC and INCC to increment
16-bit number as following.

INC

INCC

Assume R1:R0 is 0010h, statement "INC R0" increase R0 by one without carry and statement
"INCC R1" set zero (Z) flag to `1' as if the result of 16-bit increment is zero. Note that zero (Z) flag do
not exactly reflect result of 16-bit operation. Therefore when programming 16-bit increment, take
care of the change of Z flag.

$)&$/ 0

Format:

IRET

Operation:

HS[sptr - 2], sptr

sptr - 2

IRET pops the return address (after interrupt handling) from the hardware stack and assigns it to

PC. The ie (i.e., SR0[1]) bit is set to allow further interrupt generation.

Flags:

�

The program size (indicated by the nP64KW signal) determines which portion of PC is updated.
When the program size is less than 64K word, only the lower 16 bits of PC are updated
(i.e., PC[15:0]

HS[sptr � 2]).

When the program size is 64K word or more, the action taken is PC[19:0]

HS[sptr - 2].

Example:

SF_EXCEP:

NOP

// Stack full exception service routine

�

IRET

1$2

Format:

JNZD <op>, imm:8

<op>: GPR (bank 3's GPR only)

imm:8 is an signed number

Operation:

PC[delay slot] - 2's complement of imm:8

<op>

<op> - 1

JNZD performs a backward PC-relative jump if <op> evaluates to be non-zero. Furthermore, JNZD
decrease the value of <op>. The instruction immediately following JNZD (i.e., in delay slot) is
always executed, and this instruction must be 1 cycle instruction.

Flags:

�

Typically, the delay slot will be filled with an instruction from the loop body. It is noted, however, that
the chosen instruction should be "dead" outside the loop for it executes even when the loop is exited
(i.e., JNZD is not taken).

Example:

Given: IDH = 03h, eid = 1

BANK

R0, #0FFh

// R0 is used to loop counter

R1, #0

LD IDL0,

JNZD

R0, %B1

// If R0 of bank3 is not zero, jump to %1.

@ID0, R1

// Clear register pointed by ID0

�

This example can be used for RAM clear routine. The last instruction is executed even if the loop is
exited.

1$%$&$'

Format:

JP cc:4 imm:20

JP cc:4 imm:9

Operation:

If JR can access the target address, JP command is assembled to JR (1 word instruction) in linking
time, else the JP is assembled to LJP (2 word instruction) instruction.
There are 16 different conditions that can be used, as described in table 7-6.

Example:

R0, #10h

// Assume address of label %1 is 020Dh

�

Z, %B1

// Address at 0264h

C, %F2

// Address at 0265h

�

R1, #20h

// Assume address of label %2 is 089Ch

�

In the above example, the statement "JP Z, %B1" is assembled to JR instruction. Assuming that
current PC is 0264h and condition is true, next PC is made by PC[11:0]

PC[11:0] + offset, offset

value is "64h + A9h" without carry. `A9' means 2's complement of offset value to jump backward.
Therefore next PC is 020Dh. On the other hand, statement "JP C, %F2" is assembled to LJP
instruction because offset address exceeds the range of imm:9.

1$ 3

Format:

JR cc:4 imm:9

cc:4: 4-bit condition code

Operation:

PC[11:0]

PC[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign-extended

to 12 bits when added to PC.
There are 16 different conditions that can be used, as described in table 7-6.

Flags:

�

Unlike LJP, the target address of JR is PC-relative. In the case of JR, imm:9 is added to PC to
compute the actual jump address, while LJP directly jumps to imm:20, the target.

Example:

Z, %1

// Assume current PC = 1000h

�

R0, R1

// Address at 10A5h

�

After the first instruction is executed, next PC has become 10A5h if Z flag bit is set to `1'. The range
of the relative address is from +255 to �256 because imm:9 is signed number.

$"$

Format:

LCALL cc:4, imm:20

Operation:

HS[sptr][15:0]

current PC + 2, sptr

sptr + 2, PC[15:0]

imm[15:0] if the condition holds

and the program size is less than 64K word.

HS[sptr][19:0]

current PC + 2, sptr

sptr + 2, PC[19:0]

imm:20 if the condition holds and

the program size is equal to or over 64K word.

PC[11:0]

PC[11:0] + 2 otherwise.

LCALL instruction is used to call a subroutine whose starting address is specified by imm:20.

Flags:

�

Example:

LCALL L1

LCALL

Label L1 and L2 can be allocated to the same or other section. Because this is a 2-word instruction,
the saved returning address on stack is (PC + 2).

( 4

Format:

LD adr:8, <op>

<op>:

GPR

Operation:

DM[00h:adr:8]

<op> if eid = 0

DM[IDH:adr:8]

<op> if eid = 1

LD adr:8 loads the value of <op> into a memory location. The memory location is determined by

the eid bit and adr:8.

Flags:

�

Example:

Given: IDH = 01h

80h,

If eid bit of SR0 is zero, the statement "LD 80h, R0" load value of R0 into DM[0080h], else eid bit

was set to `1', the statement "LD 80h, R0" load value of R0 into DM[0180h]

( 4&5

Format:

LD @idm, <op>

<op>:

GPR

Operation:

(@idm)

<op>

LD @idm loads the value of <op> into the memory location determined by @idm. Details of the
@idm format and how the actual address is calculated can be found in chapter 2.

Flags:

�

Example:

Given R0 = 5Ah, IDH:IDL0 = 8023h, eid = 1

@ID0, R0

// DM[8023h]

5Ah

@ID0 + 3, R0

// DM[8023h]

5Ah, IDL0

26h

@[ID0-5], R0

// DM[801Eh]

5Ah, IDL0

1Eh

@[ID0+4]!, R0

// DM[8027h]

5Ah, IDL0

23h

@[ID0-2]!, R0

// DM[8021h]

5Ah, IDL0

23h

( 0

Format:

LD <op1>, <op2>

<op1>:

GPR

<op2>: GPR, SPR, adr:8, @idm, #imm:8

Operation:

<op1>

<op2>

LD loads a value specified by <op2> into the register designated by <op1>.

Flags:

Z: set if result is zero. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

Given: R0 = 5Ah, R1 = AAh, IDH:IDL0 = 8023h, eid = 1

R0, R1

// R0

AAh

R1, IDH

// R1

80h

R2, 80h

// R2

DM[8080h]

R0, #11h

// R0

11h

R0, @ID0+1

// R0

DM[8023h], IDL0

24h

R1, @[ID0-2]

// R1

DM[8021h], IDL0

21h

R2, @[ID0+3]!

// R2

DM[8026h], IDL0

23h

R3, @[ID0-5]!

// R3

DM[801Eh], IDL0

23h

( 6" 76"

Format:

LD <op1>, <op2>

<op1>: GPR: bankd

<op2>: GPR: banks

Operation:

<op1>

<op2>

LD loads a value of a register in a specified bank (banks) into another register in a specified bank
(bankd).

Flags:

Z: set if result is zero. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

R2:1, R0:3

// Bank1's R2

bank3's R0

R0:0, R0:2

// Bank0's R0

bank2's R0

( 7 /# (

Format:

LD <op1>, <op2>

<op1>:

GPR

<op2>:

TBH/TBL

Operation:

<op1>

<op2>

LD loads a value specified by <op2> into the register designated by <op1>.

Flags:

Z: set if result is zero. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

Given: register pair R1:R0 is 16-bit unsigned data.

LDC

@IL //

TBH:TBL

PM[ILX:ILH:ILL]

R1, TBH

// R1

TBH

R0, TBL

// R0

TBL

( /# (7

Format:

LD <op1>, <op2>

<op1>:

TBH/TBL

<op2>:

GPR

Operation:

<op1>

<op2>

LD loads a value specified by <op2> into the register designated by <op1>.

Flags:

�

Example:

Given: register pair R1:R0 is 16-bit unsigned data.

TBH, R1

// TBH

TBL, R0

// TBL

(

Format:

LD <op1>, <op2>

<op1>:

SPR

<op2>:

GPR

Operation:

<op1>

<op2>

LD SPR loads the value of a GPR into an SPR.

Refer to Table 3-1 for more detailed explanation about kind of SPR.

Flags:

�

Example:

Given: register pair R1:R0 = 1020h

ILH, R1

// ILH

10h

ILL, R0

// ILL

20h

( &

Format:

LD SPR0, #imm:8

Operation:

SPR0

imm:8

LD SPR0 loads an 8-bit immediate value into SPR0.

Flags:

�

Example:

Given: eid = 1, idb = 0 (index register bank 0 selection)

IDH, #80h

// IDH point to page 80h

IDL1,

#44h

IDL0,

#55h

SR0,

#02h

The last instruction set ie (global interrupt enable) bit to `1'.

Special register group 1 (SPR1) registers are not supported in this addressing mode.

(

Format:

LDC <op1>

<op1>: @IL, @IL+

Operation:

TBH:TBL

PM[ILX:ILH:ILL]

ILL

ILL + 1 (@IL+ only)

LDC loads a data item from program memory and stores it in the TBH:TBL register pair.

@IL+ increase the value of ILL, efficiently implementing table lookup operations.

Flags:

�

Example:

ILX, R1

ILH, R2

ILL, R3

LDC

@IL

// Loads value of PM[ILX:ILH:ILL] into TBH:TBL

R1, TBH

// Move data in TBH:TBL to GPRs for further processing

R0, TBL

The statement "LDC @IL" do not increase, but if you use statement "LDC @IL+", ILL register is

increased by one after instruction execution.

Format:

LJP cc:4, imm:20

cc:4: 4-bit condition code

Operation:

PC[15:0]

imm[15:0] if condition is true and the program size is less than 64K word. If the program

is equal to or larger than 64K word, PC[19:0]

imm[19:0] as long as the condition is true. There

are 16 different conditions that can be used, as described in table 7-6.

Flags:

�

LJP cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address
of the jump.

Example:

LJP

C, %1

// Assume current PC = 0812h

�

R0, R1

// Address at 10A5h

�

After the first instruction is executed, LJP directly jumps to address 10A5h if condition is true.

($"$

Format:

LLNK cc:4, imm:20

cc:4: 4-bit condition code

Operation:

If condition is true, IL[19:0]

{PC[19:12], PC[11:0] + 2}.

Further, when the program is equal to or larger than 64K word, PC[19:0]

imm[19:0] as long as

the condition is true. If the program is smaller than 64K word, PC[15:0]

imm[15:0].

There are 16 different conditions that can be used, as described in table 7-6.

Flags:

�

LLNK is used to conditionally to

call a subroutine with the return address saved in the link register

(IL) without

This is a 2-word instruction.

Example:

LLNK

Z, %1

// Address at 005Ch, ILX:ILH:ILL

00:00:5Eh

NOP

// Address at 005Eh

�

%1 LD

R0,

�

LRET

($"$ %$&$'

Format:

LNK cc:4, imm:20

LNK

imm:12

Operation:

If LNKS can access the target address and there is no conditional code (cc:4), LNK command is

assembled to LNKS (1 word instruction) in linking time, else the LNK is assembled to LLNK (2

word

instruction).

Example:

LNK

Z, Link1

// Equal to "LLNK Z, Link1"

LNK

Link2

// Equal to "LNKS Link2"

NOP

�

Link2: NOP

�

LRET

Subroutines

section CODE, ABS 0A00h

Subroutines

Link1:

NOP

�

LRET

($"$

Format:

LNKS imm:12

Operation:

IL[19:0]

{PC[19:12], PC[11:0] + 1} and PC[11:0]

imm:12

LNKS saves the current PC in the link register and jumps to the address specified by imm:12.

Flags:

�

LNKS is used to call a subroutine with the return address saved in the link register (IL) without

Example:

LNKS

Link1

// Address at 005Ch, ILX:ILH:ILL

00:00:5Dh

NOP

// Address at 005Dh

�

Link1: NOP

�

LRET

$)($"$

Format:

LRET

Operation:

IL[19:0]

LRET returns from a subroutine by assigning the saved return address in IL to PC.

Flags:

�

Example:

LNK Link1

Link1:

NOP

�

LRET

;

PC[19:0]

ILX:ILH:ILL

Format:

NOP

Operation:

No operation.

When the instruction NOP is executed in a program, no operation occurs. Instead, the instruction

time is delayed by approximately one machine cycle per each NOP instruction encountered.

Flags:

�

Example:

NOP

Format:

OR <op1>, <op2>

<op1>:

GPR

<op2>: adr:8, #imm:8, GPR, @idm

Operation:

<op1>

OR performs the bit-wise OR operation on <op1> and <op2> and stores the result in <op1>.

Flags:

Z: set if result is zero. Reset if not.

N: exclusive OR of V and MSB of result.

Example:

Given: IDH:IDL0 = 031Eh, eid = 1

R0, 80h

// R0

R0 | DM[0380h]

R1, #40h

// Mask bit6 of R1

R1, R0

// R1

R1 | R0

R0, @ID0

// R0

R0 | DM[031Eh], IDL0

1Eh

R1, @[ID0-1]

// R1

R1 | DM[031Dh], IDL0

1Dh

R2, @[ID0+1]!

// R2

R2 | DM[031Fh], IDL0

1Eh

R3, @[ID0-1]!

// R3

R3 | DM[031Dh], IDL0

1Eh

Format:

OR SR0, #imm:8

Operation:

SR0

SR0 | imm:8

OR SR0 performs the bit-wise OR operation on SR0 and imm:8 and stores the result in SR0.

Flags:

�

Example:

Given: SR0 = 00000000b

EID

EQU 01h

EQU 02h

IDB1

EQU 04h

IE0

EQU 40h

IE1

EQU 80h

OR SR0, #IE | IE0 | IE1

OR SR0, #00000010b

In the first example, the statement "OR SR0, #EID|IE|IE0" set global interrupt(ie), interrupt 0(ie0)
and interrupt 1(ie1) to `1' in SR0. On the contrary, enabled bits can be cleared with instruction "AND
SR0, #imm:8". Refer to instruction AND SR0 for more detailed explanation about disabling bit.

In the second example, the statement "OR SR0, #00000010b" is equal to instruction EI, which is
enabling interrupt globally.

Format:

POP

Operation:

sptr

sptr � 2

POP decrease sptr by 2. The top two bytes of the hardware stack are therefore invalidated.

Flags:

�

Example:

Given: sptr[5:0] = 001010b

POP

This POP instruction decrease sptr[5:0] by 2. Therefore sptr[5:0] is 001000b.

Format:

POP <op>

<op>: GPR, SPR

Operation:

<op>

HS[sptr - 1], sptr

sptr - 1

POP copies the value on top of the stack to <op> and decrease sptr by 1.

Flags:

Z: set if the value copied to <op> is zero. Reset if not.

N: set if the value copied to <op> is negative. Reset if not.

When <op> is SPR, no flags are affected, including Z and N.

Example:

POP R0

HS[sptr-1], sptr

sptr-1

POP IDH

IDH

HS[sptr-1], sptr

sptr-1

In the first instruction, value of HS[sptr-1] is loaded to R0 and the second instruction "POP IDH" load
value of HS[sptr-1] to register IDH. Refer to chapter 5 for more detailed explanation about POP
operations for hardware stack.

Format:

PUSH <op>

<op>: GPR, SPR

Operation:

HS[sptr]

<op>, sptr

sptr + 1

PUSH stores the value of <op> on top of the stack and increase sptr by 1.

Flags:

�

Example:

PUSH

// HS[sptr]

R0, sptr

sptr + 1

PUSH

IDH

HS[sptr]

IDH, sptr

sptr + 1

In the first instruction, value of register R0 is loaded to HS[sptr-1] and the second instruction "PUSH
IDH" load value of register IDH to HS[sptr-1]. Current HS pointed by stack point sptr[5:0] be emptied.
Refer to chapter 5 for more detailed explanation about PUSH operations for hardware stack.

$)$"$

Format:

RET

Operation:

HS[sptr - 2], sptr

sptr � 2

RET pops an address on the hardware stack into PC so that control returns to the subroutine call
site.

Flags:

�

Example:

Given: sptr[5:0] = 001010b

CALLS

Wait

// Address at 00120h

�

Wait: NOP

// Address at 01000h

NOP

RET

After the first instruction CALLS execution, "PC+1", 0121h is loaded to HS[5] and hardware stack
pointer sptr[5:0] have 001100b and next PC became 01000h. The instruction RET pops value
0121h on the hardware stack HS[sptr-2] and load to PC then stack pointer sptr[[5:0] became
001010b.

()

Format:

RL <op>

<op>:

GPR

Operation:

{<op>[6:0], <op>[7]}

RL rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C).

Flags:

C: set if the MSB of <op> (before rotating) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after rotating) is 1. Reset if not.

Example:

Given: R0 = 01001010b, R1 = 10100101b

// N flag is set to `1', R0

10010100b

// C flag is set

to `1', R1

01001011b

()

Format:

RLC <op>

<op>:

GPR

Operation:

{<op>[6:0], C}

RLC rotates the value of <op> to the left and stores the result back into <op>.
The original MSB of <op> is copied into carry (C), and the original C bit is copied into <op>[0].

Flags:

C: set if the MSB of <op> (before rotating) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after rotating) is 1. Reset if not.

Example:

Given: R2 = A5h, if C = 0

RLC R2

4Ah, C flag is set to `1'

RL R0
RLC R1

In the second example, assuming that register pair R1:R0 is 16-bit number, then RL and RLC are
used for 16-bit rotate left operation. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.

Format:

RR <op>

<op>:

GPR

Operation:

{<op>[0], <op>[7:1]}

RR rotates the value of <op> to the right and stores the result back into <op>. The original LSB of
<op> is copied into carry (C).

Flags:

C: set if the LSB of <op> (before rotating) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after rotating) is 1. Reset if not.

Example:

Given: R0 = 01011010b, R1 = 10100101b

// No change of flag, R0

00101101b

// C and N flags are set

to `1', R1

11010010b

Format:

RRC <op>

<op>:

GPR

Operation:

{C, <op>[7:1]}

RRC rotates the value of <op> to the right and stores the result back into <op>. The original LSB of
<op> is copied into carry (C), and C is copied to the MSB.

Flags:

C: set if the LSB of <op> (before rotating) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after rotating) is 1. Reset if not.

Example:

Given: R2 = A5h, if C = 0

RRC R2

52h, C flag is set to `1'

RR R0
RRC R1

In the second example, assuming that register pair R1:R0 is 16-bit number, then RR and RRC are
used for 16-bit rotate right operation. But note that zero (Z) flag do not exactly reflect result of 16-bit
operation. Therefore when programming 16-bit decrement, take care of the change of Z flag.

Format:

SBC <op1>, <op2>

<op1>: GPR

<op2>: adr:8, GPR

Operation:

<op1>

<op1> + ~<op2> + C

SBC computes (<op1> - <op2>) when there is carry and (<op1> - <op2> - 1) when there is no

carry.

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated.

N: set if result is negative. Reset if not.

Example:

SBC

R0, 80h

// If eid = 0, R0

R0 + ~DM[0080h] + C

// If eid = 1, R0

R0 + ~DM[IDH:80h] + C

SBC

R0,

R0 + ~R1 + C

SUB

R0,

SBC

R1,

In the last two instructions, assuming that register pair R1:R0 and R3:R2 are 16-bit signed or
unsigned numbers. Even if the result of "ADD R0, R2" is not zero, zero (Z) flag can be set to `1' if the
result of "SBC R1,R3" is zero. Note that zero (Z) flag do not exactly reflect result of 16-bit operation.
Therefore when programming 16-bit addition, take care of the change of Z flag.

)()

Format:

SL <op>

<op>:

GPR

Operation:

{<op>[6:0], 0}

SL shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).

Flags:

C: set if the MSB of <op> (before shifting) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after shifting) is 1. Reset if not.

Example:

Given: R0 = 01001010b, R1 = 10100101b

// N flag is set to `1', R0

10010100b

// C flag is set

to `1', R1

01001010b

)()

Format:

SLA <op>

<op>: GPR

Operation:

{<op>[6:0], 0}

SLA shifts <op> to the left by 1 bit. The MSB of the original <op> is copied into carry (C).

Flags:

C: set if the MSB of <op> (before shifting) is 1. Reset if not.

Z: set if result is zero. Reset if not.

V: set if the MSB of the result is different from C. Reset if not.

N: set if the MSB of <op> (after shifting) is 1. Reset if not.

Example:

Given: R0 = AAh

SLA

// C, V, N flags are set to `1', R0

54h

Format:

SR <op>

<op>: GPR

Operation:

{0, <op>[7:1]}

SR shifts <op> to the right by 1 bit. The LSB of the original <op> (i.e., <op>[0]) is copied into carry
(C).

Flags:

C: set if the LSB of <op> (before shifting) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after shifting) is 1. Reset if not.

Example:

Given: R0 = 01011010b, R1 = 10100101b

// No change of flags, R0

00101101b

// C flag is set

to `1', R1

01010010b

Format:

SRA <op>

<op>: GPR

Operation:

{<op>[7], <op>[7:1]}

SRA shifts <op> to the right by 1 bit while keeping the sign of <op>. The LSB of the original <op>
(i.e., <op>[0]) is copied into carry (C).

Flags:

C: set if the LSB of <op> (before shifting) is 1. Reset if not.

Z: set if result is zero. Reset if not.

N: set if the MSB of <op> (after shifting) is 1. Reset if not.

@&G-/ @,#HI6 9' /2(@&G J*.*

/(A(A 1(

Example:

Given: R0 = 10100101b

SRA

// C, N flags are set to `1', R0

11010010b

SRA

// N flag is set to `1', R0

11101001b

SRA

// C, N flags are set to `1', R0

11110100b

SRA

// N flags are set to `1', R0

11111010b

. %$$'

Format:

STOP

Operation:

The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter the STOP mode. In the STOP mode, the contents of the on-chip CPU
registers, peripheral registers, and I/O port control and data register are retained. A reset operation
or external or internal interrupts can release stop mode. The STOP instruction is a pseudo
instruction. It is assembled as "SYS #0Ah", which generates the SYSCP[7-0] signals. These signals
are decoded and stop the operation.

The next instruction of STOP instruction is executed, so please use the NOP instruction after the
STOP instruction.

Example:

STOP
NOP
NOP
NOP

�

In this example, the NOP instructions provide the necessary timing delay for oscillation stabilization
before the next instruction in the program sequence is executed. Refer to the timing diagrams of
oscillation stabilization, as described in Figure 15-4, 15-5

Format:

SUB <op1>, <op2>

<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm

Operation:

<op1>

<op1> + ~<op2> + 1

SUB adds the value of <op1> with the 2's complement of <op2> to perform subtraction on

Flags:

C: set if carry is generated. Reset if not.

Z: set if result is zero. Reset if not.

V: set if overflow is generated. Reset if not.
N: set if result is negative. Reset if not.

Example:

Given: IDH:IDL0 = 0150h, DM[0143h] = 26h, R0 = 52h, R1 = 14h, eid = 1

SUB

R0, 43h

// R0

R0 + ~DM[0143h] + 1 = 2Ch

SUB

R1, #16h

// R1

FEh, N flag is set to `1'

SUB

R0, R1

// R0

R0 + ~R1 + 1 = 3Eh

SUB

R0, @ID0+1

// R0

R0 + ~DM[0150h] + 1, IDL0

51h

SUB

R0, @[ID0-2]

// R0

R0 + ~DM[014Eh] + 1, IDL0

4Eh

SUB

R0, @[ID0+3]!

// R0

R0 + ~DM[0153h] + 1, IDL0

50h

SUB

R0, @[ID0-2]!

// R0

R0 + ~DM[014Eh] + 1, IDL0

50h

2A (24723</ &( 8(
/

The example in the SBC description shows how SUB and

SBC can be used in pair to subtract a 16-bit number from another.

K2>((7862((78962>((789:62((789:#2K2< 2'

Format:

SWAP <op1>, <op2>

<op1>: GPR
<op2>: SPR

Operation:

<op1>

<op1>

SWAP swaps the values of the two operands.

Flags:

�

Among the SPRs, SR0 and SR1 can not be used as <op2>.

Example:

Given: IDH:IDL0 = 8023h, R0 = 56h, R1 = 01h

SWAP

R1, IDH

// R1

80h, IDH

01h

SWAP

R0, IDL0

// R0

23h, IDL0

56h

After execution of instructions, index registers IDH:IDL0 (ID0) have address 0156h.

Format:

SYS #imm:8

Operation:

SYS generates SYSCP[7:0] and nSYSID signals.

Flags:

�

Mainly used for system peripheral interfacing.

Example:

SYS #0Ah

SYS

#05h

In the first example, statement "SYS #0Ah" is equal to STOP instruction and second example "SYS
#05h" is equal to IDLE instruction. This instruction does nothing but increase PC by one and
generates SYSCP[7:0] and nSYSID signals.

Format:

TM <op>, #imm:8

<op>:

GPR

Operation:

TM performs the bit-wise AND operation on <op> and imm:8 and sets the flags. The content of

<op> is not changed.

Flags:

Z: set if result is zero. Reset if not.

N: set if result is negative. Reset if not.

Example:

Given: R0 = 01001101b

R0, #00100010b

// Z flag is set to `1'

-5$3.

Format:

XOR <op1>, <op2>

<op1>: GPR
<op2>: adr:8, #imm:8, GPR, @idm

Operation:

<op1>

XOR performs the bit-wise exclusive-OR operation on <op1> and <op2> and stores the result in

<op1>.

Flags:

Z: set if result is zero. Reset if not.

N: set if result is negative. Reset if not.

Example:

Given: IDH:IDL0 = 8080h, DM[8043h] = 26h, R0 = 52h, R1 = 14h, eid = 1

XOR

R0, 43h

// R0

74h

XOR

R1, #00101100b

// R1

38h

XOR

R0, R1

// R0

46h

XOR

R0, @ID0

// R0

R0 ^ DM[8080h], IDL0

81h

XOR

R0, @[ID0-2]

// R0

R0 ^ DM[807Eh], IDL0

7Eh

XOR

R0, @[ID0+3]!

// R0

R0 ^ DM[8083h], IDL0

80h

XOR

R0, @[ID0-5]!

// R0

R0 ^ DM[807Bh], IDL0

80h

2A (24723</ &( 8(
/
K2>((7862((78962>((789:62((789:#2K2< 2'

Электронный компонент: S3FB205