S3C7295/P7295
PRODUCT OVERVIEW
1-1
1
PRODUCT OVERVIEW
OVERVIEW
The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsung's
newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With an up-to-704-dot LCD direct drive capability, and flexible 8-bit timer/counter, the S3C7295 offers an
excellent design solution for a mid-end LCD game.
Up to 8 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to
internal and external events. In addition, the S3C7295's advanced CMOS technology provides for low power
consumption.
OTP
The S3C7295 microcontroller is also available in OTP (One Time Programmable) version, S3P7295. S3P7295
microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM.
The S3P7295 is comparable to S3C7295, both in function and in pin configuration.
PRODUCT OVERVIEW
S3C7295/P7295
1-2
FEATURES
Memory
256
4-bit RAM (excluding LCD display RAM)
16,384
8-bit ROM
8 I/O Pins
I/O: 8 pins
LCD Controller/Driver
44 segments and 16 common terminals
(8, 12 and 16 common selectable)
Internal resistor circuit for LCD bias
Voltage doubler
All dot can be switched on/off
8-bit Basic Timer
4 interval timer functions
Watch-dog timer
8-bit Timer/Counter
Programmable 8-bit timer
Arbitrary clock output (TCLO0)
Inverted clock output (
TCLO0
)
Watch Timer
Time interval generation: 0.5 s, 3.9 ms
at 32768 Hz
Four frequency outputs to BUZ pin and
BUZ
pin
Clock source generation for LCD
Interrupts
Two internal vectored interrupts
Four external vectored interrupts
Two quasi-interrupts
Memory-Mapped I/O Structure
Data memory bank 15
Power-Down Modes
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Sub system clock stop mode
Oscillation Sources
Crystal, ceramic, or RC for main system clock
Crystal oscillator for subsystem clock
Main system clock frequency: 4.19 MHz
(typical)
Subsystem clock frequency: 32.768 kHz
CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
0.95, 1.91, 15.3 s at 4.19 MHz (main)
122 s at 32.768 kHz (subsystem)
Operating Temperature
40
C to 85
C
Operating Voltage Range
2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)
Package Type
80-pin QFP or pellet
S3C7295/P7295
PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
ARITHMETIC
AND
LOGIC UNIT
INTERRUPT
CONTROL
BLOCK
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PROGRAM
STATUS
WORD
STACK
POINTER
INSTRUCTION DECODER
CLOCK
RESET
Xin
XTin
Xout
XTout
INTERNAL
INTERRUPT
P1.3/INT
P1.1/INT1
P1.2/INT2
P1.0/INT0
I/O PORT 1
8-BIT
TIMER/
COUNTER
WATCH-DOG
TIMER
I/O PORT 0
P0.3/BUZ/K3
P0.1/ /K1
P0.2/CLO/ /K2
P0.0/TCLO0/K0
BIAS
CA
CB
SEG0-SEG43
COM0-COM15
VLC0
16K BYTES
PROGRAM
MEMORY
VOLTAGE
DOUBLER
LCD
DRIVER/
CONTROLLER
WATCH
TIMER
BASIC
TIMER
BUZ
TCLO0
256 x 4-BIT
DATA
MEMORY
Figure 1-1. S3C7295 Simplified Block Diagram
PRODUCT OVERVIEW
S3C7295/P7295
1-4
PIN ASSIGNMENTS
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
S3C7295
(TOP VIEW)
SEG41
SEG42
SEG43
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ/K3
P0.2/CLO/
BUZ
/K2
P0.1/
TCLO0
/K1
P0.0/TCLO0/K0
VDD
VSS
Xout
Xin
TEST
XTin
XTout
RESET
CA
CB
VLC0
BIAS
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
Figure 1-2. S3C7295 80-QFP Pin Assignment Diagram
S3C7295/P7295
PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. S3C7295 Pin Descriptions
Pin Name
Pin
Type
Description
Circuit
Type
Number
Share Pin
P0.0
P0.1
P0.2
P0.3
I/O
4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
Individual pull-up resistors are software assignable;
pull-up resistors are automatically disabled for
output pins.
E-1
11
10
9
8
TCLO0/K0
TCLO0
/K1
CLO/
BUZ
/K2
BUZ/K3
P1.0
P1.1
P1.2
P1.3
I/O
Same as port 0.
E-1
7
6
5
4
INT0
INT1
INT2
INT4
INT0, INT1
I/O
External interrupts. The triggering edge for INT0
and INT1 is selectable.
7, 6
P1.0, P1.1
INT2
I/O
Quasi-interrupt with detection of rising or falling
edges
5
P1.2
INT4
I/O
External interrupt with detection of rising or falling
edges.
4
P1.3
BUZ
I/O
2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for
buzzer sound.
8
P0.3/K3
BUZ
I/O
Inverted BUZ signal
9
P0.2/CLO/K2
CLO
I/O
Clock output
9
P0.2/
BUZ
/K2
TCLO0
I/O
Inverted Timer/counter 0 clock output
10
P0.1/K1
TCLO0
I/O
Timer/counter 0 clock output
11
P0.0/K0
COM0COM15
O
LCD common signal output
H-6
3924
SEG0SEG43
O
LCD segment signal output
H-6
4080,
13
PRODUCT OVERVIEW
S3C7295/P7295
1-6
Table 1-1. S3C7295 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Circuit
Type
Number Share Pin
K0K3
I/O
External interrupt (triggering edge is selectable)
E-1
118
P0.0P0.3
V
DD
Power supply
12
V
SS
Ground
13
RESET
I
Reset input (active low)
B
19
CA, CB
Capacitor terminal for voltage doubling
20, 21
VCL0
LCD power supply input
22
BIAS
O
Doubling voltage level output
23
X
in,
X
out
Crystal, ceramic or RC oscillator pins for system
clock
15, 14
XT
in,
XT
out
Crystal oscillator pins for subsystem clock
17, 18
TEST
I
Test input (must be connected to V
SS
)
16
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
S3C7295/P7295
PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
V
DD
P
-
CHANNEL
IN
N
-
CHANNEL
Figure 1-3. Pin Circuit Type A
V
DD
PULL-UP
RESISTOR
SCHMITT TRIGGER
IN
Figure 1-4. Pin Circuit Type B
V
DD
RESISTOR
ENABLE
N
-
CH
P
-
CH
V
DD
PULL-UP
RESISTOR
DATA
OUTPUT
DISABLE
SCHMITT TRIGGER
I/O
PNE
Figure 1-5. Pin Circuit Type E-1
V
LC1
OUT
V
LC2
V
LC3
SEG/COM DATA
V
LC0
V
LC4
V
SS
Figure 1-6. Pin Circuit Type H-6
S3C7295/P7295
ELECTRICAL DATA
13-1
13
ELECTRICAL DATA
OVERVIEW
In this section, information on S3C7295 electrical characteristics is presented as tables and graphics.
The information is arranged in the following order:
Standard Electrical Characteristics
-- Absolute maximum ratings
-- D.C. electrical characteristics
-- Main system clock oscillator characteristics
-- Subsystem clock oscillator characteristics
-- I/O capacitance
-- A.C. electrical characteristics
-- Operating voltage range
Miscellaneous Timing Waveforms
-- A.C timing measurement point
-- Clock timing measurement at X
in
-- Clock timing measurement at XT
in
-- TCL timing
-- Input timing for
RESET
-- Input timing for external interrupts
-- Serial data transfer timing
Stop Mode Characteristics and Timing Waveforms
-- RAM data retention supply voltage in stop mode
-- Stop mode release timing when initiated by
RESET
-- Stop mode release timing when initiated by an interrupt request
ELECTRICAL DATA
S3C7295/P7295
13-2
Table 13-1. Absolute Maximum Ratings
(T
A
= 25
C)
Parameter
Symbol
Conditions
Rating
Units
Supply Voltage
V
DD
0.3 to + 4.5
V
Input Voltage
V
I
Ports 0, 1
0.3 to VDD + 0.3
V
Output Voltage
V
O
0.3 to VDD + 0.3
V
Output Current High
I
O H
One I/O pin active
15
mA
All I/O pins active
30
Output Current Low
I
O L
One I/O pin active
+ 30 (Peak value)
mA
+ 15
(note)
Total for pins 0, 1
+ 100 (Peak value)
+ 60
(note)
Operating Temperature
T
A
40 to + 85
C
Storage Temperature
T
stg
65 to + 150
C
NOTE: The values for Output Current Low ( I
OL
) are calculated as Peak Value
Duty .
Table 13-2. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
V
IH1
Ports 0, 1, and
RESET
0.8V
DD
V
DD
V
V
IH2
X
in
, X
out
, and XT
in
V
DD
0.1
V
DD
Input Low
Voltage
V
IL1
Ports 0, 1, and
RESET
0.2V
DD
V
V
IL2
X
in
, X
out
, and XT
in
0.1
Output High
Voltage
V
OH
V
DD
= 2.2 V to 3.4 V
I
OH
= 1 mA
Ports 0, 1
V
DD
1.0
V
Output Low
Voltage
V
OL
V
DD
= 2.2 V to 3.4 V
I
OL
= 5 mA
Ports 0, 1
1.0
V
S3C7295/P7295
ELECTRICAL DATA
13-3
Table 13-2. D.C. Electrical Characteristics (Continued)
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Leakage
Current
I
LIH1
V
I
= V
DD
All input pins except those
specified below for I
LIH2
3
A
I
LIH2
V
I
= V
DD
X
in
, X
out
and XT
in
20
Input Low
Leakage
Current
I
LIL1
V
I
= 0 V
All input pins except
RESET
X
in,
X
out
and XT
in
3
A
I
LIL2
V
I
= 0 V
RESET,
X
in
, X
out
and XT
in
20
Output High
Leakage
Current
I
LOH
V
O
= V
DD
All output pins
3
A
Output Low
Leakage
Current
I
LOL
V
O
= 0 V
All output pins
3
A
Pull-Up
Resistor
R
L1
V
I
= 0 V; V
DD
= 3V
Ports 0, 1
50
100
200
k
R
L2
V
I
= 0 V; V
DD
= 3V;
RESET
200
450
800
LCD Voltage
Dividing
Resistor
(1)
R
LCD1
Ta = + 25
C
50
100
150
k
R
LCD2
Ta = + 25
C
25
50
75
V
DD
-COM
i
Voltage Drop
(i = 015)
V
DC
V
LCD
= 3.0 V
15 A per common pin
120
mV
V
LCD
-
SEGx
Voltage Drop
(x = 043)
V
DS
V
LCD
= 3.0 V
15 A per common pin
120
Middle Output
V
LC0
V
LC0 =
5.0 V
V
LC0
-0.2
V
LC0
V
LC0
+0.2
V
Voltage
(2)
V
LC1
0.8V
LC0
-0.2
0.8V
LC0
0.8V
LC0
+0.2
V
LC2
0.6V
LC0
-0.2
0.6V
LC0
0.6V
LC0
+0.2
V
LC3
0.4V
LC0
-0.2
0.4V
LC0
0.4V
LC0
+0.2
V
LC4
0.2V
LC0
-0.2
0.2V
LC0
0.2V
LC0
+0.2
NOTES:
1.
RLCD1 is LCD voltage dividing resistor when LCON.2 = "0", and RLCD2 when LCON.2 = "1".
2.
It is middle output voltage when 1/16 duty and 1/5 bias.
ELECTRICAL DATA
S3C7295/P7295
13-4
Table 13-2. D.C. Electrical Characteristics (Concluded)
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current
(1)
I
DD1
V
DD
= 3V
10%
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
1.3
3.0
mA
I
DD2
Idle mode; V
DD
= 3 V
10%
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
0.4
1.0
I
DD3
(2)
V
DD
= 3 V 10%
32 kHz crystal oscillator
15
30
A
I
DD4
(2)
Idle mode; V
DD
= 3 V 10%
32 kHz crystal oscillator
5
15
I
DD5
Stop mode; V
DD
= 3 V 10%
SCMOD=0000B,
XTin=0V
0.5
3
Stop mode; V
DD
= 3 V 10%
SCMOD=0100B
0.2
2
NOTES:
1.
Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
voltage doubler, and output port drive currents.
2.
Data includes power consumption for subsystem clock oscillation.
3.
When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
S3C7295/P7295
ELECTRICAL DATA
13-5
Table 13-3. Main System Clock Oscillator Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Ceramic
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
0.4
4.19
MHz
Stabilization time
(2)
Stabilization occurs
when V
DD
is equal to
the minimum
oscillator voltage
range; V
DD
= 3.0 V
4
ms
Crystal
Oscillator
Xin
Xout
C1
C2
Oscillation frequency
(1)
0.4
4.19
MHz
Stabilization time
(2)
V
DD
= 3.0 V
10
ms
External
Clock
Xin
Xout
X
in
input frequency
(1)
0.4
4.19
MHz
X
in
input high and low
level width (t
XH
, t
XL
)
83.3
1250
ns
RC
Oscillator
Xin
Xout
R
Frequency
V
DD
= 3 V
0.4
1.5
MHz
NOTES:
1.
Oscillation frequency and Xin
input
frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.
ELECTRICAL DATA
S3C7295/P7295
13-6
Table 13-4. Recommended Oscillator Constants
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Manufacturer
Series
Number
(1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
C2
MIN
MAX
TDK
FCR
M5
3.58 MHz4.2 MHz
33
33
2.2
3.4
Leaded Type
FCR
MC5
3.58 MHz4.2 MHz
(2)
(2)
2.2
3.4
On-chip C
Leaded Type
CCR
MC3
3.58 MHz4.2 MHz
(3)
(3)
2.2
3.4
On-chip C
SMD Type
NOTES:
1.
Please specify normal oscillator frequency.
2.
On-chip C: 30pF built in.
3.
On-chip C: 38pF built in.
Table 13-5. Subsystem Clock Oscillator Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max
Units
Crystal
Oscillator
XTin
XTout
C1
C2
Oscillation frequency
(1)
32
32.768
35
kHz
Stabilization time
(2)
V
DD
= 2.2 V to 3.4 V
1.0
3
s
External
Clock
XTin
XTout
XT
in
input frequency
(1)
32
100
kHz
XT
in
input high and low
level width (t
XTL
, t
XTH
)
5
15
s
NOTES:
1.
Oscillation frequency and XTin
input frequency data are for oscillator characteristics only.
2.
Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
S3C7295/P7295
ELECTRICAL DATA
13-7
Table 13-6. Input/Output Capacitance
(T
A
= 25
C, V
DD
=
0 V )
Parameter
Symbol
Condition
Min
Typ
Max
Units
Input
Capacitance
C
IN
f = 1 MHz; Unmeasured pins
are returned to V
SS
15
pF
Output
Capacitance
C
OUT
15
pF
I/O Capacitance
C
IO
15
pF
Table 13-7. Voltage Doubler Output
(T
A
= -40
C to + 85
C, V
DD
=
2.2 V to 3.4 V)
Parameter
Symbol
Condition
Min
Typ
Max
Units
Voltage Doubler
Output
Vbias
V
DD
= 2.2 V to 3.4 V
2 V
DD
V
Table 13-8. A.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
(note)
t
CY
V
DD
= 2.2 V to 3.4 V
0.95
64
s
With subsystem clock (fxt)
114
122
125
Interrupt Input
High, Low Width
f
INTH,
f
INTL
INT0INT2, INT4
K0K3
10
RESET
Input Low
Width
t
RSL
Input
10
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
ELECTRICAL DATA
S3C7295/P7295
13-8
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
SUPPLY VOLTAGE (V)
15.6 kHz
CPU CLOCK
1.05 MHz
4.2 MHz
1
2
3
4
5
6
7
Main OSC frequency (Divided by 4)
2.2V
Figure 13-1. Standard Operating Voltage Range
Table 13-9. RAM Data Retention Supply Voltage in Stop Mode
(T
A
= 40
C to + 85
C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Data retention supply voltage
V
DDDR
2.2
3.4
V
Data retention supply current
I
DDDR
V
DDDR
= 2.2 V
0.1
10
A
Release signal set time
t
SREL
0
s
Oscillator stabilization wait
time
(1)
t
WAIT
Released by
RESET
2
17
/ fx
ms
Released by interrupt
(2)
NOTES:
1.
During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2.
Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
S3C7295/P7295
ELECTRICAL DATA
13-9
TIMING WAVEFORMS
t
SREL
t
WAIT
V
DD
RESET
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
IDLE MODE
NORMAL MODE
INTERNAL
OPERATION
RESET
STOP MODE
~ ~
~ ~
Figure 13-2. Stop Mode Release Timing When Initiated by
RESET
RESET
V
DD
EXECUTION OF
STOP INSTRUCTION
V
DDDR
DATA RETENTION MODE
STOP MODE
t
WAIT
t
SREL
IDLE MODE
NORMAL MODE
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
~ ~
~ ~
Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request
ELECTRICAL DATA
S3C7295/P7295
13-10
0.8
V
DD
0.2
V
DD
0.8
V
DD
0.2
V
DD
MEASUREMENT
POINTS
Figure 13-4. A.C. Timing Measurement Points (Except for X
in
and XT
in
)
Xin
t
XL
t
XH
1 / f
VDD -0.5 V
0.4 V
x
Figure 13-5. Clock Timing Measurement at X
in
XTin
t
XTL
t
XTH
1 / f
VDD - 0.5 V
0.4 V
xt
Figure 13-6. Clock Timing Measurement at XT
in
S3C7295/P7295
ELECTRICAL DATA
13-11
RESET
tRSL
0.2 VDD
Figure 13-7. Input Timing for
RESET
RESET
Signal
INT0, 1, 2, 4, K0 to K3
t
INTL
tINTH
0.8 VDD
0.2 VDD
Figure 13-8. Input Timing for External Interrupts
ELECTRICAL DATA
S3C7295/P7295
13-12
NOTES
S3C7295/P7295
ELECTRICAL DATA
13-13
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.
5.0
4.5
4.0
3.5
I DD1
, I
DD2
(mA)
(TA = 25
C, fx = 4.2 MHz)
3.0
2.5
2.0
1.5
1.0
0.5
2.7
4.0
4.5
6.0
VDD (V)
0
I
DD1
, CPU Clock = fx/4
I
DD1
, CPU Clock = fx/64
I
DD2
Figure 13-11. I
DD1
, I
DD2
VS.
V
DD
ELECTRICAL DATA
S3C7295/P7295
13-14
5
0
I DD3, 4, 5
(A)
2.5
VDD (V)
3.0
3.5
4.0
(TA = 25
C, fx = 32.768 kHz)
10
15
20
25
30
35
40
45
4.5
5.0
5.5
6.0
6.5
IDD3
2.0
50
IDD4
IDD5
Figure 13-12. I
DD3
, I
DD4
, I
DD5
VS.
V
DD
S3C7295/P7295
ELECTRICAL DATA
13-15
0.5
0
I D
D
1
(
m
A
)
0.5
Main System Clock Frequency (MHz)
1.0
1.5
2.0
(TA = 25
C, CPU CLOCK = fx/4)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2.5
3.0
3.5
4.0
4.5
VDD = 6.0 V
VDD = 4.5 V
Figure 13-13. I
DD1
VS.
Main System Clock Frequency
0.2
0
I D
D
2
(
m
A
)
0.5
Main System Clock Frequency (MHz)
1.0
1.5
2.0
(TA = 25
C)
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.5
3.0
3.5
4.0
4.5
VDD = 6.0 V
VDD = 4.5 V
Figure 13-13. I
DD2
VS.
Main System Clock Frequency
ELECTRICAL DATA
S3C7295/P7295
13-16
2.5
0
I OH
(mA)
0.5
VOH (V)
1.0
1.5
2.0
(TA = 25
C, Ports 0, 2, 3, 4, 5, 6, 7)
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD = 4.5 V
5.5
6.0
VDD = 6.0 V
Figure 1315. I
OH
VS.
V
OH
(P0, 2, 3, 4, 5, 6, 7)
S3C7295/P7295
ELECTRICAL DATA
13-17
2.5
0
I OH
(mA)
0.5
VOH (V)
1.0
1.5
2.0
(TA = 25
C, Ports 8, 9)
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
25.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD = 4.5 V
5.5
6.0
VDD = 6.0 V
Figure 1316. I
OH
VS.
V
OH
(P8, 9)
ELECTRICAL DATA
S3C7295/P7295
13-18
5.0
0
I OL
(mA)
0.5
VOL (V)
1.0
1.5
2.0
(TA = 25
C, Ports 0, 2, 3, 4, 5, 6, 7)
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
2.5
3.0
3.5
4.0
4.5
5.0
55.0
5.5
6.0
VDD = 6.0 V
VDD = 4.5 V
Figure 1317. I
OL
VS.
V
OL
(P0, 2, 3, 4, 5, 6, 7)
S3C7295/P7295
ELECTRICAL DATA
13-19
5.0
0
I OL
(mA)
0.5
VOL (V)
1.0
1.5
2.0
(TA = 25
C, Ports 8, 9)
10.0
15.0
20.0
25.0
30.0
35.0
40.0
45.0
50.0
2.5
3.0
3.5
4.0
4.5
5.0
55.0
5.5
6.0
VDD = 6.0 V
VDD = 4.5 V
Figure 1318. I
OL
VS.
V
OL
(P8, 9)
S3C7295/P7295
MECHANICAL DATA
14-1
14
MECHANICAL DATA
OVERVIEW
The S3C7295/P7295 is available in a 80-QFP-1420 package.
80-QFP-1420C
#80
20.00
0.20
23.90
0.30
14.00
0.20
17.90
0.30
#1
0.80
0.35
+ 0.10
NOTE: Dimensions are in millimeters.
0.15 MAX
(0.80)
0.15
+ 0.10
- 0.05
0-8
0.10 MAX
0.80
0.20
0.05 MIN
2.65
0.10
3.00 MAX
0.80
0.20
Figure 14-1. 80-QFP-1420C Package Dimensions
S3C7295/P7295
S3P7295 OTP
15-1
15
S3P7295 OTP
OVERVIEW
The S3P7295 single-chip CMOS microcontroller is the OTP (One Time Programmable)
version of the S3C7295
microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.
The S3P7295 is fully compatible with the S3C7295, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7295 is ideal for use as an evaluation chip for the S3C7295.
S3P7295 OTP
S3C7295/P7295
15-2
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
S3P7295
(TOP VIEW)
SEG41
SEG42
SEG43
P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0
P0.3/BUZ/K3
P0.2/CLO/
BUZ
/K2
SDAT / P0.1/
TCLO0
/K1
SCLK /P0.0/TCLO0/K0
VDD /VDD
VSS/VSS
Xout
Xin
VPP/TEST
XTin
XTout
RESET
RESET / RESET
CA
CB
VLC0
BIAS
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEG0
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
Figure 15-1. S3P7295 Pin Assignments (80-QFP Package)
S3C7295/P7295
S3P7295 OTP
15-3
Table 15-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
During Programming
Pin Name
Pin Name
Pin No.
I/O
Function
P0.1
SDAT
10
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P0.0
SCLK
11
I/O
Serial clock pin. Input only pin.
TEST
V
PP
(TEST)
16
I
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing
mode). When 12.5 V is applied, OTP is in
writing mode and when 5 V is applied, OTP is in
reading mode. (Option)
RESET
RESET
19
I
Chip initialization
V
DD
/V
SS
V
DD
/V
SS
12/13
I
Logic power supply pin. VDD should be tied to
+5 V during programming.
Table 15-2. Comparison of S3P7295 and S3C7295 Features
Characteristic
S3P7295
S3C7295
Program Memory
16 Kbyte EPROM
16 Kbyte mask ROM
Operating Voltage (V
DD
)
2.2 V to 3.4 V
2.2 V to 3.4 V
OTP Programming Mode
V
DD
= 5 V, V
PP
(TEST)=12.5V
Pin Configuration
80 QFP
80 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the S3P7295, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 153 below.
Table 15-3. Operating Mode Selection Criteria
V
DD
V
PP
(TEST)
REG/MEM
Address
(A15A0)
R/W
Mode
5 V
5 V
0
0000H
1
EPROM read
12.5 V
0
0000H
0
EPROM program
12.5 V
0
0000H
1
EPROM verify
12.5 V
1
0E3FH
0
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3P7295 OTP
S3C7295/P7295
15-4
Table 15-4. D.C. Electrical Characteristics
(T
A
= 40
C to + 85
C, V
DD
= 2.2 V to 3.4 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply
Current (1)
IDD1
V
DD
= 3V
10%
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
1.3
3.0
mA
IDD2
Idle mode; V
DD
= 3 V
10%
4.19 MHz (PCON=3H) crystal oscillator
C1 = C2 = 22 pF
0.4
1.0
IDD3 (2)
V
DD
= 3 V 10%
32 kHz crystal oscillator
15
30
A
IDD4 (2)
Idle mode; V
DD
= 3 V 10%
32 kHz crystal oscillator
5
15
IDD5
Stop mode; V
DD
= 3 V 10%
SCMOD=0000B,
XTin=0V
0.5
3
Stop mode; V
DD
= 3 V 10%
SCMOD=0100B
0.2
2
NOTES:
1.
Data includes power consumption for subsystem clock oscillation.
2.
When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the
subsystem clock is used.
3.
Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors,
voltage doubler, and output port drive currents.
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
SUPPLY VOLTAGE (V)
15.6 kHz
CPU CLOCK
1.05 MHz
4.2 MHz
1
2
3
4
5
6
7
Main OSC frequency (Divided by 4)
2.2V
Figure 15-2. Standard Operating Voltage Range
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