S3C7559/P7559

PRODUCT OVERVIEW

1-1

PRODUCT OVERVIEW

OVERVIEW

The S3C7559/P7559 single-chip CMOS microcontroller has been designed for high-performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). The S3P7559 is a
microcontroller which has 32-kbyte one-time-programmable EPROM but its functions are same to S3C7559.

With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the S3C7559/P7559 offers
an excellent design solution for a wide variety of telecommunication applications.

Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O. Seven vectored interrupts provide fast
response to internal and external events. In addition, the S3C7559/P7559's advanced CMOS technology
provides for low power consumption and a wide operating voltage range.

DEVELOPMENT SUPPORT

The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based develop-
ment environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its
window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction
timing, and performance measurement applications.

The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and
accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard
hex files that also contain program control data for SMDS compatibility.

PRODUCT OVERVIEW

S3C7559/P7559

1-2

FEATURES SUMMARY

Memory

1 K

4-bit RAM

32 K

8-bit ROM

55 I/O Pins

Input only: 4 pins

I/O: 43 pins

N-channel open-drain I/O (S/W): 8 pins

Memory-Mapped I/O Structure

Data memory bank 15

DTMF Generator

16 dual-tone frequencies for tone dialing

8-bit Basic Timer

Programmable internal timer

Watchdog timer

Two 8-bit Timer/Counters

Programmable interval timer

External event counter function

Timer/counters clock outputs to TCLO0 and
TCLO1 pins

External clock signal divider

Serial I/O interface clock generator

Watch Timer

Time interval generation:
0.5 s, 3.9 ms at 32.768 kHz

4 frequency outputs to the BUZ pin

8-bit Serial I/O Interface

8-bit transmit/receive mode

8-bit receive mode

LSB-first or MSB-first transmission selectable

Bit Sequential Carrier

Supports 8-bit serial data transfer in arbitrary
format

Interrupts

3 external interrupt vectors

4 internal interrupt vectors

2 quasi-interrupts

Power-Down Modes

Idle: Only CPU clock stops

Stop: Main system clock stops

Subsystem clock stop mode

Oscillation Sources

Crystal, ceramic for main system clock

Crystal oscillator for subsystem clock

Main system clock frequency:
3.579545 MHz (typical)

Subsystem clock frequency: 32.768 kHz
(typical)

CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

0.67, 1.33, 10.7 µs at 6.0 MHz

1.12, 2.23, 17.88 µs at 3.579545 MHz

122 µs at 32.768 kHz

Operating Temperature

C to 85

Operating Voltage Range

1.8 V to 5.5 V (at 3 MHz)

2.7 V to 5.5 V (at 6 MHz)

Package Types

64 SDIP, 64 QFP

S3C7559/P7559

PRODUCT OVERVIEW

1-3

BLOCK DIAGRAM

Stack

Pointer

Arithmetic

and

Logic Unit

Instruction Decoder

Internal

Interrupts

Interrupt

Control

Block

Clock

32 K Byte

Program

Memory

OUT

Basic
Timer

Watch

Timer

I/O Port 12

Serial I/O

Port

I/O Port 0

I/O Port 13

Program

Counter

Program

Status

Word

Flags

Watch-Dog

Timer

DTMF

Generator

Input

Port1

I/O Port 2

I/O Port 3

RESET

INT0, INT1, INT2 INT4

P0.0/

SCK

P0.1/SO
P0.2/SI
P0.3/BTCO

P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4

P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P2.3/BUZ

P4.0-P4.3

P5.0-P5.3

P3.0/TCLO0
P3.1/TCLO1
P3.2
P3.3

I/O Port 8

I/O Port 9

1 K x 4-BIT

Data

Memory

P13.0-P13.2

P12.0-P12.3

I/O Port 10

I/O Port 11

P11.0-P11.3

P10.0-P10.3

P9.0-P9.3

P8.0-P8.3

I/O Port 6

I/O Port 7

P7.0-P7.3/

KS4-KS7

P6.0-P6.3/

KS0-KS3

8-BIT

Timer/

Counter 1

8-BIT

Timer/

Counter 0

I/O Port 4

I/O Port 5

DTMF

Figure 1-1. S3C7559/P7559 Simplified Block Diagram

PRODUCT OVERVIEW

S3C7559/P7559

1-4

PIN ASSIGNMENTS

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P13.2
P13.1
P13.0

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1
P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/

SCK

P10.3
P10.2
P10.1
P10.0
P11.3
P11.2
P11.1
P11.0
P12.3
P12.2
P12.1
P12.0

P3.3
P3.2

TEST

DTMF

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

VSS
P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XT

OUT

RESET

P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
P3.0/TCL0
P3.1/TCL1

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

S3C7559

(64-SDIP-750)

Figure 1-2. S3C7559/P7559 Pin Assignment Diagrams (64-SDIP)

S3C7559/P7559

PRODUCT OVERVIEW

1-5

P8.1

P8.2

P8.3

P7.0/KS4

P7.1/KS5

P7.2/KS6

P7.3/KS7

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

OUT

RESET

P5.0

P5.1

P5.2

P8.0
P9.3
P9.2
P9.1
P9.0

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P13.2
P13.1
P13.0

32
31
30
29
28
27
26
25
24
23
22
21
20

52
53
54
55
56
57
58
59
60
61
62
63
64

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1

P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/

SCK

P10.3

P10.2

P10.1

P10.0

P11.3

P11.2

P11.1

P11.0

P12.3

P12.2

P12.1

P5.3
P4.0
P4.1
P4.2
P4.3
P3.0/TCL0
P3.1/TCL1
V

DTMF
TEST
P3.2
P3.3
P12.0

S3C7559

(64-QFP-1420F)

Figure 1-3. S3C7559/P7559 Pin Assignment Diagrams (64-QFP)

PRODUCT OVERVIEW

S3C7559/P7559

1-6

PIN DESCRIPTIONS

Table 1-1. S3C7559/P7559 Pin Descriptions

Pin Name

Pin Type

Description

Number

Share Pin

P0.0
P0.1
P0.2
P0.3

I/O

4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

15 (8)
14 (7)
13 (6)
12 (5)

SCK

BTCO

P1.0
P1.1
P1.2
P1.3

4-bit input port.
1-bit and 4-bit read and test is possible.
4-bit pull-up resistors are assignable by software to
port 1.

1 (61)
2 (60)
3 (59)
4 (58)

INT0
INT1
INT2
INT4

P2.0
P2.1
P2.2
P2.3

I/O

Same as port 0.

11 (4)
10 (3)

9 (2)
8 (1)

TCLO0
TCLO1

CLO
BUZ

P3.0
P3.1
P3.2
P3.3

I/O

Same as port 0.

34 (27)
33 (26)
29 (22)
28 (21)

TCL0
TCL1

SCLK

(1)

SDAT

(1)

P4.0P4.3

P5.0P5.3

I/O

4-bit I/O ports.
1-bit and 4-bit read/write and test is possible.
4-bit pull-up resistors are software assignable to input
pins and are automatically disable for output pins.
N-channel open-drain or push-pull output can be
selected by software. Port 4 and 5 can be paired to
support 8-bit data transfer.

3835

(3128)

4239

(3532)

P6.0P6.3

P7.0P7.3

I/O

4-bit I/O ports.
1-bit or 4-bit read/write and test is possible.
Port 6 pins are individually software configurable as
input or output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.

5148

(4441)

5552

(4845)

KS0KS3

KS4KS7

P8.0P8.3

I/O

Same as port 0.

5956

(5249)

P9.0P9.3

I/O

4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.

6360

(5653)

NOTES:
1.

SCLK and SDAT are used for S3P7559 only.

Parentheses indicate pin number for 64 QFP package.

S3C7559/P7559

PRODUCT OVERVIEW

1-7

Table 1-1. S3C7559/P7559 Pin Descriptions (Continued)

Pin Name

Pin Type

Description

Number

Share Pin

P10.0P10.3

P11.0P11.3

I/O

Same as port 9.
Ports 10 and 11 can be paired to support 8-bit data
transfer.

1916

(129)

2320

(1613)

P12.0P12.3

I/O

4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-down resistors are software assignable;
pull-down resistors are automatically disabled for
output pins.

2724

(2017)

P13.0P13.2

I/O

3-bit I/O port; characteristics are same as port 9.

(6462)

DTMF

DTMF output.

31 (24)

SCK

I/O

Serial I/O interface clock signal

15 (8)

P0.0

I/O

Serial data output

14 (7)

P0.1

I/O

Serial data input

13 (6)

P0.2

BTCO

I/O

Basic timer clock output

12 (5)

P0.3

INT0, INT1

External interrupts. The triggering edge for INT0 and
INT1 is selectable. INT0 is synchronized to system
clock.

4, 3

(61, 60)

P1.0, P1.1

INT2

Quasi-interrupt with detection of rising edges

2 (59)

P1.2

INT4

External interrupt with detection of rising and falling
edges.

1 (58)

P1.3

TCLO0

I/O

Timer/counter 0 clock output

11 (4)

P2.0

TCLO1

I/O

Timer/counter 1 clock output

10 (3)

P2.1

CLO

I/O

Clock output

9 (2)

P2.2

BUZ

I/O

2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
the watch timer clock frequency of 32.768 kHz for
buzzer sound

8 (1)

P2.3

TCL0

I/O

External clock input for timer/counter 0

34 (27)

P3.0

TCL1

I/O

External clock input for timer/counter 1

33 (26)

P3.1

KS0KS3

KS4KS7

I/O

Quasi-interrupt inputs with falling edge detection

5148

(4441)

5552

(4845)

P6.0P6.3

P7.0P7.3

NOTE: Parentheses indicate pin number for 64 QFP package.

PRODUCT OVERVIEW

S3C7559/P7559

1-8

Table 1-1. S3C7559/P7559Pin Descriptions (Concluded)

Pin Name

Pin Type

Description

Number

Share Pin

Power supply

32 (25)

Ground

64 (57)

RESET

Reset signal

43 (36)

IN,

OUT

Crystal, ceramic, or R/C oscillator signal for main
system clock. (For external clock input, use X

and

input X

's reverse phase to X

OUT

)

45, 44

(38, 37)

IN,

OUT

Crystal oscillator signal for subsystem clock.
(For external clock input, use XT

and input XT

reverse phase to XT

OUT

)

46, 47

(39, 40)

TEST

Chip test input pin.
Hold GND when the device is operating.

30 (23)

NOTE: Parentheses indicate pin number for 64 QFP package.

S3C7559/P7559

PRODUCT OVERVIEW

1-9

Table 1-2. Overview of S3C7559/P7559 Pin Data

Pin Names

Share Pins

I/O Type

Reset Value

Circuit Type

P0.0P0.3

SCK

, SO, SI, BTCO

I/O

Input

D-4

P1.0P1.3

INT0, INT1, INT2,
INT4

Input

A-1

P2.0P2.3

TCLO0, TCLO1, CLO,
BUZ

I/O

Input

D-2

P3.0P3.1

TCL0, TCL1

I/O

Input

D-4

P3.2P3.3

I/O

Input

D-2

P4.0P4.3
P5.0P5.3

I/O

Input

E-2

P6.0P6.3
P7.0P7.3

KS0KS3
KS4KS7

I/O

Input

D-4

P8.0P8.3

I/O

Input

D-2

P9.0P9.3

I/O

Input

D-2

P10.0P10.3
P11.0P11.3

I/O

Input

D-2

P12.0P12.3

I/O

Input

D-6

P13.0P13.2

I/O

Input

D-2

DTMF

High impedence

G-6

, X

OUT

, XT

OUT

RESET

, V

PRODUCT OVERVIEW

S3C7559/P7559

1-10

PIN CIRCUIT DIAGRAMS

P-Channel

N-Channel

Figure 1-4. Pin Circuit Type A

Schmitt Trigger

Pull-Up
Resistor

Pull-Up
Resistor
Enable

P-Channel

Figure 1-5. Pin Circuit Type A-1

Schmitt Trigger

Pull-Up
Resistor

Figure 1-6. Pin Circuit Type B

P-Channel

N-Channel

Out

Output

DIsable

Data

Figure 1-7. Pin Circuit Type C

S3C7559/P7559

PRODUCT OVERVIEW

1-11

P-Channel

I/O

Output

DIsable

Data

Circuit

Type C

Pull-up
Enable

Figure 1-8. Pin Circuit Type D-2

P-Channel

I/O

Output

Disable

Data

Circuit

Type C

Pull-up
Enable

Schmitt Trigger

Figure 1-9. Pin Circuit Type D-4

I/O

Output

DIsable

Data

Circuit

Type C

Pull-down

Enable

Figure 1-10. Pin Circuit Type D-6

PNE

Output

Disable

Data

Pull-up
Enable

I/O

Figure 1-11. Pin Circuit Type E-2

S3C7559/P7559

ELECTRICAL DATA

14-1

ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7559 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:

Standard Electrical Characteristics

-- Absolute maximum ratings

-- D.C. electrical characteristics

-- System clock oscillator characteristics

-- I/O capacitance

-- A.C. electrical characteristics

-- Operating voltage range

Miscellaneous Timing Waveforms

-- A.C timing measurement point

-- Clock timing measurement at X

and X

OUT

-- TCL timing

-- Input timing for

RESET

-- Input timing for external interrupts

-- Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

-- RAM data retention supply voltage in stop mode

-- Stop mode release timing when initiated by

RESET

-- Stop mode release timing when initiated by an interrupt request

ELECTRICAL DATA

S3C7559/P7559

14-2

Table 14-1. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Units

Supply Voltage

0.3 to 6.5

Input Voltage

All I/O ports

0.3 to V

+ 0.3

Output Voltage

0.3 to V

+ 0.3

Output Current High

One I/O port active

All I/O ports active

Output Current Low

One I/O port active

+ 30 (Peak value)

+ 15

(note)

All I/O ports, total

+ 100 (Peak value)

+ 60

(note)

Operating Temperature

40 to + 85

Storage Temperature

stg

65 to + 150

NOTE: The values for Output Current Low ( I

) are calculated as Peak Value

Duty .

Table 14-2. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Input High
Voltage

IH1

All input pins except those
specified below for V

IH2

IH4

0.7 V

IH2

Ports 0, 1, 3, 6, 7, and

RESET

0.8 V

IH3

Ports 4 and 5 with pull-up resistors
assigned

0.7 V

IH4

IN,

OUT

and XT

0.1

Input Low
Voltage

IL1

All input pins except those
specified below for V

IL2

IL3

0.3 V

IL2

Ports 0, 1, 3, 6, 7, and

RESET

0.2 V

IL3

IN,

OUT

and XT

0.1

S3C7559/P7559

ELECTRICAL DATA

14-3

Table 14-2. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Output High
Voltage

= 1 mA Ports except 1

1.0

Output Low
Voltage

OL1

= 4.5 V to 5.5 V

= 15 mA Ports 4,5 only

= 1.8 to 5.5 V, I

= 1.6mA

0.4

OL2

= 4.5 V to 5.5 V

= 4mA all out Ports except ports 4,5

= 1.8 to 5.5 V, I

= 1.6mA

0.4

Input High
Leakage
Current

LIH1

= V

All input pins except those specified
below for I

LIH2

= V

IN,

OUT

and XT

Input Low
Leakage
Current

LIL1

VI = 0 V
All input pins except below and

RESET

- 3

LIL2

VI = 0 V

IN,

OUT

and XT

- 20

Output High
Leakage
Current

LOH

= V

All output pins

Output Low
Leakage
Current

LOL

= 0 V

All output pins

- 3

Pull-Up
Resistor

= 5 V; V

= 0 V

except

RESET

100

= 3 V

200

= 5 V; V

= 0 V;

RESET

100

212

400

= 3 V

200

441

800

Pull-Down
Resistor

= 5 V; V

= V

; Port 12

100

= 3 V

200

ELECTRICAL DATA

S3C7559/P7559

14-4

Table 14-2. D.C. Electrical Characteristics (Concluded)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply
Current

(1)

DD1

(DTMF ON)

Run mode; V

= 5.0 V

10%

3.58 MHz Crystal oscillator; C1 = C2 = 22 pF

3.0

5.0

= 3 V ± 10%

1.6

3.0

DD2

Run mode; V

= 5.0 V

10%

6.0 MHz

2.7

8.0

(DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF

3.58 MHz

2.0

4.0

= 3 V

10%

6.0 MHz

1.3

4.0

3.58 MHz

0.9

2.3

DD3

Idle mode; V

= 5 V ± 10%

6.0 MHz

0.8

2.5

3.58 MHz

0.7

1.8

= 3 V ± 10%

6.0 MHz

0.3

1.5

3.58 MHz

0.2

1.0

DD4

Run mode; V

= 3.0 V

10%

32 kHz Crystal oscillator

12.5

DD5

Idle mode; V

= 3.0 V

10%

32 kHz Crystal oscillator

4.5

DD6

Stop mode; V

= 5 V ± 10%

SCMOD =
0000B

1.9

Stop mode; V

= 3 V ± 10%

XT = 0V

0.6

Stop mode; V

= 5 V ± 10%

SCMOD =
0100B

0.2

Stop mode; V

= 3 V ± 10%

0.1

Row Tone
Level

(2)

ROW

= 2.0 V to 5.5 V

=12 K

; Temp = 30 to 60

dBV

Ratio of
Column to
Row Tone

(2)

= 2.0 V to 5.5 V

= 12 K

; Temp = 30 to 60

Distortion

(2)

(Dual tone)

THD

= 2.0 V to 5.5 V

1 MHz band, R

= 12 K

Temp = 30 to 60

NOTES:
1.

D.C. electrical values for Supply Current (I

DD1

to I

DD3

) do not include current drawn through internal pull-up resistors.

DTMF electrical characteristics.

For D.C. electrical values, the power control register (PCON) must be set to 0011B.

S3C7559/P7559

ELECTRICAL DATA

14-5

Table 14-3. Main System Clock Oscillator Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Ceramic
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

Stabilization time

(2)

= 3 V

Crystal
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

Stabilization time

(2)

= 3 V

External
Clock

OUT

input frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

input high and low

level width (t

XH,

)

83.3

1250

NOTES:
1.

Oscillation frequency and X

input frequency data are for oscillator characteristics only.

Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is
terminated.

ELECTRICAL DATA

S3C7559/P7559

14-6

Table 14-4. Recommended Oscillator Constants

= 40

C to + 85

Manufacturer

Series

Number

(1)

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

MIN

MAX

TDK

FCR

3.58 MHz6.0 MHz

2.0

5.5

Leaded Type

FCR

MC5

3.58 MHz6.0 MHz

(2)

2.0

5.5

On-chip C
Leaded Type

CCR

MC3

3.58 MHz6.0 MHz

(3)

2.0

5.5

On-chip C
SMD Type

NOTES:
1.

Please specify normal oscillator frequency.

On-chip C: 30pF built in.

On-chip C: 38pF built in.

S3C7559/P7559

ELECTRICAL DATA

14-7

Table 14-5. Subsystem Clock Oscillator Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Oscillato

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Crystal
Oscillator

OUT

Oscillation frequency

(1)

32.76

kHz

Stabilization time

(2)

= 2.7 V to 5.5 V

1.0

= 1.8 V to 5.5 V

External
Clock

OUT

input frequency

(1)

100

kHz

input high and low

level width (t

XH,

)

µs

NOTES:
1.

Oscillation frequency and XT

input frequency data are for oscillator characteristics only.

Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is
terminated.

Table 14-6. Input/Output Capacitance

= 25

C, V

0 V )

Parameter

Symbol

Condition

Min

Typ

Max

Units

Input
Capacitance

f = 1 MHz; Unmeasured pins
are returned to V

Output
Capacitance

OUT

I/O Capacitance

ELECTRICAL DATA

S3C7559/P7559

14-8

Table 14-7. A.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Instruction Cycle
Time

(1)

= 2.7 V to 5.5 V

0.67

µs

= 1.8 V to 5.5 V

1.33

TCL0, TCL1 Input
Frequency

TI0,

TI1

= 2.7 V to 5.5 V

1.5

MHz

= 1.8 V to 5.5 V

MHz

TCL0, TCL1 Input
High, Low Width

TIH0,

TIL0

TIH1,

TIL1

= 2.7 V to 5.5 V

0.48

µs

= 1.8 V to 5.5 V

1.8

SCK

Cycle Time

KCY

= 2.7 V to 5.5 V

External

SCK

source

800

Internal

SCK

source

670

= 1.8 V to 5.5 V

External

SCK

source

3200

Internal

SCK

source

3800

SCK

High, Low

Width

KH,

= 2.7 V to 5.5 V

External

SCK

source

335

Internal

SCK

source

KCY

250

= 1.8 V to 5.5 V

External

SCK

source

1600

Internal

SCK

source

KCY

2150

SI Setup Time to

SCK

High

SIK

= 2.7 V to 5.5 V

External

SCK

source

100

Internal

SCK

source

150

= 1.8 V to 5.5 V

External

SCK

source

150

Internal

SCK

source

500

SI Hold Time to

SCK

High

KSI

= 2.7 V to 5.5 V

External

SCK

source

400

Internal

SCK

source

400

= 1.8 V to 5.5 V

External

SCK

source

600

Internal

SCK

source

500

S3C7559/P7559

ELECTRICAL DATA

14-9

Table 14-7. A.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Output Delay for

SCK

to SO

KSO

(note)

= 2.7 V to 5.5 V

External

SCK

source

300

Internal

SCK

source

250

= 1.8 V to 5.5 V

External

SCK

source

1000

Internal

SCK

source

1000

Interrupt Input
High, Low Width

INTH,

INTL

INT0, INT1, INT2, INT4, KS0KS7

µs

RESET

Input

Low Width

RSL

Input

µs

NOTE: R (1 k

) and C (100 pF) are the load resistance and load capacitance of the SO output line.

1.5 MHz

CPU Clock

1.05

MHz

0.75 MHz

15.625 kHz

Main Oscillator Frequency
(Divided by 4)

4.2 MHz

3 MHz

6 MHz

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)

2.7

1.8

Figure 14-1. Standard Operating Voltage Range

ELECTRICAL DATA

S3C7559/P7559

14-10

Table 14-8. RAM Data Retention Supply Voltage in Stop Mode

= 40

C to + 85

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Data retention supply voltage

DDDR

1.8

5.5

Data retention supply current

DDDR

= 1.5 V

0.1

µA

Release signal set time

SREL

µs

Oscillator stabilization
wait time

(1)

WAIT

Released by

RESET

/fx

Released by interrupt

(2)

NOTES:
1.

During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.

Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

S3C7559/P7559

ELECTRICAL DATA

14-11

TIMING WAVEFORMS

Execution of

STOP Instrction

Internal

RESET

Operation

~ ~

DDDR

~ ~

Stop Mode

Idle Mode

Operating Mode

Data Retention Mode

SREL

WAIT

RESET

Figure 14-2. Stop Mode Release Timing When Initiated by

RESET

Execution of

STOP Instrction

DDDR

~ ~

Data Retention

Normal
Operating
Mode

~ ~

Stop Mode

Idle Mode

SREL

WAIT

Power-down Mode Terminating
(Interrupt Request)

Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request

ELECTRICAL DATA

S3C7559/P7559

14-12

0.8 V

0.2 V

0.8 V

0.2 V

Measurement

Points

Figure 14-4. A.C. Timing Measurement Points (Except for X

and XT

)

1/fx

- 0.1 V

0.1 V

Figure 14-5. Clock Timing Measurement at X

(XT

)

TCL

TIH

TIL

1/f

0.8 V

0.2 V

Figure 14-6. TCL0/1 Timing

S3C7559/P7559

MECHANICAL DATA

15-1

MECHANICAL DATA

This section contains the following information about the device package:

-- Package dimensions in millimeters

-- Pad diagram

64-QFP-1420F

#64

NOTE: Dimensions are in millimeters.

20.00

± 0.2

14.00

± 0.2

17.90

± 0.3

23.90

± 0.3

(1.00)

0.80 ± 0.20

0.05-0.25

2.65

± 0.10

3.00 MAX

0.15

+0.10

-0.05

0-8

1.00

0.15 MAX

0.40+0.10

-0.05

0.80

± 0.20

0.10 MAX

Figure 15-1. 64-QFP-1420F Package Dimensions

S3C7559/P7559

S3P7559 OTP

16-1

S3P7559OTP

OVERVIEW

The S3P7559 single-chip CMOS microcontroller is the OTP (One Time Programmable)

version of the S3C7559

microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data
format.

The S3P7559 is fully compatible with the S3C7559, both in function and in pin configuration. Because of its
simple programming requirements, the S3P7559 is ideal for use as an evaluation chip for the S3C7559.

S3P7559 OTP

S3C7559/P7559

16-2

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P13.2
P13.1
P13.0

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1
P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/SCK

P10.3
P10.2
P10.1
P10.0
P11.3
P11.2
P11.1
P11.0
P12.3
P12.2
P12.1
P12.0

SDAT/P3.3
SCLK/P3.2

/TEST

DTMF

DD/

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

SS/

P9.0
P9.1
P9.2
P9.3
P8.0
P8.1
P8.2
P8.3
P7.0/KS4
P7.1/KS5
P7.2/KS6
P7.3/KS7
P6.0/KS0
P6.1/KS1
P6.2/KS2
P6.3/KS3
XT

OUT

RESET

P5.0
P5.1
P5.2
P5.3
P4.0
P4.1
P4.2
P4.3
P3.0/TCL0
P3.1/TCL1

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

NOTE:

The bold indicate a OTP pin name.

S3P7559

(64-SDIP-750)

Figure 16-1. S3P7559 Pin Assignments (64-SDIP)

S3C7559/P7559

S3P7559 OTP

16-3

P8.0
P9.3
P9.2
P9.1
P9.0

SS/

P1.3/INT4
P1.2/INT2
P1.1/INT1
P1.0/INT0

P13.2
P13.1
P13.0

32
31
30
29
28
27
26
25
24
23
22
21
20

52
53
54
55
56
57
58
59
60
61
62
63
64

P8.1

P8.2

P8.3

P7.0/KS4

P7.1/KS5

P7.2/KS6

P7.3/KS7

P6.0/KS0

P6.1/KS1

P6.2/KS2

P6.3/KS3

OUT

RESET

RESET
RESET

P5.0

P5.1

P5.2

P2.3/BUZ

P2.2/CLO

P2.1/TCLO1

P2.0/TCLO0

P0.3/BTCO

P0.2/SI

P0.1/SO

P0.0/

SCK

P10.3

P10.2

P10.1

P10.0

P11.3

P11.2

P11.1

P11.0

P12.3

P12.2

P12.1

P5.3
P4.0
P4.1
P4.2
P4.3
P3.0/TCL0
P3.1/TCL1
V

DD/

DTMF
TEST/V

P3.2/SCLK
P3.3/SDAT
P12.0

S3P7559

(64-QFP-1420F)

NOTE:

The bold indicate a OTP pin name.

Figure 16-2. S3P7559 Pin Assignments (64-QFP)

S3P7559 OTP

S3C7559/P7559

16-4

Table 16-1. Descriptions of Pins Used to Read/Write the EPROM

Pin Name

During Programming

Pin No.

I/O

Function

SDAT

28 (21)

I/O

Serial data pin. Output port when reading and input port when
writing. Can be assigned as a Input/push-pull output port.

SCLK

29 (22)

Serial clock pin. Input only pin.

(TEST)

30 (23)

Power supply pin for EPROM cell writing (indicates that OTP
enters into the writing mode). When 12.5 V is applied, OTP is
in writing mode and when 5 V is applied, OTP is in reading
mode. (Option)
Hold GND when OTP is operating.

RESET

43 (36)

Chip initialization

32 (25) /

64 (57)

Logic power supply pin. V

should be tied to + 5 V during

programming.

NOTE: Parentheses indicate pin number for 64 QFP package.

Table 16-2. Comparison of S3P7559 and S3C7559 Features

Characteristic

S3P7559

S3C7559

Program Memory

32 K byte EPROM

32 K byte mask ROM

Operating Voltage (V

)

1.8 V to 5.5 V

OTP Programming Mode

= 5 V, V

(TEST) = 12.5V

Pin Configuration

64 SDIP/QFP

EPROM Programmability

User Program 1 time

Programmed at the factory

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the V

(TEST) pin of the S3P7559, the EPROM programming mode is entered.

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 16-3 below.

Table 16-3. Operating Mode Selection Criteria

(TEST)

REG/

MEM

Address

(A15A0)

Mode

5 V

0000H

EPROM read

12.5V

0000H

EPROM program

12.5V

0000H

EPROM verify

12.5V

0E3FH

EPROM read protection

NOTE: "0" means Low level; "1" means High level.

S3C7559/P7559

S3P7559 OTP

16-5

Table 16-4. Absolute Maximum Ratings

= 25

Parameter

Symbol

Conditions

Rating

Units

Supply Voltage

0.3 to 6.5

Input Voltage

All I/O ports

0.3 to V

+ 0.3

Output Voltage

0.3 to V

+ 0.3

Output Current High

One I/O port active

All I/O ports active

Output Current Low

One I/O port active

+ 30 (Peak value)

+ 15

(note)

All I/O ports, total

+ 100 (Peak value)

+ 60

(note)

Operating Temperature

40 to + 85

Storage Temperature

stg

65 to + 150

NOTE: The values for Output Current Low ( I

) are calculated as Peak Value

Duty .

Table 16-5. D.C. Electrical Characteristics

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Input High
Voltage

IH1

All input pins except those
specified below for V

IH2

IH4

0.7 V

IH2

Ports 0, 1, 3, 6, 7, and

RESET

0.8 V

IH3

Ports 4 and 5 with pull-up resistors
assigned

0.7 V

IH4

IN,

OUT

and XT

0.1

Input Low
Voltage

IL1

All input pins except those
specified below for V

IL2

IL3

0.3 V

IL2

Ports 0, 1, 3, 6, 7, and

RESET

0.2 V

IL3

IN,

OUT

and XT

0.1

S3P7559 OTP

S3C7559/P7559

16-6

Table 16-5. D.C. Electrical Characteristics (Continued)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Output High
Voltage

= 1 mA Ports except 1

1.0

Output Low
Voltage

OL1

= 4.5 V to 5.5 V

= 15 mA Ports 4,5 only

= 2.0 to 5.5 V, I

= 1.6mA

0.4

OL2

= 4.5 V to 5.5 V

= 4mA all out Ports except ports 4,5

= 2.0 to 5.5 V, I

= 1.6mA

0.4

Input High
Leakage
Current

LIH1

= V

All input pins except those specified
below for I

LIH2

= V

, X

OUT

and XT

Input Low
Leakage
Current

LIL1

= 0 V

All input pins except below and

RESET

- 3

LIL2

= 0 V

, X

OUT

and XT

Output High
Leakage
Current

LOH

= V

All output pins

Output Low
Leakage
Current

LOL

= 0 V

All output pins

Pull-up
Resistor

= 5 V; V

= 0 V

except

RESET

100

= 3 V

200

= 5 V; V

= 0 V;

RESET

100

212

400

= 3 V

200

441

800

Pull-Down

= 5 V ; V

= V

; Port 12

100

Resistor

= 3 V

200

S3C7559/P7559

S3P7559 OTP

16-7

Table 16-5. D.C. Electrical Characteristics (Concluded)

= 40

C to + 85

C, V

= 1.8 V to 5.5 V)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply
Current

(1)

DD1

(DTMF ON)

Run mode; V

= 5.0 V

10%

3.58 MHz Crystal oscillator; C1 = C2 = 22 pF

3.0

5.0

= 3 V ± 10%

1.6

3.0

DD2

Run mode; V

= 5.0 V

10%

6.0 MHz

2.7

8.0

(DTMF OFF) Crystal oscillator; C1 = C2 = 22 pF

3.58 MHz

2.0

4.0

= 3 V

10%

6.0 MHz

1.3

4.0

3.58 MHz

0.9

2.3

DD3

Idle mode; V

= 5 V ± 10%

6.0 MHz

0.8

2.5

3.58 MHz

0.7

1.8

= 3 V ± 10%

6.0 MHz

0.3

1.5

3.58 MHz

0.2

1.0

DD4

Run mode; V

= 3.0 V

10%

32 kHz Crystal oscillator

12.5

DD5

Idle mode; V

= 3.0 V

10%

32 kHz Crystal oscillator

4.5

DD6

Stop mode; V

= 5 V ± 10%

SCMOD =
0000B

1.9

Stop mode; V

= 3 V ± 10%

XT = 0 V

0.6

Stop mode; V

= 5 V ± 10%

SCMOD =

0.2

Stop mode; V

= 3 V ± 10%

0100B

0.1

Row Tone
Level

(2)

ROW

= 2.0 V to 5.5 V

=12 K

; Temp = 30 to 60

dBV

Ratio of
Column to
Row Tone

(2)

= 2.0 V to 5.5 V

=12 K

; Temp = 30 to 60

Distortion

(2)

(Dual tone)

THD

= 2.0 V to 5.5 V

1 MHz band, R

= 12 K

Temp = 30 to 60

NOTES:
1.

D.C. electrical values for Supply Current (I

DD1

to I

DD3

) do not include current drawn through internal pull-up resistors.

DTMF electrical characteristics.

For D.C. electrical values, the power control register (PCON) must be set to 0011B.

S3P7559 OTP

S3C7559/P7559

16-8

Table 16-6. Main System Clock Oscillator Characteristics

= 40

C + 85

C, V

= 1.8 V to 5.5 V)

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Ceramic
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

3.0

Stabilization time

(2)

= 3 V

Crystal
Oscillator

OUT

Oscillation frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

3.0

Stabilization time

(2)

= 3 V

External
Clock

OUT

input frequency

(1)

= 2.7 V to 5.5 V

0.4

6.0

MHz

= 1.8 V to 5.5 V

0.4

3.0

input high and low

level width (t

XH,

)

83.3

1250

NOTES:
1.

Oscillation frequency and X

input frequency data are for oscillator characteristics only.

Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.

S3C7559/P7559

S3P7559 OTP

16-9

Table 16-7. Recommended Oscillator Constants

= 40

C + 85

C, V

= 1.8 V to 5.5 V)

Manufacturer

Series

Number

(1)

Frequency Range

Load Cap (pF)

Oscillator Voltage

Range (V)

Remarks

MIN

MAX

TDK

FCR

3.58 MHz6.0 MHz

2.0

5.5

Leaded Type

FCR

MC5

3.58 MHz6.0 MHz

(2)

2.0

5.5

On-chip C
Leaded Type

CCR

MC3

3.58 MHz6.0 MHz

(3)

2.0

5.5

On-chip C
SMD Type

NOTES:
1.

Please specify normal oscillator frequency.

On-chip C: 30pF built in.

On-chip C: 38pF built in.

Table 16-8. Subsystem Clock Oscillator Characteristics

= 40

C + 85

C, V

= 1.8 V to 5.5 V)

Oscillator

Clock

Configuration

Parameter

Test Condition

Min

Typ

Max

Units

Crystal
Oscillator

OUT

Oscillation frequency

(1)

32.768

kHz

Stabilization time

(2)

= 2.7 V to 5.5 V

1.0

= 1.8 V to 5.5 V

External
Clock

OUT

input frequency

(1)

100

kHz

input high and low

level width (t

XH,

)

µs

NOTES:
1.

Oscillation frequency and XT

input frequency data are for oscillator characteristics only.

Stabilization time is the interval required for oscillating stabilization after a power-on occurs or when stop mode is
terminated.

S3P7559 OTP

S3C7559/P7559

16-10

Table 16-9. Input/Output Capacitance

= 25

C, V

= 0 V )

Parameter

Symbol

Condition

Min

Typ

Max

Units

Input
Capacitance

f = 1 MHz; Unmeasured pins
are returned to V

Output
Capacitance

OUT

I/O Capacitance

1.5 MHz

CPU Clock

1.05

MHz

0.75 MHz

15.625 kHz

Main Oscillator Frequency
(Divided by 4)

4.2 MHz

3 MHz

6 MHz

Supply Voltage (V)

CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)

2.7

1.8

Figure 16-3. Standard Operating Voltage Range

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3P7559

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3P7559

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: S3P7559