S524AD0XD1/D0XF1
128K/256K-bit
Serial EEPROM
for Low Power
Data Sheet
8-1
OVERVIEW
The S524AD0XD1/D0XF1 serial EEPROM has a 128K/256K-bit (16,384/32,768 bytes) capacity, supporting the
standard I
2
CTM-bus serial interface. It is fabricated using Samsung's most advanced CMOS technology. It has
been developed for low power and low voltage applications (1.8 V to 5.5 V). One of its major feature is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 64 bytes of data into
the EEPROM in a single write operation. Another significant feature of the S524AD0XD1/D0XF1 is its support for
fast mode and standard mode.
FEATURES
I
2
C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
128K/256K-bit (16,384/32,768 bytes) storage
area
64-byte page buffer
Typical 3 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
500,000 erase/write cycles
50 years data retention
Operating Characteristics
Operating voltage
-- 1.8 V to 5.5 V
Operating current
-- Maximum write current: < 3 mA at 5.5 V
-- Maximum read current: < 400
A at 5.5 V
-- Maximum stand-by current: < 1
A at 5.5 V
Operating temperature range
-- 25C to + 70C (commercial)
-- 40C to + 85C (industrial)
Operating clock frequencies
-- 400 kHz at standard mode
-- 1 MHz at fast mode
Electrostatic discharge (ESD)
-- 5,000 V (HBM)
-- 500 V (MM)
Packages
8-pin DIP, and TSSOP
S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET
8-2
Start/Stop
Logic
Slave Address
Comparator
Word Address
Pointer
Row
decoder
EEPROM
Cell Array
16,384 x 8 bits
32,768 x 8 bits
HV Generation
Timing Control
Control Logic
Column Decoder
Data Register
D
OUT
and ACK
SCL
WP
SDA
A0
A1
A2
Figure 8-1. S524AD0XD1/D0XF1 Block Diagram
DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM
8-3
S524AD0XD1/D0XF1
V
CC
WP
SCL SDA
A0
A1
A2
V
SS
NOTE:
The S524AD0XD1/D0XF1 is available
in 8-pin DIP, and TSSOP package.
Figure 8-2. Pin Assignment Diagram
Table 8-1. S524AD0XD1/D0XF1 Pin Descriptions
Name
Type
Description
Circuit
Type
A0, A1, A2
Input
Input pins for device address selection. To configure a device address,
these pins should be connected to the V
CC
or V
SS
of the device.
These pins are internally pulled down to V
SS.
1
V
SS
Ground pin.
SDA
I/O
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to V
DD.
3
SCL
Input
Schmitt trigger input pin for serial clock input.
2
WP
Input
Input pin for hardware write protection control. If you tie this pin to V
CC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to V
SS
, the write function is enabled.
This pin is internally pulled down to V
SS.
1
V
CC
Single power supply.
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
S524AD0XD1/D0XF1 SERIAL EEPROM DATA SHEET
8-4
A0, A1,
A2, WP
Figure 8-3. Pin Circuit Type 1
SCL
Noise
Filter
Figure 8-4. Pin Circuit Type 2
SDA
V
SS
Data Out
Noise
Filter
Data In
Figure 8-5. Pin Circuit Type 3
DATA SHEET S524AD0XD1/D0XF1 SERIAL EEPROM
8-5
FUNCTION DESCRIPTION
I
2
C-BUS INTERFACE
The S524AD0XD1/D0XF1 supports the I
2
C-bus serial interface data transmission protocol. The two-wire bus
consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected
to V
CC
by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a "transmitter" and any device that gets data from the bus is
a "receiver." The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Using the A0, A1, and A2 input pins, up to eight S524AD0XD1/D0XF1 devices can be
connected to the same I
2
C-bus as slaves (see Figure 8-6). Both the master and slaves can operate as a
transmitter or a receiver, but the master device determines which bus operating mode would be active.
SDA
Bus Master
(Transmitter/
Receiver)
MCU
S524AD0XD1/
D0XF1
Tx/Rx
A0 A1 A2
Slave 1
To V
CC
or V
SS
S524AD0XD1/
D0XF1
Tx/Rx
A0 A1 A2
Slave 2
To V
CC
or V
SS
S524AD0XD1/
D0XF1
Tx/Rx
A0 A1 A2
Slave 3
To V
CC
or V
SS
S524AD0XD1/
D0XF1
Tx/Rx
A0 A1 A2
Slave 8
To V
CC
or V
SS
R
V
CC
R
V
CC
SCL
Figure 8-6. Typical Configuration
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