S524C20D11/20D21/80D41/80D81
1K/2K/4K/8K-bit
Serial EEPROM
Data Sheet
3-1
OVERVIEW
The S524C20D11/20D21/80D41/80D81 serial EEPROM has a 1,024/2,048/4,096/8,192-bit (128/256/512/1,024-
byte) capacity, supporting the standard I
2
CTM-bus serial interface. It is fabricated using Samsung's most
advanced CMOS technology. One of its major feature is a hardware-based write protection circuit for the entire
memory area. Hardware-based write protection is controlled by the state of the write-protect (WP) pin. Using one-
page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another
significant feature of the S524C20D11/20D21/80D41/80D81 is its support for fast mode and standard mode.
FEATURES
I
2
C-Bus Interface
Two-wire serial interface
Automatic word address increment
EEPROM
1K/2K/4K/8K-bit (128/256/512/1,024-byte)
storage area
16-byte page buffer
Typical 3.5 ms write cycle time with
auto-erase function
Hardware-based write protection for the entire
EEPROM (using the WP pin)
EEPROM programming voltage generated
on chip
1,000,000 erase/write cycles
100 years data retention
Operating Characteristics
Operating voltage
-- 2.5 V to 5.5 V (write)
-- 2.2 V to 5.5 V (read)
Operating current
-- Maximum write current: < 3 mA at 5.5 V
-- Maximum read current: < 200
A at 5.5 V
-- Maximum stand-by current: < 5
A at 3.3 V
Operating temperature range
-- 25C to + 70C (commercial)
-- 40C to + 85C (industrial)
Operating clock frequencies
-- 100 kHz at standard mode
-- 400 kHz at fast mode
Electrostatic discharge (ESD)
-- 3,000 V (HBM)
-- 300 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET
3-2
Start/Stop
Logic
Slave Address
Comparator
Word Address
Pointer
Row
decoder
EEPROM
Cell Array
128 x 8 bits
256 x 8 bits
512 x 8 bits
1024 x 8 bits
HV Generation
Timing Control
Control Logic
Column Decoder
Data Register
D
OUT
and ACK
SCL
WP
SDA
A0
A1
A2
Figure 3-1. S524C20D11/20D21/80D41/80D81 Block Diagram
DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM
3-3
S524C20D11/20D21/
80D41/80D81
V
CC
WP
SCL
SDA
A0
A1
A2
V
SS
NOTE:
The S524C20D11/20D21/80D41/80D81 is available
in 8-pin DIP, SOP, and TSSOP package.
Figure 3-2. Pin Assignment Diagram
Table 3-1. S524C20D11/20D21/80D41/80D81 Pin Descriptions
Name
Type
Description
Circuit
Type
A0, A1, A2
Input
Input pins for device address selection. To configure a device address,
these pins should be connected to the V
CC
or V
SS
of the device.
1
V
SS
Ground pin.
SDA
I/O
Bi-directional data pin for the I
2
C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor must
be connected to V
CC.
Typical values for this pull-up resistor are 4.7 k
(100 kHz) and 1 k
(400 kHz).
3
SCL
Input
Schmitt trigger input pin for serial clock input.
2
WP
Input
Input pin for hardware write protection control. If you tie this pin to V
CC,
the write function is disabled to protect previously written data in the
entire memory; if you tie it to V
SS
, the write function is enabled.
1
V
CC
Single power supply.
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
S524C20D11/20D21/80D41/80D81 SERIAL EEPROM DATA SHEET
3-4
A0, A1,
A2, WP
Figure 3-3. Pin Circuit Type 1
SCL
Noise
Filter
Figure 3-4. Pin Circuit Type 2
SDA
V
SS
Data Out
Noise
Filter
Data In
Figure 3-5. Pin Circuit Type 3
DATA SHEET S524C20D11/20D21/80D41/80D81 SERIAL EEPROM
3-5
FUNCTION DESCRIPTION
I
2
C-BUS INTERFACE
The S524C20D11/20D21/80D41/80D81 supports the I
2
C-bus serial interface data transmission protocol. The two-
wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be
connected to V
CC
by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the "transmitter" and any device that gets data from the bus
is the "receiver." The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524C20D11/20D21 (four
S524C80D41, two for S524C80D81) devices can be connected to the same I
2
C-bus as slaves (see Figure 3-6).
Both the master and slaves can operate as transmitter or receiver, but the master device determines which bus
operating mode would be active.
SDA
Bus Master
(Transmitter/
Receiver)
MCU
S524C20D21
Tx/Rx
A0 A1 A2
Slave 1
To V
CC
or V
SS
S524C20D21
Tx/Rx
A0 A1 A2
Slave 2
To V
CC
or V
SS
S524C20D21
Tx/Rx
A0 A1 A2
Slave 3
To V
CC
or V
SS
S524C20D21
Tx/Rx
A0 A1 A2
Slave 8
To V
CC
or V
SS
R
V
CC
R
V
CC
SCL
NOTES:
1. The A0 does not affect the device address of the S524C80D41.
2. The A0, A1 do not affect the device address of the S524C80D81.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I
2
C-Bus)
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