1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
S5F333SZ03
1
INTRODUCTION
The S5F333SZ03 is an interline transfer progressive scan
type square pixel CCD area image sensor of 1/3 inch optical
format developed for VGA. The electron accumulation time
can be changed by the electronic shutter function and it is
possible to obtain a frame still image without a mechanical
shutter. High resolution and good color reproduction are
accomplished by using mosaic R, G, B primary color filters. It
is suitable for still cameras and PC input cameras.
FEATURES
330K Pixel Progressive-scan CCD
High Vertical Resolution (480 TV lines)
Square Unit Pixel for VGA Format
No Substrate Voltage Adjustment
No DC bias on Reset Clock
R, G, B Mosaic On-Chip Color Filter
Optical Size 1/3 inch Format
Variable Speed Electronic Shutter
Low Smear
High Antiblooming
Horizontal Register 5V Drive
STRUCTURE
Number of Total Pixels:
692(H)
504(V)
Number of Effective Pixels:
659(H)
494(V)
Chip Size:
6.00mm(H)
4.95mm(V)
Unit Pixel Size:
7.40
m(H)
7.40
m(V)
Optical Blacks & Dummies:
Refer to Figure Below
16Pin Cer - DIP
ORDERING INFORMATION
Device
Package
Operating
S5F333SZ03-LBB0
16Pin Cer - DIP
-10
C
-
+60
C
16 2
659
31
2
4
9
4
8
5
H-CCD
V
-
C
C
D
OUTPUT
Dummy Pixels
Optical Black Pixels
Effective Pixels
Effective
Imaging
Area
(Top view)
S5F333SZ03 1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
2
BLOCK DIAGRAM
PIN DESCRIPTION
Figure 1. Block Diagram
Table 1. Pin Description
Pin
Symbol
Description
Pin
Symbol
Description
1
V3
Vertical CCD transfer clock 3
9
V
DD
Output stage drain bias
2
V2
Vertical CCD transfer clock 2
10
NC
No connection
3
V1
Vertical CCD transfer clock 1
11
GND
Ground
4
NC
No connection
12
SUB
Substrate clock
5
GND
Ground
13
V
L
Protection circuit bias
6
NC
No connection
14
RS
Reset gate clock
7
GND
Ground
15
H1
Horizontal CCD transfer
8
V
OUT
Signal output
16
H2
Horizontal CCD transfer
8
V
OUT
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
GND
NC
GND
NC
V1
V2
V3
V
DD
V
L
NC
H1
H2
RS
SUB
V
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t
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S
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R
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C
C
D
V
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t
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c
a
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S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
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r
t
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c
a
l
S
h
i
f
t
R
e
g
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s
t
e
r
C
C
D
V
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t
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c
a
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S
h
i
f
t
R
e
g
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s
t
e
r
C
C
D
Horizontal Shift Register CCD
G
R
B
G
B
G
G
G
G
G
G
G
B
B
B
B
B
B
R
R
G
G
R
G
R
R
G
G
GND
to substrate
(Top View)
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
S5F333SZ03
3
ABSOLUTE MAXIMUM RATINGS
(1)
NOTE:
1.
The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage or
temperature.
2.
V
DD
bias must be operated before reset pulse operation.
3.
Substrate DC bias(OFD bias) must be operated before horizontal, reset pulse operation.
Table 2. Absolute Maximum Ratings
Characteristics
Symbols
Min.
Max.
Unit
Substrate clock voltage
SUB
- GND
-0.3
40
V
SUB
- V
DD
-0.3
40
V
SUB
- V
OUT
-0.3
40
V
Supply voltage
V
DD
, V
OUT
- GND
-0.3
17
V
Vertical clock input voltage
V1
- V
L
-0.3
17
V
V2
,
V3
- V
L
-0.3
32
V
V1
-
SUB
-40
17
(2)
V
V2,
V3
-
SUB
-40
32
V
Horizontal clock input voltage
H1
,
H2
- GND
-0.3
17
V
H1
,
H2
- V
L
-0.3
17
V
H1
,
H2
-
SUB
-40
substrate DC bias
(3)
V
Output clock input voltage
RS
- V
L
-0.3
17
V
RS
-
SUB
-40
substrate DC bias
(2)
V
RS
- GND
-0.3
17
(2)
V
Protection circuit bias voltage
SUB
- V
L
-16
40
V
GND - V
L
-0.3
17
V
Operating temperature
T
OP
-10
60
C
Storage temperature
T
STG
-30
80
C
S5F333SZ03 1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
4
DC CHARACTERISTICS
NOTE: A DC bias (OFD bias) is generated within the CCD.
CLOCK VOLTAGE CONDITIONS
Table 3. DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Output stage drain bias
V
DD
14.55
15.0
15.45
V
Protection circuit bias voltage
V
L
The lowest vertical clock level
Substrate clock
SUB
NOTE
V
Output stage drain current
I
DD
5.0
mA
Table 4. Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Read-out clock voltage
V
VH2
, V
VH3
14.55
15.0
15.45
V
High
Vertical transfer clock voltage
V
VM1
~ V
VM3
-0.05
0.0
0.05
V
Middle
V
VL1
~ V
VL3
-8.0
-7.5
-7.0
V
Low
Horizontal transfer clock voltage
V
HH1
, V
HH2
4.75
5.0
5.25
V
High
V
HL1
, V
HL2
-0.05
0.0
0.05
V
Low
Charge reset clock voltage
V
RSH
4.75
5.0
5.25
V
High
V
RSL
-0.05
0.0
0.05
V
Low
Substrate clock voltage
V
SUB
21.5
22.5
23.5
V
Shutter
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
S5F333SZ03
5
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
Vertical Transfer Clock Waveform
0V
100%
90%
10%
0%
V
VH 2,
V
VH3
tr
twh
tf
V
VH
V
VHL
V
VH H
V
VHH
V
V HL
V
V H4
V
VL
V
VL H
V
VL L
V
VL 4
V 3
V
V HH
V
V HH
V
VH
V
VH L
V
VH L
V
VH2
V
VL
V
VL L
V
VL H
V
VL 2
V 2
V
VL 3
V
V HH
V
VL
V
VH L
V
V HL
V
VH3
V
VHH
V
VH
V
V L H
V
V L L
V 1
V
V H
= V
V H 2
V
V L
= (V
V L 1
+ V
V L 3
)/ 2
V
V
= V
V H n
- V
V L n
(n =1~3 )
V
V H H
= V
V H
+ 0 . 3 V
V
V H L
= V
V H
- 0 . 3 V
V
V L H
= V
V L
+ 0 . 3 V
V
V L L
= V
V L
- 0 . 3 V
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