1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
S5F518NZ03
1
INTRODUCTION
The S5F518NZ03 is an interline transfer CCD area image
sensor developed for NTSC 1/5 inch optical format PC
cameras, object detector and image pattern recognizer. High
sensitivity is achieved through the adoption of Ye, Cy, Mg and
G complementary color mosaic filter, on-chip micro lenses.
This chip features a field integration read out system and an
electronic shutter with variable charge storage time.
FEATURES
Optical Size 1/5 inch Format
Ye, Cy, Mg, G On-chip Complementary
Color Mosaic Filter
Horizontal Register 3.3V ~ 5V Drive
14pin Ceramic DIP Package
No Adjust Substrate Bias
Field Integration Read Out System
No DC Bias on Reset Gate
STRUCTURE
Number of Total Pixels:
381(H)
506(V)
Number of Effective Pixels:
362(H)
492(V)
Chip Size:
3.75mm(H)
3.30mm(V)
Unit Pixel Size:
8.10
m(H)
4.45
m(V)
Optical Blacks & Dummies:
Refer to Figure Below
Vertical 1 Line (Even Field Only)
14Pin Cer - DIP
ORDERING INFORMATION
Device
Package
Operating
S5F518NZ03-LEB0
14Pin Cer - DIP
-10
C
-
+60
C
14 2
362
17
2
4
9
2
1
2
V
-
C
C
D
OUTPUT
Dummy Pixels
Optical Black Pixels
Effective Pixels
Effective
Imaging
Area
H-CCD
S5F518NZ03 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
2
BLOCK DIAGRAM
PIN DESCRIPTION
Figure 1. Block Diagram
Table 1. Pin Description
Pin
Symbol
Description
Pin
Symbol
Description
1
V4
Vertical register transfer clock 4
8
V
DD
Output stage drain bias
2
V3
Vertical register transfer clock 3
9
GND
Ground
3
V2
Vertical register transfer clock 2
10
SUB
Substrate clock
4
V1
Vertical register transfer clock 1
11
V
L
Protection circuit bias
5
NC
No connection
12
RG
Reset gate clock
6
GND
Ground
13
H1
Horizontal CCD transfer clock 1
7
V
OUT
Signal output
14
H2
Horizontal CCD transfer clock 2
7
V
OUT
6
5
4
3
2
1
8
9
10
11
12
13
14
GND
NC
V1
V2
V3
V4
V
DD
V
L
GND
H1
H2
RG
SUB
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
V
e
r
t
i
c
a
l
S
h
i
f
t
R
e
g
i
s
t
e
r
C
C
D
Horizontal Shift Register CCD
Cy
Ye
Mg
Mg
Mg
Mg
Mg
Ye
Ye
Ye
Ye
Ye
Ye
Ye
G
G
G
G
Cy
Cy
Cy
Cy
Cy
G
Mg
G
Cy
Cy
(Top View)
1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
S5F518NZ03
3
ABSOLUTE MAXIMUM RATINGS
(NOTE)
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
Table 2. Absolute Maximum Ratings
Characteristics
Symbols
Min.
Max.
Unit
Substrate voltage
SUB - GND
-0.3
40
V
Vertical clock input voltage
V1
,
V3
, - GND
-0.3
30
V
V2
,
V4
- GND
-0.3
17
V
V1
,
V3
, - V
L
-0.3
30
V
V2
,
V4
- V
L
-0.3
17
V
V1
,
V2
,
V3
,
V4
- SUB
-40
10
V
Horizontal clock input voltage
V1
,
V2
,
- GND
-0.3
16
V
H1
,
H2
- V
L
-0.3
16
V
Voltage difference between vertical and
horizontal clock input pins
V1
, -
V3
-30
30
V
V2
, -
V4
-16
16
V
H1
,
H2
-16
16
V
H1
,
H2
-
V4
-16
16
V
Output clock input voltage
RG
- GND
-0.3
16
V
Protection circuit bias voltage
V
L
- SUB
-40
0.3
V
Operating temperature
T
OP
-10
60
C
Storage temperature
T
STG
-30
80
C
S5F518NZ03 1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
4
DC CHARACTERISTICS
CLOCK VOLTAGE CONDITIONS
Table 3. DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Remar
Output stage drain bias
V
DD
14.55
15.0
15.45
V
Reset gate voltage adjustment range
V
RGL
0
V
Protection circuit bias voltage
V
L
The lowest vertical clock level
Output stage drain current
I
DD
5
mA
Table 4. Clock Voltage Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Remark
Read-out clock voltage
V
VT
14.55
15.0
15.45
V
High level
Vertical transfer clock voltage
V
VM1
-
V
VM4
-0.05
0.0
0.05
V
V
VH
= (V
VH
1+V
VH2
)/2
V
VL1
-
V
VL4
-8.5
-8.0
-7.5
V
V
VH
= (V
VH
1+V
VH2
)/2
Horizontal transfer clock voltage
V
H
3.0
5.0
5.25
V
High
V
HL
-0.05
0.0
0.05
V
Low
Charge reset clock voltage
V
RG
4.75
5.0
5.25
V
High
V
RGLH -
V
RGLL
0.8
V
Low
Substrate clock voltage
V
SUB
21.5
22.5
23.5
V
Shutter
1/5 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
S5F518NZ03
5
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
Vertical Transfer Clock Waveform
0V
100%
90%
10%
0%
V
VH 1,
V
VH3
tr
twh
tf
V
V H 1
V
VH
V
V H H
V
VL L
V
VL
V
VL 1
V
VL H
V
V H L
V
V H L
V
V H H
V 1
V
VH
V
VHL
V
VH H
V
V HH
V
VHL
V
VH 4
V
VL
V
VL H
V
VL L
V
V L 4
V 4
V
VH H
V
VHH
V
VH
V
VHL
V
VHL
V
VH2
V
VL
V
VL L
V
VL H
V
VL 2
V 2
V
VL 3
V
VHH
V
VL
V
V HL
V
VH L
V
VH3
V
VH H
V
VH
V
VL H
V
VL L
V 3
V
V H
= ( V
V H 1
+ V
V H 2
)/ 2
V
V L
= (V
V L 3
+ V
V L 4
)/ 2
V
V
= V
V H n
- V
V L n
(n =1~4)
V
V H H
= V
V H
+ 0 . 3 V
V
V H L
= V
V H
- 0 . 3 V
V
V L H
= V
V L
+ 0 . 3 V
V
V L L
= V
V L
- 0 . 3 V
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