DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
1
DIGITAL SIGNAL PROCESSOR
The S5L9826F01 is a CMOS integrated circuit designed for the Digital
Audio Signal Processor for Compact Disc Player. It is a monolithic IC that
builts-in 16-bit Digital Analog Convertor, ESP Interface and Digital De-
emphasis additional conventional DSP function.
FEATURES
EFM data demodulation
Frame sync detection / protection / insertion
Powerful error correction (C1: 2 error; C2: 4 erasure)
Interpolation
8fs digital filter (51th+13th+9th)
Subcode data serial output
CLV servo controller
MICOM interface
Digital audio output
Digital de-emphasis
ESP interface
Built-in 16K SRAM
Built-in digital PLL
Double speed play available
Built-in 16-bit D/A converter
V
DD
= 5V
ORDERING INFORMATION
Device
Package
Tempe. Range
S5L9286F01-Q0R0
80-QFP-1420C
-20
o
C +75
o
C
80-QFP-1420C
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
3
PIN CONFIGURATION
S5L9286F01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AVDD1
DPDO
DPFIN
DPFOUT
CNTVOL
AVSS1
DATX
XIN
XOUT
WDCHO
LRCHO
ADATAO
DVSS1
BCKO
C2PO
VREFL2
VREFL1
AVDD2
RCHOUT
LCHOUT
AVSS2
VREFH1
VREFH2
EMPH
LKFS
S0S1
RESET
/ESP
SQCK
SQDT
SQOK
SBCK
SDAT
DVDD1
MUTE
MLT
MDAT
MCK
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
/PBCK
DVSS2
FSDW
ULKFS
/JIT
C4M
C16M
/WE
/CS
XTALSEL
FOK
CDROM
SRAM
TEST1
EFMI
ADATAI
/ISTAT
TRCNT
LOCK
PBFR
SMEF
SMON
DVDD2
SMDP
SMDS
BCKI
TESTV
DSPEED
LRCHI
S5L9286F01
DIGITAL SIGNAL PROCESSOR FOR CDP
4
PIN DESCRIPTION
PIN NO
SYMBOL
IO
DESCRIPTION
1
AVDD1
-
Analog VCC1
2
DPDO
O
Charge pump output for Digital PLL
3
DPFIN
I
Filter input for Digital PLL
4
DPFOUT
O
Filter output for Digital PLL
5
CNTVOL
I
VCO control voltage for Digital PLL
6
AVSS1
-
Analog Ground1
7
DATX
O
Digital Audio output data
8
XIN
I
X'tal oscillator input
9
XOUT
O
X'tal oscillator output
10
WDCHO
O
Word clock output of 48bit/Slot (88.2kHz)
11
LRCHO
O
Channel clock output of 48 bit/Slot (44.1kHz)
12
ADATAO
O
Serial audio data output of 48 bit/Slot (MSB first)
13
DVSS1
-
Digital Ground1
14
BCKO
O
Audio data bit clock output of 48 bit/Slot (2.1168MHz)
15
C2PO
O
C2 Pointer for output audio data
16
VREFL2
I
Input terminal2 of reference voltage "L" (Floating)
17
VREFL1
I
Input terminal1 of reference voltage "L" (GND connection)
18
AVDD2
-
Analog VCC2
19
RCHOUT
O
Right-Channel audio output through D/A converter
20
LCHOUT
O
Left-Channel audio output through D/A converter
21
AVSS2
-
Analog ground2
22
VREFH1
I
Input terminal1 of reference voltage "H" (VDD connection)
23
VREFH2
I
Input terminal2 of reference voltage "H" (Floating)
24
EMPH
O
H: Emphasis ON, L: Emphasis OFF
25
LKFS
O
The Lock Status output of frame sync
26
S0S1
O
Output of subcode sync signal(S0+S1)
27
RESET
I
System reset at "L"
28
/ESP
I
ESP function ON/OFF control ("L": ESP function ON, "H": ESP function OFF)
29
SQCK
I
Clock for output Subcode-Q data
DIGITAL SIGNAL PROCESSOR FOR CDP
S5L986F01
5
PIN DESCRIPTION (continued)
PIN NO
SYMBOL
IO
DESCRIPTION
30
SQDT
O
Serial output of Subcode-Q data
31
SQOK
O
The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q
32
SBCK
I
Clock for output subcode data
33
SDAT
O
Subcode serial data output
34
DVDD1
-
Digital VDD1
35
MUTE
I
Mute control input ("H": Mute ON)
36
MLT
I
Latch Signal Input from Micom (Schmit Trigger)
37
MDAT
I
Serial data input from Micom (Schmit Trigger)
38
MCK
I
Serial clock input from Micom (Schmit Trigger)
39
RD7
I/O
SRAM data I/O port 8 (MSB)
40
RD6
I/O
SRAM data I/O port 7
41
RD5
I/O
SRAM data I/O port 6
42
RD4
I/O
SRAM data I/O port 5
43
RD3
I/O
SRAM data I/O port 4
44
RD2
I/O
SRAM data I/O port 3
45
RD1
I/O
SRAM data I/O port 2
46
RD0
I/O
SRAM data I/O port 1 (LSB)
47
FLAG1
I/O
Monitoring output for error correction (RA0)
48
FLAG2
I/O
Monitoring output for error correction (RA1)
49
FLAG3
I/O
Monitoring output for error correction (RA2)
50
FLAG4
I/O
Monitoring output for error correction (RA3)
51
FLAG5
I/O
Monitoring output for error correction (RA4)
52
/PBCK
I/O
Output of VCO/2 (4.3218MHz) (RA5)
53
DVSS2
I/O
Digital ground 2
54
FSDW
I/O
Window or unprotected frame sync (RA6)
55
ULKFS
I/O
Frame sync protection state (RA7)
56
/JIT
I/O
Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)
57
C4M
I/O
Only monitoring signal (4.2336MHz) (RA9)
58
C16M
I/O
16.9344MHz signal output(RA10)
59
/WE
I/O
Terminal for test
60
/CS
I/O
Terminal for test
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