DIGITAL SIGNAL PROCESSOR FOR DISCMAN
S5L986F02
1
DIGITAL SIGNAL PROCESSOR
The S5L9826F02 is a CMOS integrated circuit designed for the Digital
Audio Signal Processor for Compact Disc Player. It is a monolithic IC that
builts-in 16-bit Digital Analog Convertor, ESP Interface and Digital De-
emphasis additional conventional DSP function.
FEATURES
EFM data demodulation
Frame sync detection / protection / insertion
Powerful error correction (C1: 2 error; C2: 4 erasure)
Interpolation
8fs digital filter (51th+13th+9th)
Subcode data serial output
CLV servo controller
MICOM interface
Digital audio output
Digital de-emphasis
ESP interface
Built-in 16K SRAM
Built-in digital PLL
Double speed play available
Built-in 16-bit D/A converter
V
DD
= 3.2 - 5.5V
ORDERING INFORMATION
Device
Package
Tempe. Range
S5L9286F02-T0R0
80-TQFP-1212
-20
o
C +75
o
C
80-TQFP-1212
S5L9286F02
DIGITAL SIGNAL PROCESSOR FOR DISCMAN
4
PIN DESCRIPTION
PIN NO
SYMBOL
IO
DESCRIPTION
1
DPDO
O
Charge pump output for Digital PLL
2
DPFIN
I
Filter input for Digital PLL
3
DPFOUT
O
Filter output for Digital PLL
4
CNTVOL
I
VCO control voltage for Digital PLL
5
AVSS1
-
Analog Ground1
6
DATX
O
Digital Audio output data
7
XIN
I
X'tal oscillator input
8
XOUT
O
X'tal oscillator output
9
WDCHO
O
Word clock output of 48bit/Slot (88.2kHz)
10
LRCHO
O
Channel clock output of 48 bit/Slot (44.1kHz)
11
ADATAO
O
Serial audio data output of 48 bit/Slot (MSB first)
12
DVSS1
-
Digital Ground1
13
BCKO
O
Audio data bit clock output of 48 bit/Slot (2.1168MHz)
14
C2PO
O
C2 Pointer for output audio data
15
VREFL2
I
Input terminal2 of reference voltage "L" (Floating)
16
VREFL1
I
Input terminal1 of reference voltage "L" (GND connection)
17
AVDD2
-
Analog VCC2
18
RCHOUT
O
Right-Channel audio output through D/A converter
19
LCHOUT
O
Left-Channel audio output through D/A converter
20
AVSS2
-
Analog ground2
21
VREFH1
I
Input terminal1 of reference voltage "H" (VDD connection)
22
VREFH2
I
Input terminal2 of reference voltage "H" (Floating)
23
EMPH
O
H: Emphasis ON, L: Emphasis OFF
24
LKFS
O
The Lock Status output of frame sync
25
S0S1
O
Output of subcode sync signal(S0+S1)
26
RESET
I
System reset at "L"
27
/ESP
I
ESP function ON/OFF control ("L": ESP function ON, "H": ESP function OFF)
28
SQCK
I
Clock for output Subcode-Q data
29
SQDT
O
Serial output of Subcode-Q data
DIGITAL SIGNAL PROCESSOR FOR DISCMAN
S5L986F02
5
PIN DESCRIPTION (continued)
PIN NO
SYMBOL
IO
DESCRIPTION
30
SQOK
O
The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q
31
SBCK
I
Clock for output subcode data
32
SDAT
O
Subcode serial data output
33
DVDD1
-
Digital VDD1
34
MUTE
I
Mute control input ("H": Mute ON)
35
MLT
I
Latch Signal Input from Micom (Schmit Trigger)
36
MDAT
I
Serial data input from Micom (Schmit Trigger)
37
MCK
I
Serial clock input from Micom (Schmit Trigger)
38
RD7
I/O
SRAM data I/O port 8 (MSB)
39
RD6
I/O
SRAM data I/O port 7
40
RD5
I/O
SRAM data I/O port 6
41
RD4
I/O
SRAM data I/O port 5
42
RD3
I/O
SRAM data I/O port 4
43
RD2
I/O
SRAM data I/O port 3
44
RD1
I/O
SRAM data I/O port 2
45
RD0
I/O
SRAM data I/O port 1 (LSB)
46
FLAG1
I/O
Monitoring output for error correction (RA0)
47
FLAG2
I/O
Monitoring output for error correction (RA1)
48
FLAG3
I/O
Monitoring output for error correction (RA2)
49
FLAG4
I/O
Monitoring output for error correction (RA3)
50
FLAG5
I/O
Monitoring output for error correction (RA4)
51
/PBCK
I/O
Output of VCO/2 (4.3218MHz) (RA5)
52
DVSS2
I/O
Digital ground 2
53
FSDW
I/O
Window or unprotected frame sync (RA6)
54
ULKFS
I/O
Frame sync protection state (RA7)
55
/JIT
I/O
Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)
56
C4M
I/O
Only monitoring signal (4.2336MHz) (RA9)
57
C16M
I/O
16.9344MHz signal output(RA10)
58
/WE
I/O
Terminal for test
59
/CS
I/O
Terminal for test
60
XTALSEL
I
Mode Selection1 (H: 33.8688MHz, L: 16.9344MHz)
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