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LOW POWER DTMF RECEIVER
S5T3170
1
INTRODUCTION
The S5T3170 is a complete Dual Tone Multiple Frequency (DTMF)
receiver that is fabricated by low power CMOS and the Switched-
Capacitor Filter technology. This LSI consists of band split filters,
which separates counting section which verifies the frequency and
duration of the received tones before passing the corresponding code
to the output bus. It decodes all 16 DTMF tone pairs into a 4bits digital
code. The externally required components are minimized by on chip
provision of a differential input AMP, clock oscillator and latched three
state interface. The on chip clock generator requires only a low cost
TV crystal as an external component.
FEATURES
Detects all 16 standard tones.
Low power consumption: 15mW (Typ)
Single power supply: 5V
Uses inexpensive 3.58MHz crystal
Three state outputs for microprocessor interface
Good quality and performance for using in exchange system
Power down mode/input inhibit
ORDERING INFORMATION
APPLICATIONS
Device
Package
Operating
S5T3170X01-D0B0
18
-
DIP
-
300A
-
25
C -- + 75
C
S5T3170X01-S0B0
20
-
SOP
-
375
PABX
Key Phone System
Central Office
Answering Phone
Paging Systems
Home Automation System
Remote Control
Mobile Radio
Credit Card Systems
Remote Data Entry
18
-
DIP
-
300A
20
-
SOP
-
375
S5T3170
LOW POWER DTMF RECEIVER
2
PIN CONFIGURATION
PIN DESCRIPTION
Pin No
Symbol
Description
1
IN +
Non inverting input of the internal amp.
2
IN
-
Inverting input of the internal amp.
3
GS
Gain Select.
The output used for gain adjustment of analog input signal with a feedback resistor.
4
V
REF
Reference Voltage output (V
DD
/2, Typ) can be used to bias the internal amp input of
V
DD
/2.
5
I
IN
Input inhibit.
High input states inhibits the detection of tones. This pin is pulled down internally.
6
PDN
Control input for the stand-by power down mode.
Power down occurs when the signal on this input is in high states. This pin is pulled
down internally.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
S5T3170
IN+
IN-
GS
V
REF
I
IN
PDN
OSC1
OSC2
GND
V
DD
SI/GTO
ESO
DSO
Q4
Q3
Q2
Q1
OE
1
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
S5T3170
IN+
IN-
GS
V
REF
I
IN
PDN
OSC1
OSC2
GND
V
DD
SI/GTO
ESO
DSO
Q4
Q3
Q2
Q1
10
11
NC
OE
NC
(20-SOP)
(18-DIP)
LOW POWER DTMF RECEIVER
S5T3170
3
ABSOLUTE MAXIMUM RATINGS
7, 8
OSC1
OSC2
Clock input/output.
A inexpensive 3.579545MHz crystal connected between these pins completes internal
oscillator. Also, external clock can be used.
9
GND
Ground pin.
10
OE
Output Enable input.
Outputs Q1-Q4 are CMOS push-pull when OE is High and open circuited (High
impedance) when disabled by pulling OE low. Internal pull up resistor built in.
11 - 14
Q1 - Q4
Three state data output.
When enabled by OE, these digital outputs provide the hexadecimal code
corresponding to the last valid tone pair received.
15
DSO
Delayed Steering Output.
Indicates that valid frequencies have been present for the required guard time, thus
constituting a valid signal. Presents a logic high when a received tone pair has been
registered and the output latch is updated.
Returns to logic low when the voltage on SI/GTO falls below V
TH
.
16
ESO
Early Steering Outputs.
Indicates detection of valid tone output a logic high immediately when the digital
algorithm detects a recognizable tone pair.
Any momentary loss of signal condition will cause ESO to return to low.
17
SI/GTO
Steering Input/Guard Time Output.
A voltage greater the V
TS
detected at SI causes the device to register the detected
tone pair and update the output latch. A voltage less than V
TS
frees the device to
accept a new tone pair. The GTO output acts to reset the external steering time
constant, and its state is a function of ESO and the voltage on SI
18
V
DD
Power Supply (+5V, Typ)
Characteristics
Symbol
Value
Unit
Power Supply Voltage
V
DD
6
V
Analog Input Voltage Range
V
I (A)
-
0.3 -- V
DD
+ 0.3
V
Digital Input Voltage Range
V
I (D)
-
0.3 -- V
DD
+ 0.3
V
Output Voltage Range
V
O
-
0.3 -- V
DD
+ 0.3
V
Current On Any Pin
I
I
10
V
Operating Temperature
T
OPR
-
40 -- + 85
mA
Storage Temperature
T
STG
-
60 -- + 150
C
PIN DESCRIPTION (Continued)
Pin No
Symbol
Description
S5T3170
LOW POWER DTMF RECEIVER
4
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V, Ta = 25
C, unless otherwise noted)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Operating Voltage
V
DD
-
4.75
-
5.25
V
Operating Current
I
DD
-
-
3.0
9.0
mA
Power Dissipation
P
D
-
-
15
45
mW
Input Voltage Low
V
IL
-
-
-
1.5
V
Input Voltage High
V
IH
-
3.5
-
-
V
Input Leakage Current
I
I (LKG)
V
IN
= GND or V
DD
-
0.1
-
m
Pull Up Current On OE Pin
I
PU
OE = GND
-
7.5
15
A
Analog Input Impedance
R
I
f
IN
= 1KHz
8
10
-
M
Steering Input Threshold Voltage
V
TH
-
2.2
-
2.5
V
Output Voltage Low
V
OL
No Load
-
-
0.03
V
V
OH
No Load
4.97
-
-
V
Output Current (Sinking)
I
O (SINK)
V
OL
= 0.4V
1
2.5
-
mA
Output Current (Sourcing)
I
O (SOURCE)
V
OH
= 4.6V
0.4
0.8
-
mA
V
REF
Output Voltage
V
O (REF)
-
2.4
-
2.8
V
V
REF
Output Resistance
R
O (REF)
-
-
10
-
K
Analog Input Offset Voltage
V
IO
-
-
25
-
mV
Power Supply Rejection Ratio
PSRR
Gain Setting Amp at
1KHz
-
60
-
dB
Common Mode Rejection Ratio
CMRR
-
3.0V < V
IN
< 3.0V
-
60
-
dB
Open Loop Voltage Gain
G
V
Gain Setting Amp at
1KHz
-
65
-
dB
Open Loop Unit Gain Bandwidth
BW
-
-
1.5
-
MHz
Analog Output Voltage Swing
V
O (P-P)
R
L
= 100K
-
4.5
-
V
P-P
Acceptable Capacitive Load
C
L
GS
-
100
-
pF
Acceptable Resistive Load
R
L
GS
-
50
-
K
Analog Input Common Mode
Voltage Range
V
CM
No Load
-
3.0
-
V
P-P
Valid Input Signal Range
(each tone of composite signal)
V
I(VAL)
-
-
29
-
1.0
dBm
Dual Tone Twist Accept
TW
-
-
10
-
dB
Acceptable Frequency Deviation
f
-
-
-
1.5%
2Hz
-
Frequency Deviation Reject
f
R
-
3.5%
-
-
-
LOW POWER DTMF RECEIVER
S5T3170
5
NOTES:
1.
Digit sequence consists of all 16 DTMF tones.
2.
Tone duration = 40mS, Tone pause = 40mS.
3.
Nominal DTMF frequencies are used.
4.
Both tones in the composite signal have an equal amplitude.
5.
Tone pair is deviated by
1.5%
2Hz.
6.
Bandwidth limited (3KHz) Gaussian Noise.
7.
The precise dial tone frequencies are (350Hz and 440Hz)
2%.
8.
For an error rate of better than 1 in 10000.
9.
Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. This item also applies to a third tone injected onto the power supply.
12. Referenced to Fig. 1 Input DTMF tone level at -28dBm.
Third Tone Tolerance
T3rd
-
-
25
-
16
-
dB
Noise Tolerance
TN
-
-
-
12
-
dB
Dial Tone Tolerance
DT
-
18
22
-
dB
Crystal Clock Frequency
f
CK
-
3.5759
3.5795 3.5831
MHz
Maximum Clock Input Rise Time
t
R(MAX)
External Clock
-
-
110
nS
Maximum Clock Input Fall Time
t
F(MAX)
External Clock
-
-
110
nS
Acceptable Clock Input Duty Cycle
D
CK
External Clock
40
50
60
%
Acceptable Capacitive Load
D
L
OSC2 PIN
-
-
30
pF
Tone Present Detect Time
t
DET(P)
-
5
11
14
mS
Tone Absent Detect Time
t
DET(A)
-
0.5
4
8.5
mS
Minimum Tone Duration Accept
t
TDA(MIN)
User Adjustable
-
-
40
mS
Minimum Tone Duration Reject
t
TDR(MAX)
User Adjustable
20
-
-
mS
Acceptable Interdigit Pause
t
IDP(A)
User Adjustable
-
-
40
mS
Rejectable Interdigit Pause
t
IDP(R)
User Adjustable
20
-
-
mS
Propagation Delay Time SI to Q
t
D(SI-Q)
OE = High
-
8
11
S
Propagation Delay Time SI to DSO
t
D(SI-D)
OE = High
-
12
16
S
Output Data Setup Q to DSO
t
SU
OE = High
-
3.4
-
S
Propagation Delay Time OE to Q
(Enable)
t
D(QE-Q)EN
RL = 10K, CL = 50pF
-
50
60
nS
Propagation Delay Time OE to Q
(Disable)
t
D(QE-Q)DIS
RL = 10K, CL = 50pF
-
300
-
nS
ELECTRICAL CHARACTERISTICS (Continued)
(V
DD
= 5V, Ta = 25
C, unless otherwise noted)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
S5T3170
LOW POWER DTMF RECEIVER
6
TEST CIRCUIT
Figure 1. Test Circuit
HL74LS47
3
b
c
LT
RDO
ABI
d
GND
V
CC
f
g
a
c
d
HL74HCTLS02
8
14
12
11
9
1
4
7
1
10
2
6
13
4
5
8
7
2
3
5
6
R3
C1
300K
LED
KT3170
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
100K
R2
R1
100K
X - tal 2
0.1
F
3
2
1
4
5
6
7
8
9
0
*
#
9
8
7
6
5
4
3
2
10
11
12
13
14
15
16
17
18
1
X - tal 1
V
CC
V
CC
V
CC
V
CC
a
1
LTS542R
com
d
4
5
c dp
2
3
V
CC
10
9
8
7
6
g
com
f
a
b
16
15
14
13
12
11
10
9
R10
R9
R8
R7
R6
R5
R4
V
CC
KS58006
Fig. 2
S5T5820C
S5T3170
LOW POWER DTMF RECEIVER
S5T3170
7
TIMING DIAGRAM
Figure 2. Timing Diagram
DTMF
INPUT
ESO
SI/GTO
Q1 - Q4
DSO
OE
DTMF #n
DTMF #n + 1
DECODED TONE # (n - 1)
t
TDR (MAX)
t
TDA (MIN)
t
IDP (A)
t
IDP (R)
t
DET (P)
t
DET (A)
t
PGT
t
AGT
t
SU
t
D (SI-D)
t
D (OE-Q) DIS
t
D (OE-Q) EN
V
TH
DTMF #n + 1
S5T3170
LOW POWER DTMF RECEIVER
8
DIGITAL OUTPUT
Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when
disabled by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF
signals. The table below describes the hexadecimal.
NOTE:
Z
: High Impedance
H
: High Logic Level
L
: Low Logic Level
NO
Low Frequency
High Frequency
OE
Q4
Q3
Q2
Q1
1
697
1209
H
0
0
0
1
2
697
1336
H
0
0
1
0
3
697
1477
H
0
0
1
1
4
770
1209
H
0
1
0
0
5
770
1336
H
0
1
0
1
6
770
1477
H
0
1
1
0
7
852
1209
H
0
1
1
1
8
852
1336
H
1
0
0
0
9
852
1477
H
1
0
0
1
0
941
1336
H
1
0
1
0
*
941
1209
H
1
0
1
1
#
941
1477
H
1
1
0
0
A
697
1633
H
1
1
0
1
B
770
1633
H
1
1
1
0
C
852
1633
H
1
1
1
1
D
941
1633
H
0
0
0
0
ANY
-
-
L
Z
Z
Z
Z
LOW POWER DTMF RECEIVER
S5T3170
9
APPLICATION CIRCUIT
All resistors are 1% tolerance
All capacitors are 5% tolerance
Figure 3. Single Ended Input Configuration
R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1
INPUT IMPEDANCE : + (1/wC)
2
All resistors are 1% tolerance
All resistors are 1% tolerance
All capacitors are 5% tolerance
Figure 4. Differential Ended Input Configuration
IN+
IN-
GS
V
REF
I
IN
PDN
OSC1
OSC2
GND
V
DD
SI/GTO
ESO
DSO
Q4
Q3
Q2
Q1
OE
0.1uF
100K
100K
3.58MHz
+5V
0
.
1
u
F
300K
1
2
3
4
10nF
100K
C1
R1
10nF
100K
C2
R2
R3
37.5K
R2
60K
V
REF
R5
100K
GS
IN-
IN+
S5T3170
+
_
R
1
2
2
S5T3170
LOW POWER DTMF RECEIVER
10
Figure 5. Guard Time Adjustment
Figure 6. Oscillator Connection
t
PGT
= (R1C) In (V
DD
/V
DD
-V
TH
)
t
AGT
= (RPC) In (V
DD
/V
TST
)
R
P
= R1R2/(R1 + R2)
Decreasing t
AGT
(t
PGT
> t
AGT
)
t
PGT
= (RPC) In (V
DD
/V
DD
-V
TH
)
t
AGT
= (R1C) In (V
DD
/V
TH
)
R
P
= R1R2 (R1 + R2)
Decreasing t
PGT
(t
PGT
< t
AGT
)
V
DD
SI/GTO
ESO
R1
C
R2
SI/GTO
ESO
R1
R2
C
S5T3170
OSC1
OSC2
30pF
3.579545MHz
OSC1
OSC2
S5T3170
TO OSC1 of next S5T3170
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