1 CHIP CODEC
S5T8554B/7B
1
INTRODUCTION
The S5T8554B/7B are single-chip PCM encoders and decoders
(PCM CODECs) and PCM line filters. These devices provide all the
functions required to interface a full-duplex voice telephone circuit
with a time-division-multiplex (TDM) system.
These devices are designed to perform the transmit encoding and
receive decoding as well as the transmit and receive filtering
functions in PCM system. They are intended to be used at the
analog termination of a PCM line or trunk.
These devices provide the bandpass filtering of the analog signals
prior to encoding and after decoding. These combination devices
perform the encoding and decoding of voice and call progress tones
as well as the signalling and supervision information.
FEATURES
Complete CODEC and filtering system
Meets or exceeds AT&T D3/D4 and CCITT specifications
-Law: S5T8554B, A-Law: S5T8557B
On-chip auto zero, sample and hold, and precision voltage references
Low power dissipation: 60mW (operating), 3mW (standby)
5V operation
TTL or CMOS compatible
Automatic power down
ORDERING INFORMATION
Device
Package
Operating Temperature
S5T8554B02-L0B0
S5T8557B02-L0B0
16-CERDIP
-
25
C to 125
C
S5T8554B01-D0B0
S5T8557B01-D0B0
16-DIP-300A
-
25
C to +70
C
S5T8554B01-S0B0
S5T8557B01-S0B0
16-SOP-BD300
-
25
C to +70
C
16-CERDIP
16-DIP-300A
8
-
DIP
-
300
S5T8554B/7B
1 CHIP CODEC
2
PIN CONFIGURATION
PIN DISCRIPTION
Pin No
Symbol
Description
1
V
BB
V
BB
=
-
5V
5%
2
GNDA
Analog ground.
3
VF
R
O
Analog output of the receive power Amp.
4
V
CC
V
CC
= +5 V
5%
5
FS
R
Receive frame sync pulse. 8kHz pulse train
6
D
R
PCM data input.
7
BLCK
R
/
CLKSEL
Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock
in normal operation and BCLK
X
is used for both TX and RX directions.
Alternately direct clock input available, vary from 60kHz to 2.048MHz.
8
MCLK
R
/
PDN
When MCLK
R
is connected continuously high, the device is powered down.
Normally connected continuously low, MCLK
X
is selected for all DAC timing.
Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.
9
MCLK
X
Must be 1.536MHz/1.544MHz or 2.048MHz.
10
BLCK
X
May be vary from 64kHz to 2.048MHz but BCLK
X
is externally tied with MCLK
X
in
normal operation.
11
D
X
PCM data output.
12
FS
X
TX frame sync pulse. 8kHz pulse train.
13
TS
X
Changed from high to low during the encoder timeslot. Open drain output.
14
GS
X
Analog output of the TX input amplifier. Used to set gain through external resistor.
15
VF
X
I
-
Inverting input stage of the TX analog signal.
16
VF
X
I
+
Non-inverting input stage of the TX analog signal.
VF
X
I
+
VF
X
I
-
GS
X
TS
X
FS
X
S
D
X
BCLK
X
MCLK
X
V
BB
GNDA
VF
R
O
V
CC
FS
R
D
R
BCLK
R
/CLKSEL
MCLK
R
/PDN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
KT8554/7
S5T8554B/7B
1 CHIP CODEC
S5T8554B/7B
3
ABSOLUTE MAXIMUM RATING
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
5%, V
BB
=
-
5.0V
5%, GND
A
= 0V, Ta = 0
C to 70
C;
typical characteristics specified at V
CC
= 5.0V, V
BB
=
-
5.0V, Ta=25
C; all signals referenced to GND
A
)
Characteristic
Symbol
Value
Unit
Positive Supply Voltage
V
CC
7
V
Negative Supply Voltage
V
BB
-
7
V
Voltage at Any Analog Input or Output
V
I (A)
V
CC
+ 0.3 ~ V
BB
- 0.3
V
Voltage at Any Digital Input or Output
V
I (D)
V
CC
+ 0.3 ~ GND
A
- 0.3
V
Operating Temperature Range
Ta
-
25 ~ +125
C
Storage Temperature Range
T
STG
-
65 ~ +150
C
Lead Temperature (Soldering, 10 secs)
T
LEAD
300
C
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
POWER DISSIPATION
Power-Down Current
I
CC (DOWN)
No Load
-
0.5
1.5
mA
Power-Down Current
I
BB (DOWN)
No Load
-
0.05
0.3
mA
Active Current
I
CC (A)
No Load
-
6.0
9.0
mA
Active Current
I
BB (A)
No Load
-
6.0
9.0
mA
DIGITAL INTERFACE
Input Low Voltage
V
IL
-
-
-
0.6
V
Input High Voltage
V
IH
-
2.2
-
-
V
Input Low Current
I
IL
GND
A
V
IN
V
IL
, all digital input
-
10
-
10
A
Input High Current
I
IH
V
IH
V
IN
V
CC
-
10
-
10
A
Output Low Voltage
V
OL
D
X
, I
L
= 3.2mA
SIG
R
, I
L
= 1.0mA
TS
X
, I
L
= 3.2mA, open drain
-
-
0.4
0.4
0.4
V
V
V
Output High Voltage
I
O (HZ)
D
X
, I
H
=
-
3.2mA
SIG
R
, I
H
=
-
1.0mA
2.4
2.4
-
-
V
V
Output Current in High
Impedance State (Tri -state)
I
O (HZ)
D
X
, GND
A
V
O
V
CC
-
10
-
10
A
ANALOG INTERFACE WITH RECEIVE FILTER
Output Resistance
R
O
Pin VF
R
O
-
1
3
S5T8554B/7B
1 CHIP CODEC
4
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
5%, V
BB
=
-
5.0V
5%, GND
A
= 0V, Ta = 0
C to 70
C;
typical characteristics specified at V
CC
= 5.0V, V
BB
=
-
5.0V, Ta=25
C; all signals referenced to GND
A
)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Load Resistance
R
L
VF
R
O = 2.5V
600
-
-
Load Capacitance
C
L
-
-
-
500
pF
Output DC Offset Voltage
V
OO (RX)
-
-
200
-
200
mV
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER
Input Leakage Current
I
LKG
-2.5V
V
+2.5V, VF
X
I+ or VF
X
I-
-
200
-
200
nA
Input Resistance
R
I
-2.5V
V
+2.5V, VF
X
I+ or VF
X
I-
10
-
-
M
Output Resistance
R
O
Closed loop, unity gain
-
1
3
Load Resistance
R
L
GS
X
10
-
-
k
Load Capacitance
C
L
GS
X
-
-
50
pF
Output Dynamic Range
V
OD (TX)
GS
X
, R
L
10KW
2.8
-
-
V
Voltage Gain
G
V
VF
X
I+ to GSX
5,000
-
-
V/N
Unity Gain Bandwidth
BW
-
1
2
-
MHz
Offset Voltage
V
IO (TX)
-
-
20
-
20
mV
Common-Mode Voltage
V
CM (TX)
CMRRXA > 60dB
-
2.5
-
2.5
V
Common-Mode Rejection Ratio
CMRR
DC Test
60
-
-
dB
Power Supply Rejection Ratio
PSRR
DC Test
60
-
-
dB
1 CHIP CODEC
S5T8554B/7B
5
TIMING CHARACTERISTICS
(Unless otherwise noted, V
CC
= 5.0V
5%, V
BB
=
-
5.0V
5%, GND
A
= 0V, Ta = 0
C to 70
C;
typical characteristics specified at V
CC
= 5.0V, V
BB
=
-
5.0V, Ta=25
C; all signals referenced to GND
A
)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Frequency of Master Clock
f
MCK
Depends on the device used
and the BCLK
R
/CLKSEL Pin.
MCLK
X
and MCLK
R
-
1.536
1.544
2.048
-
nS
Rise Time of Bit Clock
t
R (BCK)
t
PB
= 488ns
-
-
50
nS
Fall Time of Bit Clock
t
F (BCK)
t
PB
= 488ns
-
-
50
nS
Holding Time from Bit Clock
Low to Frame Sync
t
H (LFS)
Long frame only
0
-
-
nS
Holding Time from Bit Clock
High to Frame Sync
t
H (RFS)
Short frame only
0
-
-
nS
Set-Up Time from Frame Sync
to Bit Clock Low
t
SU (FBCL)
Long frame only
80
-
-
nS
Delay Time from BCLK
X
High
to Data Valid
t
D (HDV)
Load = 150pF plse 2 LSTTL
loads
0
-
180
nS
Delay Time to TS
X
Low
t
D (TSXL)
Load = 150pF plse 2 LSTTL
loads
-
-
140
nS
Delay Time from BCLK
X
Low to
Data Output Disabled
t
D (LDD)
-
50
-
165
nS
Delay Time to Valid Data from
FSX or BCLK
X
, Whichever
Comes Later
t
D (VD)
C
L
= 0pF to 150pF
20
-
165
nS
Set-Up Time from D
R
Valid to
BCLK
R/X
Low
t
SU (DRBL)
-
50
-
-
nS
Hold Time from FS
R/X
Low to
D
R
Invalid
t
H (BLDR)
-
50
-
-
nS
Set-Up Time from FS
R/X
to
BCLK
R/X
Low
t
SU (FBLS)
Short frame sync pulse (1 or 2
bit clock periods long) (Note 1)
50
-
-
nS
Width of Master Clock High
t
W (MCKH)
MCLK
X
and MCLK
R
160
-
-
nS
Width of Master Clock Low
t
W (MCKL)
MCLK
X
and MCLK
R
160
-
-
nS
Rise Time of Master Clock
t
R (MCK)
MCLK
X
and MCLK
R
-
-
50
nS
Fall Time of Master Clock
t
F (MCK)
MCLK
X
and MCLK
R
-
-
50
nS
Set-Up Time from BCLK
X
High
(and FS
X
In Long Frame Sync
Mode) to MCLK
X
Falling Edge
t
SU (BHMF)
First bit clock after the leading
edge FS
X
-
-
-
-
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