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Электронный компонент: S5T8610

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DIGITAL CLP MODEM WITH ADPCM CODEC
S5T8610
1
PRELIMINARY
INTRODUCTION
S5T8610 provides low cost digital communication solution in 900 MHz
wideband cordless phone. It replaces the compander of an analog wideband
cordless phone. It has internal analog-to-digital and digital-to-analog converters
to reduce system cost.
S5T8610 provides the full advantages of digital communication such as
security, higher resistance to noise, and lowest cost solution in today's digital
cordless phone ICs. Furthermore, S5T8610 offers error concealment at 16 kbps
ADPCM transmission to provide longer communication range.
FEATURES
Operating voltage range: 3.0V to 3.6V
System main clock: 36.8 MHz or 36.864 MHz
Serial host interface
Internal ADC and DAC for modem
Internal voice CODEC for ADPCM
8 Phase DPSK
24kbps/16kbps ADPCM
Error concealment for 16kbps ADPCM
Loop back test
Encryption/Decryption
DTMF Generator
Digital Volume Control
typical application
ISM band digital cordless phone
ORDERING INFORMATION
Device
Package
Operating Temperature
++ S5T8610X01-Q0R0
64-QFP-1414
-20
C to +75
C
++: Under development
64-QFP-1414
S5T8610
DIGITAL CLP MODEM WITH ADPCM CODEC
2
PRELIMINARY
BLOCK DIAGRAM
DSP Unit
Program
ROM
Data RAM
Stack
DSIU
Timing
Correction
Unit
MODEM
ADC/DAC
Interface
Unit
12bits
ADC
12bits
DAC
Voice
Codec
Interface
Unit
Voice
Codec
Host
Interface
Unit
Control
Register
Unit
Clock
Generation
Unit
DIGITAL CLP MODEM WITH ADPCM CODEC
S5T8610
3
PRELIMINARY
PIN CONFIGURATION
TSELDR0
TSELDR1
TIDR
TODR
TINT
VDDD_OSC
OSCI
OSCO
VSSD_OSC
CKOUT
TEST0
TEST1
TEST2
TEST3
BER/JAM DET
VSSD1
VREF
AGND
VDDA_ADC
VSSA_ADC
RXI
VRT
VRB
TXO
VDDA_DAC
VSSA_DAC
VDDD_DAC
VSSD_DAC
VDDD1
TCLKDR
TSHFTDR
TUPDDR
S5T8610
DCLP
(64-QFP-1414)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSD_ADC
VDDD_ADC
REFL
REFH
VDDA_CDC
RXO
DTMF
VREFOUT
VSSA_CDC
TXI
AINFB
VSSD_CDC
VDDD_CDC
TD12
TD11
TD10
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDD2
TD9
TD8
TD7
TD6
TD5
TD4
TD3
TD2
TD1
TD0
HWEB
HCLK
HDATA
RESET
VSSD2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
S5T8610
DIGITAL CLP MODEM WITH ADPCM CODEC
4
PRELIMINARY
PIN DESCRIPTION
Pin No
Symbol
I/O
Description
1
VREF
AI
Reference top (3.3V) for ADC
2
AGND
AI
Reference bottom (0V) for ADC
3
VDDA_ADC
AP
Analog power (3.3V) for ADC
4
VSSA_ADC
AG
Analog ground (0V) for ADC
5
RXI
AI
Analog input (input range: 0V to 3.3V) for ADC
6
VRT
AI
Voltage reference top (2.0V) for DAC
7
VRB
AI
Voltage reference bottom (0V) for DAC
8
TXO
AO
Analog voltage output for DAC
9
VDDA_DAC
AP
Analog power (3.3V) for DAC
10
VSSA_DAC
AG
Analog ground (0V) for DAC
11
VDDD_DAC
DP
Digital power (3.3V) for DAC
12
VSSD_DAC
DG
Digital ground (0V) for DAC
13
VDDD1
DP
Digital power (3.3V) for DSP core
14
TCLKDR
DI
Test clock
15
TSHFTDR
DI
Test scan shift enable
16
TUPDDR
DI
Test scan update
17
TSELDR0
DI
Test scan register selection 0
18
TSELDR1
DI
Test scan register selection 1
19
TIDR
DI
Test scan input
20
TODR
DO
Test scan output
21
TINT
DO
Interrupt check
22
CKOUT
DO
Test clock output
23
VDDD_OSC
DP
Digital power (3.3V) for oscillator block
24
OSCI
I
Oscillator input
25
OSCO
O
Oscillator output
26
VSSD_OSC
DG
Digital ground (0V) for oscillator block
27
TEST0
DI
Test
28
TEST1
DI
Test
29
TEST2
DI
Test
30
TEST3
DI
Test
31
SYNCH/BER/JAM
DO
Initial synchronization / BER (bit error rate) / jamming
detection output
32
VSSD1
DG
Digital ground (0V)
DIGITAL CLP MODEM WITH ADPCM CODEC
S5T8610
5
PRELIMINARY
PIN DESCRIPTION (Continued)
Pin No
Symbol
I/O
Description
33
VSSD2
DG
Digital ground (0V)
34
RESET
DI
System reset (Reset: high, Normal: low)
35
HDATA
DB
Host data
36
HCLK
DI
Host interface clock
37
HWEB
DI
Host read/write signal (R: high, W: low)
38
TCK
DI
Test data input
39
TD0
DB
Test data input/output
40
TD1
DB
Test data input/output
41
TD2
DB
Test data input/output
42
TD3
DB
Test data input/output
43
TD4
DB
Test data input/output
44
TD5
DB
Test data input/output
45
TD6
DB
Test data input/output
46
TD7
DB
Test data input/output
47
TD8
DB
Test data input/output
48
VDDD2
DP
Digital power (3.3V) for DSP core
49
TD9
DB
Test data input/output
50
TD10
DB
Test data input/output
51
TD11
DB
Test data input/output
52
VDDD_CDC
AP
Digital power (3.3V) for CODEC
53
VSSD_CDC
AG
Digital ground (0V) for CODEC
54
AINFB
AO
Analog input gain control for CODEC
55
TXI
AI
ADC analog input for CODEC
56
VSSA_CDC
AG
Analog ground (0V) for CODEC
57
VREFOUT
AO
Vref output for CODEC (Vref = 1/2 V
DD
)
58
DTMF
AO
DTMF output for CODEC
59
RXO
AO
DAC analog output for CODEC
60
VDDA_CDC
AP
Analog power for CODEC
61
REFH
AI
Analog reference power (3.3V) for CODEC
62
REFL
AI
Analog reference ground (0V) for CODEC
63
VDDD_ADC
AP
Digital power (3.3V) for ADC
64
VSSD_ADC
AG
Digital ground (0V) for ADC