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Электронный компонент: S5T8803A01-D0B0

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10 CH PLL
S5T8803A
1
INTRODUCTION
The S5T8803A is designed to select 10 channels of a cordless phone,
whose frequency band is 46/49MHz.
It has a reference frequency generator, programmable divider for
Transmit and Receive section, and phase detector.
FEATURES
Able to select 10 Channels: S5T8803A
(both transmit/receive)
Include oscillation circuit with external x-tal (10.24MHz)
5KHz output for guard tone
Unlock detector
(phase difference more than 6.25us)
Standby function for power saving
ORDERING INFORMATION
Device
Package
Operating Temperature
S5T8803A01-D0B0
16
-
DIP
-
300A
-
30
C to +75
C
S5T8803A01-S0B0
16
-
SOP
-
225
16
-
DIP
-
300A
16
-
SOP
-
225
S5T8803A
10 CH PLL
2
BLOCK DIAGRAM
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
OSCI
OSCO
PDT
TIF
SB
D0
D1
D2
D3 MODE
LDT
RIF
PDR
F1
V
SS
V
DD
REFERENCE
DIVIDER
PHASE
DETECTOR (Tx)
PHASE
DETECTOR (Rx)
PROGRAMMABLE
DIVIDER (Tx)
PROGRAMMABLE
DIVIDER (Rx)
DECODER
UNLOCK
DETECTOR
V
DD
+
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
S5T8803A
OSCO
MODE
SB
F1
D0
D1
D2
D3
RIF
PDR
V
SS
PDT
LDT
TIF
OSCI
V
DD
10 CH PLL
S5T8803A
3
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
Pin No
Symbol
Description
1
OSCO
This output generates the reference frequency when it is connected to Pin 16 with the
external OSC, whose frequency is 10.24MHz.
2
MODE
Base/Remote Unit Selection Pin.
"
High
"
: Base Unit
"
Low
"
: Remote Unit
3
SB
Standby pin. This input controls Tx PLL for reducing the power dissipation
"
High
"
: Normal operation
"
Low
"
: Standby
4
F1
5KHz output
5, 6
7, 8
D0, D1
D2, D3
Channel selection pins
The Combinations of these inputs select one channel among the 10 channels
9
TIF
Input to programmable divider of Tx. AC coupling with VCO
In case of a larger signal, It needs DC
-
coupling. Minimum input voltage is 0.1 Vrms
10
LDT
Unlocked signal out pin (see output characteristics)
11
PDT
Phase detector output for Tx.
PDT detects the phase error from Tx PLL and its output is connected to the external
low pass filter
12
VSS
This pin is the negative supply of the IC. It is usually grounded
13
PDR
Phase detector output for Rx. PDR detects the phase error from Rx PLL and its output
is connected to the external low pass filter
14
RIF
Input of programmable divider for Rx. AC coupling with VCO
In case of a larger signal (standard CMOS logic), it needs DC coupling.
Minimum input voltage is 0.1Vrms
15
V
DD
This pin is the positive supply of the IC
Its reference is V
SS
, and normally + 3.0V ~ + 5.5V more positive than V
SS
16
OSCI
X-TAL OSC connection pin
This input generates the reference frequency when it is connected to pin 1 with the
external OSC
Characteristic
Symbol
Value
Unit
Supply voltage
V
DD
-
0.5 ~
+
6.0
V
Input Voltage
V
I
-
0.3 ~ V
DD
+ 0.5
V
Power Dissipation
P
D
350
mW
Operating Temperature
T
OPR
-
30 ~ + 75
C
Storage Temperature
T
STG
-
40 ~ + 125
C
S5T8803A
10 CH PLL
4
ELECTRICAL CHARACTERISTICS
(Ta = 25
C, V
DD
= 5 V, unless otherwise specified)
NOTES:
1.
OSC IN: 10.24MHz X-tal Connection
TIF: 27MHz 150 mVrms
RlF: 42MHz 150 mVrrns
MODE: V
DD
, SB = V
DD
, others are opened
2.
OSC IN: 10.24MHz X-tal Connection
TlF: 27MHz 150rnVrms
RIF: 42MHz 150mVrms
MODE: V
DD
, SB = V
SS
, others are opened
Capacitor more than 2000pF should be connected between V
DD
& V
SS
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Supply Voltage
V
DD
-
3
-
5.5
V
Input Voltage
V
IH1
D0 - D3, SB
0.7 V
DD
-
V
DD
V
V
IL1
D0 - D3, SB
-
-
0.3V
DD
V
V
IH2
MODE
0.9 V
DD
-
V
DD
V
V
IL2
MODE
-
-
0.1V
DD
V
f
I1
V
TIF
= 0.15Vrms
10
-
52
MHz
Input Frequency
f
l2
V
RIF
= 0.15Vrms
30
-
42
MHz
f
I3
OSC
IN
= 0.3Vrms
5
10.24
11
MHz
V
I(AMP)1
f
TIF
= 52MHz
0.1
-
0.3V
DD
Vrms
Input Amplitude
V
I(AMP)2
f
RIF
= 42MHz
0.1
-
0.3V
DD
Vrms
V
I(AMP)3
OSC
IN
= 11MHz
0.3
-
0.3V
DD
Vrms
Input Current
I
IH
V
IN
= V
DD
-
-
40
A
I
IL
V
IN
= V
SS
-
-
40
A
Output Voltage
V
OH1
PDT, RDR: I
O
= 0.5mA
V
DD
-1.0
-
-
V
V
OL1
PDT, RDR : I
O
= 0.5mA
-
-
1.0
V
V
OH2
LDT: I
O
= 1mA
V
DD
-1.0
-
-
V
V
OL2
F1: I
O
= 1mA
-
-
1.0
V
Output OFF Leakage
Current
I
LKG1
PDT, PDR : V
O
= V
DD
/V
SS
-
0.01
1.0
A
I
LKG2
LDT: V
O
= V
SS
-
-
5.0
A
Standby Current
I
SB1
V
DD
= 3V (Note 2)
-
1.0
2.0
mA
I
SB2
V
DD
= 3V (Note 2)
3.5
4.0
-
mA
Operating Current
I
DD1
V
DD
= 3V (Note 1)
-
2.0
3.0
mA
I
DD2
V
DD
= 5V (Note 1)
-
6.0
7.0
mA
10 CH PLL
S5T8803A
5
OUTPUT CHARACTERISTICS
LOCK
Figure 1.
Reference
Divider
Programmable
Divider
LDT
2) UNLOCK
Reference Divider
Programmable
Divider
LDT
t
PD
t
PD
t
PD
: Phase Difference ( 6.25
s )
V
DD
V
SS
V
DD
V
SS
Floating
V
DD
V
SS
V
SS
V
DD
V
DD
Floating
6.4ms