S6B0796
240 SEG / COM DRIVER FOR STN LCD
January, 2000
Ver. 1.0
Prepared by: Gyeong-Nam, Kim
kgn@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
S6B0796 PRELIMINARY SPEC. VER. 1.0 240 SEG / COM DRIVER FOR STN LCD
3
CONTENTS
INTRODUCTION ..................................................................................................................................................4
FEATURES ..........................................................................................................................................................4
BLOCK DIAGRAM ...............................................................................................................................................5
PAD CONFIGURATION (TBD) .............................................................................................................................6
PAD CENTER COORDINATES............................................................................................................................7
PIN DESCRIPTION ..............................................................................................................................................9
FUNCTIONAL DESCRIPTION............................................................................................................................10
BLOCK FUNCTION.....................................................................................................................................10
PIN FUNCTION...........................................................................................................................................11
FUNCTIONAL OPERATIONS......................................................................................................................15
SPECIFICATIONS..............................................................................................................................................18
ABSOLUTE MAXIMUM RATINGS...............................................................................................................18
RECOMMENDED OPERATING CONDITIONS ...........................................................................................18
DC CHARACTERISTICS.............................................................................................................................19
AC CHARACTERISTICS .............................................................................................................................21
PRECAUTION ....................................................................................................................................................28
CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS ........................................................................29
TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS......................................30
CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS .........................................................................31
240 SEG / COM DRIVER FOR STN LCD PRELIMINARY SPEC. VER. 1.0 S6B0796
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INTRODUCTION
The S6B0796 is a 240-outputs segment/common driver LSI for graphic dot-matrix liquid
crystal display systems. It is fabricated by low power CMOS high voltage process technology.
This device consists of 240-bits bi-directional shift register, 240-bits data latch and 240-bits
driver. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit
parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are
bi-directional, four data shift directions are pin-selectable
.
FEATURES
Both Segment Mode and Common Mode
- Supply voltage for LC driver: +15.0 to +32.0V
- Number of LC driver outputs: 240
- Low output impedance
- Low power consumption
- Supply voltage for the logic system: +2.4V to +5.5V
- CMOS silicon gate process (P-type Silicon Substrate)
- Package: 268-pin TCP (Tape Carrier Package) or Gold bumped chip
Segment Mode
- Shift clock frequency: 20MHz (Max) (Vdd=+5V
10%)
12MHz (Max) (Vdd=+2.4V to +4.5V)
- Adopts a data bus system
- 4- / 8-bit parallel input modes are selectable with a mode (MD) pin
- Automatic transfer function of an enable signal
- Automatic counting function which, in the chip select, causes the internal clock to be stopped
by automatically counting 240 of input data
- Line latch circuit reset function when DISPOFFB active
Common Mode
- Shift clock frequency: 4.0MHz (Max) (vdd=+2.4V to +5.5V)
- Built-in 240-bits bi-directional shift register (divisible into 120-bits
2)
- Available in a single mode (240-bits shift register)
or in a dual mode (120-bits shift register
2)
- Shift register circuit reset function when DISPOFFB active
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