1
Introduction
Table of Contents
1.1 Library Description .............................................................................................. 1-1
1.2 Features .............................................................................................................. 1-2
1.3 EDA Support ....................................................................................................... 1-4
1.4 Product Family..................................................................................................... 1-4
1.4.1 Analog Core Cells...................................................................................... 1-4
1.4.2 Standard Logic Cells ................................................................................. 1-8
1.4.3 Compiled Memory ..................................................................................... 1-9
1.4.4 Input/Output Cells ...................................................................................... 1-11
1.5 Timings................................................................................................................ 1-13
1.6 Design for Test (DFT) Methodology .................................................................... 1-22
1.7 Maximum Fanouts............................................................................................... 1-25
1.8 Package Capability by Pitch and Lead Count ..................................................... 1-31
1.9 Power Dissipation................................................................................................ 1-32
1.10 Crystal Oscillator Considerations ........................................................................ 1-36
Introduction
1.1 Library Description
Samsung ASIC
1-1
STDH150
1.1
Library
Description
STDH150 is Samsung's next generation Standard Cell library containing
standard cells implemented in Samsung's 0.13
m, L13 high-speed(L13HS)
process technology. Samsung's L13HS process uses 4 to 7 metal interconnect
layers. The STDH150 library contains diverse application specific digital and
analog IP for System-on-Chip (SoC) applications. Samsung provides a full range
of cells within the STDH150 library to address the challenges of designing and
producing high-speed devices that take advantage of SoC integration. STDH150
can help active system performance for high performance applications such as
HDD, Networking, and Displays.
STDH150 library supports gate counts of up to 34.3 million gates with 85%
usability. Gate delay is 20%~30% faster than that of STD130, 0.18
m generic
library. Logic density is 30% less than that of STD130 and complied memory
density is 15% less than that of STD130.
STDH150 supports also fully user configurable memories suitable for high-speed
applications with best density. To get much higher yield for SoC designs, it
contains the repairable memory with row redundant elements for high-capacity
memory.
STDH150 library also supports a wide range of I/O interface voltages and
standards. I/O cells that drive 2.5V, and 3.3V are available as 5V tolerant I/Os.
Available I/O standards include LVTTL, LVCMOS, PCI, PCI-X, OSC, AGP,
PECL, HSTL, SSTL2, GTLp, LVDS.
To better support SoC design, a robust collection of digital and analog IP cores
are available. Digital cores include the ARM7TDMI, ARM9TDMI, ARM920T,
ARM940T, ARM946E-S, and ARM926E-JS from ARM Ltd., as well as the Teak
and TeakLite DSP cores from the DSP Group. Analog cores include ADCs,
DACs, CODECs, and PLLs with various bit configurations and frequency ranges.
A thick oxide process option allows for high resolution operation of analog cores
with a 3.3V power supply.
In addition, the STDH150 library supports communication and data transmission
cores such as, IEEE1284, IEEE1394 link controller, UART, PCI controller,
PCMCIA controller and 10/100 ethernet MAC.
Samsung's design methodology offers a comprehensive timing driven design
flow including automated time budgeting, tight floor plan synthesis integration,
powerful timing analysis, and timing driven layout. Our advanced characterization
flow provides accurate timing data and robust delay models for L13HS, our
0.13
m very deep sub-micron process technology. Static verification methods,
such as static timing analysis and formal equivalence checking, provide an
effective verification methodology with a variety of simulators. Samsung's
Design-for-Test (DFT) methodology supports full and partial scan chain design,
BIST, JTAG boundary scan, and Built-in-Redundancy-Analysis (BIRA) for
reparable SRAM. Samsung provides a full set of test ready IP cores with an
efficient core test integration methodology.
1.2 Features
Introduction
STDH150
1-2
Samsung ASIC
1.2
Features
Robust 1.2V standard cell library including micro processor, DSP, and analog
cores.
- 0.13
m CMOS high-speed process technology with optional 7 metal layers.
- High gate count design of up to 46 million gates with up to 85% utilization for
7 metal layers.
- Typical 2 input NAND gate delay of 34ps with a fanout of 2.
- Characterized to industrial (-40C to 85C) and commercial (0C to 70C)
temperature ranges.
Robust Digital Cores
- Hard macro cells - ARM7TDMI, ARM9TDMI, ARM920T, ARM940T,
ARM946E-S, ARM926E-JS, Teak, and TeakLite.
- ARM embedded trace macro cells - ETM7 and ETM9
- Soft macro cells - USB1.1, IrDA, 16C450 and 16C550 UART, Fast Ether
net MAC, P1394a LINK, IEEE1284, PCI controller,
PCMCIA controller.
Ultra Low Voltage (1.2V) and High Resolution (3.3V) Analog Cores
- Analog core supply voltages (
5%) -1.2V, 2.5V, and 3.3V.
- ADC: 8 bit (250KHz, 1.2V and 125MHz, 3.3V), 10 bit (30MHz, 1.2V), and
12 bit (250KHz-10MHz, 3.3V)
- DAC: 10 bit (80MHz, 1.2V), 12 bit (2MHz - 300MHz, 3.3V)
- CODEC: 14 bit Sigma-Delta (8KHz - 11KHz, 2.5V)
- PLL: 1.2V FSPLL (25MHz - 300MHz and 100MHz - 500MHz), SSCG (1.2V,
200MHz)
Fully User Configurable SRAMs and ROMs
- Suitable for high-speed memory configurations with best density
- Single port (1RW, 1R), dual port (2RW), and multi port (1R1W, 2R1W,
2R2W)
- Bit-write capability
- 2 bank architecture available
- Zero hold time for data in, address and control pins
- Flexible aspect ratio
- Up to 256K-bit single port(1RW) SRAM
- Up to 1M-bit single port(1RW) repairable SRAM
- Up to 128K-bit dual port(2RW) SRAM
- Up to 1M-bit single port(1R) via-1 programmable ROM
- Up to 16K-bit multi port(1R1W, 2R1W, 2R2W) register files
- Up to 32K-bit CAM with binary (On-demand)
- Up to 64K-bit FIFO (On-demand)
- Up to 4M-bit single port(1RW) SRAM with burst operations (On-demand)
- Up to 4M-bit single port(1R) via-1 programmable ROM (On-demand)
Full Compliment of I/O Cells
- 2.5V/3.3V drive and 5.0V tolerant I/Os
- 3 levels (high, medium, and no) of slew rate control
- Minimum wire bonded pad pitch
- 60
m single in line I/Os
- 30
m staggered I/Os
- Drive capabilities
- Up to 12mA for drive I/Os
- Up to 6mA for 5V tolerant I/Os
Introduction
1.2 Features
Samsung ASIC
1-3
STDH150
Standard Interface IP
- PCI 2.1 compliant, 33/66MHz, 5V tolerant
- USB 1.1 compliant, full speed/low speed, 3.3V
- SSTL2 Class-I and II SDRAM interface, up to 200MHz
- ATA4/UDMA66, 3.3V, 5V tolerant
- AGP 2.0 compliant, 66MHz @ 1X, 133MHz @ 2X, 266MHz @ 4X
- PECL, 200MHz single ended, 500MHz differential point-to-point ATM
interface
- HSTL, 300MHz, 1.5V SRAM interface with programmable output impedance
control
- Hot Swap PCI - 1V pre-charge, VIO pre-charge
- PCI-X, 1.0 compliant, 133MHz, 3.3V
Fully Integrated CAD software and EDA support
- Logic synthesis: Synopsys Design compiler
- Physical synthesis: Synopsys Physical compiler
- Logic simulation: Cadence Verilog XL, Cadence NC-Verilog/VHDL,
Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VCS.
- DFT, scan insertion and ATPG: Synopsys TestGen, Synopsys TestCompiler,
Synopsys TetraMax, Mentor Fastscan.
- Static timing analysis: Synopsys PrimeTime
- RC analysis: Avant! Star-RCXT
- Power analysis: Synopsys DesignPower, Sequence Watt Watcher,
CubicPower (Samsung in-house tool).
- Formal verification: Synopsys Formality, Avant! Design VERIFYer,
Verplex Tuxedo-LEC
- Fault simulation: Cadence Verifault
- Delay calculator: CubicDelay (Samsung in-house tool).
- Floor planner: Avant! PlanerPL, CubicPlan (Samsung in-house tool).
- Place and Route: Avant! Apollo, Cadence Silicon Ensemble
- DRC and LVS: Dracula, Hercules, Calibre
Easy and Accurate Clock Tree Insertion
- 12 user selectable clock tree cells
- Accurate pre-layout and post-layout correlation
- Insertion delay, skew, transition time management
- Clock tree information file generation
- Tightly coupled with in-house delay calculator, CubicDelay.
For more information on the CTC flow, refer to "Clock Analysys Flow (with CTC)
User Guide for CubicDelay" included in the Samsung Design Kit.
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