Ordering number: ENN6522

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Tuner System IC with Built-in PLL

for Car Audio Applications

LA17000M

Monolithic Linear IC

62901RM (II) No. 6522-1/54

Package Dimensions

unit: mm

3255-QFP80

14.0

17.2

0.15

0.1

3.0max

0.25

0.65

(0.83)

(2.7)

0.8

[LA17000M]

SANYO: QFP80 (14 x 14)

Overview

The LA17000M is an all-in-one car tuner IC that incorpo-
rates a PLL frequency synthesizer and all functions of an
AM/FM tuner in a single chip. By combining two chips, a
PLL (LC72144 equivalent) and an FM tuner IC (LA1781M
equivalent) into a single chip (*PLL + AM (up conversion)
+ FMFE + IF + NC + MCP + MRC), and as a result of
optimal chip partitioning, the LA17000M improves the
performance of car tuner systems, eliminates adjustments,
and provides high reliability, all at a lower cost.

Features

· PLL on chip

· ADC (6 bits, 1 channel)
· IF counter and I/O port on chip permit simplification

of the interface.

· Supports AM double conversion.

· Enhanced noise countermeasures

· Excellent tri-signal characteristics
· Improved medium and weak electric field NC

characteristics

· Improved separation characteristics
· Anti-birdie filter on chip (analog/digital output)
· Multipath sensor output (analog/digital output)

· Cost-saving features

· AM double conversion (Up conversion method)
· Enhanced FM-IF circuit

(When there is interference from adjacent frequencies,
the software handles switching of the CF between
wide and narrow automatically.)

· Because deviations in IF gain are only 1/3 that of

earlier devices, adjustment is simplified when this IC
is incorporated into a set; this IC also includes a shifter
pin for VSM adjustment.

· Suited for smaller devices

· Permits high-frequency signal line processing in a

tuner pack.

· Easily conformes to FCC standards

LA17000M

No. 6522-2/54

Maximum Ratings at Ta = 25°C

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

1 max

Pins 6, 56, and 77

8.7

2 max

Pins 7, 61, 70, 75, and 76

12.0

max

Pin 19

6.0

Allowable power dissipation

Pd max

85°C, * With board

950

Operating temperature

Topr

40 to +85

°C

Storage temperature

Tstg

40 to 150

°C

* Specified board: 114.3

× 76.1 × 1.6 mm

, glass epoxy

Operating Conditions at Ta = 25°C

Parameter

Symbol

Conditions

Ratings

Unit

Recommended supply voltage

Pins 6, 7, 56, 61, 70, 75, 76, and 77

8.0

Pin 19

5.0

Operating supply voltage range

7.5 to 8.5

4.5 to 5.5

Tuner Block

Operating Characteristics at Ta = 25°C, V

= 8.0 V, V

= 5.0 V, in the specified Test Circuit

Parameter

Symbol

Conditions

Ratings

min

typ

max

Unit

[FM characteristics] FM IF input

Current drain

CCO

-FM

No input, I56 + I61 + I70 + I75 + I76 + I79

110

Demodulated output

220

330

445

mVrms

Channel balance

Total harmonic distortion

THD-FMmono 10.7 MHz, 100 dB

µV, 1 kHz, 100% mod, pin 15

0.4

Signal-to-noise ratio IF

S/N-FM IF

10.7 MHz, 100 dB

µV, 1 kHz, 100% mod, pin 15

AM suppression ratio IF

AMR IF

Muting attenuation

Att-1

Att-2

Att-3

Separation

Stereo ON level

ST-ON

Pilot modulation at which V17 < 0.5 V

4.1

6.6

Stereo OFF level

ST-OFF

Pilot modulation at which V17 > 3.5 V

1.2

3.1

Main total harmonic distortion

THD-Main L

0.4

1.2

Pilot cancellation

PCAN

SNC output attenuation

AttSNC

HCC output attenuation

AttHCC-1

AttHCC-2

Continued on next page.

10.7 MHz, 100 dB

µV, 1 kHz, 100%mod,

pin 15 output

10.7 MHz, 100 dB

µV, 1 kHz,

ratio of pin15 and pin 16

10.7 MHz, 100 dB

µ, 1 kHz, fm = 1 kHz, pin 15

at 30% AM

10.7 MHz, 100 dB

µV, 1 kHz, attenuation on

pin 15 when V49 = 0

2 V

10.7 MHz, 100 dB

µV, 1 kHz, attenuation on

pin 15 when V49 = 0

2 V *Note 1

10.7 MHz, 100 dB

µV, 1 kHz, attenuation on

pin 15 when V49 = 0

2 V *Note 2

10.7 MHz, 100 dB

µ, L + R = 90%,

pilot = 10%, pin 15 output ratio

10.7 MHz, 100 dB

µV, L + R = 90%,

pilot = 10%, pin 15

10.7 MHz, 100 dB

µV, pilot = 10%,

pin 15 signal/PILOT-LEVEL leak DIN AUDIO

10.7 MHz, 100 dB

µV, L R = 90%,

pilot = 10%, V44 = 3 V

0.6 V, pin 15

10.7 MHz, 100 dB

µV, 10 kHz, L + R = 90%,

pilot = 10%, V45 = 3 V

0.6 V, pin 15

10.7 MHz, 100 dB

µV, 10 kHz, L + R = 90%,

pilot = 10%, V45 = 3 V

0.1 V, pin 15

LA17000M

No. 6522-3/54

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

min

typ

max

Unit

Input limiting voltage

-LIM

Muting sensitivity

-MUTE

IF input level non-mod when V49 = 2 V

SD sensitivity

SD-sen1 FM

SD-sen2 FM

IF counter buffer output

IFBUFF-FM

145

245

330

mVrms

IFBUFF-FM

145

245

330

mVrms

Signal meter output

FM-1

No input, pin 42 DC output non-mod

0.0

0.1

0.3

FM-2

50 dB

, pin 42 DC output non-mod

0.65

1.6

2.4

FM-3

70 dB

, pin 42 DC output non-mod

2.4

3.2

4.2

FM-4

100 dB

, pin 42 DC output non-mod

4.9

5.8

6.5

Muting bandwidth

BW-MUTE

140

210

280

kHz

Muting drive output

MUTE

-100

100 dB

V, 0 dB

, pin 49 DC output non-mod

0.00

0.1

0.3

[FM FE Block]

N-AGC on input

NAGC

W-AGC on input

WAGC

104

Conversion gain

A. V1

83 MHz, 80 dB

, non-mod, FECF output

A. V2

Oscillator buffer output

OSCBUFFFM

No input, pin 5 output

102

mVrms

[NC Block] NC input (pin 30)

Gate time

GATE

f = 1 kHz, 1

s, 100 mVp-o pulse input

Noise sensitivity

mVp-o

[MRC Block]

MRC output

MRC

V42 = 5 V

2.1

2.25

2.4

MRC operating level

MRC-ON

mVrms

MRC sensor output

MRC

-sensor1 V42 = 5 V, pin 34 output

1.5

1.9

MRC-

sensor2

V42 = 5 V, pin 48 output, f = 70 kHz, 100 mVrms

2.1

2.9

[AM Characteristics] AM ANT input

Practical sensitivity

S/N-30

1 MHz, 30 dB

V, fm = 1 kHz, 30% mod, pin 15

Detection output

-AM

1 MHz, 74 dB

V, fm = 1 kHz, 30% mod, pin 15

105

160

220

mVrms

AGC-F.O.M

AGC-FOM

mVrms

Signal-to-noise ratio

S/N-AM

1 MHz, 74 dB

V, fm = 1 kHz, 30% mod

Total harmonic distortion

THD-AM

1 MHz, 74 dB

V, fm = 1 kHz, 80% mod

0.5

1.2

Signal meter output

AM-1

1 MHz, 30 dB

V, non - mod

0.6

1.4

AM-2

1 MHz, 120 dB

V, non - mod

3.4

4.5

5.9

Oscillator buffer output

OSCBUFF

AM-1 No input, pin 5 output

170

210

mVrms

Wideband AGC sensitivity

W-AGCsen1

1.4 MHz, input when V62 = 0.7 V

W-AGCsen2

1.4 MHz, input when V62 = 0.7 V (during SEEK)

Continued on next page.

10.7 MHz, 100 dB

V, 30% mod, IF input that

decreases the input reference output by 3 dB

IF input non-mod (at least 100 mVrms) at
which the IF count buffer output turns on

10.7 MHz, 100 dB

V, non-mod, pin 38 output,

during SEEK

83 MHz, 80 dB

, non-mod, 5 V applied to CF

(pin 10), FECF output

1 kHz, 1

s pulse input that starts noise

canceller operation. Measured at Pin 30.

Input level on pin 48 that is below
pin 42 = 5 V and pin 43 = 2 V, f = 70 kHz

1 MHz, 74 dB

V, output reference, input width

at which output drops by 10 dB, pin 15

10.7 MHz, 100 dB

V, non-mod,

pin 38 output, during RDS mode

100 dB

V, when V49 = 2 V

Bandwidth non-mod

83 MHz, non-mod, input at which pin 2 is
2.0 V or less

83 MHz, non-mod, input at which pin 2 is
2.0 V or less (when KEYED-AGC is 4.0 V)

LA17000M

No. 6522-4/54

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

min

typ

max

Unit

SD sensitivity

SD-sen1AM

SD-sen2AM

1 MHz, ANT input level at which SD pin turns on

IF buffer output

IFBUFF-AM

1 MHz, 74 dB

V, non-mod, pin 38 output

150

220

mVrms

PLL Block
Allowable Operating Ranges

at Ta = 40 to +85°C, V

= 5 V, V

= 0 V

Parameter

Symbol

Conditions

Ratings

min

typ

max

Unit

High-level input voltage

CE, CL, DI, I/O-1, I/O-2

2.2

+ 0.3

Low-level Input voltage

CE, CL, DI, I/O-1, I/O-2, SDSTSW

0.8

Output voltage

6.5

I/O-1, I/O-2

Input amplitude

; Sine wave, capacitor coupled

MHz

PLL

; Sine wave, capacitor coupled

160

MHz

HCTR; Sine wave, capacitor coupled

0.4

MHz

X'tal

10.1

10.5

MHz

Input amplitude

200

1500

mVrms

2-1

PLL

;

f < 130 MHz; Note 2

1500

mVrms

2-2

PLL

; 130

f <160 MHz; Note 2

1500

mVrms

3-1

1500

mVrms

3-2

1500

mVrms

Data setup time

DI, CL: Note 5

0.45

Data hold time

DI, CL: Note 5

0.45

Clock low-level time

CL: Note 5

0.45

Clock high-level time

CL: Note 5

0.45

CE wait time

CE, CL: Note 5

0.45

CE setup time

CE, CL: Note 5

0.45

CE hold time

CE, CL: Note 5

0.45

Data latch change time

Note 5

0.45

Data output time

0.2

Note 1:

Recommended CI value for crystal oscillator
CI

(X'tal: 10.25, 10.35 MHz)

However, because the characteristics of the X'tal oscillation circuit depend on the board and circuit constants,
we recommend requesting that the X'tal manufacturer perform the evaluation.

Note 2:

Refer to the program divider configuration.

Note 3:

Serial data: CTC = 0

Note 4:

Serial data: CTC = 1

Note 5:

Refer to the serial data timing.

Guaranteed crystal oscillator
ranges

, X

OUT

; CI

(X'tal: 10.25, 10.35 MHz); Note 1

HCTR; 0.4

f < 25 MHz: Serial data;

CTC = 0: Note 3

HCTR; 8

f <12MHz: Serial data;

CTC = 1: Note 4

DO, CL; Dependent on pull-up resistance,
board capacity: Note 5

1 MHz, ANT input level at which IF count
output turns on

LA17000M

No. 6522-5/54

PLL Characteristics
Electrical Characteristics

at Ta = 25°C, V

= 5 V, V

= 0 V

Parameter

Symbol

Conditions

Ratings

min

typ

max

Unit

Built-in feedback resistors

Rf1

Rf2

PLL

500

Rf3

HCTR

250

Hysterisis width

HIS

CE, CL, DI

0.1V

High-level output voltage

PD1, PDS, SEEKSW; I

= 1 mA

1.0

XBUF; I

= 0.5 mA

1.5

Low-level output voltage

PD1, PDS, SEEKSW; I

= 1 mA

XBUFF; I

= 0.5 mA

1.5

I/O-1 to I/O-2; I

= 1.0 mA

0.2

I/O-1 to I/O-2; I

= 2.5 mA

0.5

I/O-1 to I/O-2; I

= 5.0 mA

I/O-1 to I/O-2; I

= 9.0 mA

1.8

DO; I

= 5.0 mA

High-level input current

CE, CL, DI; V

= 6.5 V

I/O-1 to I/O-2; V

= 13 V

; V

= V

PLL

; V

= V

Low-level input current

CE, CL, DI; V

= 0 V

I/O-1 to I/O-2; V

= 0 V

; V

= 0 V

PLL

; V

= 0 V

Output off leakage current

OFF

I/O-1 to I/O-2; V

= 13 V

OFF

DO; V

= 6.5 V

OFFH

PD1, PDS; V

= V

0.01

200

OFFL

PD1, PDS; V

= 0 V

0.01

200

Input capacitance

A/D converter linearity error

Err

MRC SENSOR AUTO ADJ (MOS)

0.5

+0.5

LSB

Rpd1

PLL

200

600

Supply current

; PLL block halt, X'tal OSC halt

High-level 3-state off leakage
current

Low-level 3-state off leakage
current

Pull-down transistor on
resistance

; X'tal = 10.25 MHz,

2 = 160 MHz,

2 = 70 mVrms,

3 = 25 MHz,

3 = 40 mVrms

; PLL block halt (PLL INHIBIT),

X'tal OSC operation (10.25 MHz)

LA17000M

FM RF AGC

FE GND

FMOSC

OSC BUFFER

AM/FM

AM OSC

NC Sens

NC AGC

XBUFF IN

Gore OUT

LPF OUT

MPX Pdot IN

NC MPX GND

Lch OUT

Rch out

SDSTSW

PLL IN

PLL V

FM MIX IN

FM ANTD

0.022

16V/100

0.022

8pF

10.7Hz

10.7MHz

450kHz

1000pF

100

FC18

2.2

16V/47

0.022

16V/47

0.01

0.022

82pF

8
2pF

68pF

0.022

3.3

0.1

100

0.022

33mH

100

65pF

6pF

15pF

1SV234

0.022

AM/FM S-METER

MRC OUT

SNC

HCC

NC IN

DET OUT

FM S-METER MRC IN

MUTE

AFC IN

QD OUT

QD IN

REF

FM SD

KEYED AGC

C-HCC

AM LC

PILOT DET

IF AGC

PD1

PLL VSS

PDS

XBUFF

I/O2

X IN

X OUT

I/O1

HCTR

SEEKSW

MRC SENSOR OUT ADC 0

PC IN

PC OUT

MPX VCO

IF COUNT BUFF SEEK/STOP SELECT

GND

AM 1st MIX IN

1st IF IN (NARROW)

FE VCC

MIX OUT

NARROW AGC IN/MUTE ATT ADJ

AM RF AGC OUT

1st IF (WIDE)

AM SD ADJ/WIDE AGC IN

AM MIX OUT

1st IF OUT

AM IF IN

FM IF IN

FM IF BYPASS

2nd MIX IN

RF AGC

FM MUTE ADJ

AM ANTD/WIDE AGC

AM FT

LA17000M

+5V

--5V

0.022

0.01

270pF

30pF

100pF

30k

0.47

0.015

100pF

0.01

0.1

0.01

1000pF

712-12

1025MHz

0.01

180pF

112NME

112LDA

0.1

0.047

0.22

0.022

912kHz

16V/10

16V/1

16V/100

16V/1

0.022

0.01

0.22

3.3

0.022

10.7Hz

51k

10k

51k

350

10k

SOFP80

10k

2SK583

10k

47k

200

22pF

47k

33k

5.6k

PHASE COMP

330

47k

15k

100k

10k

100k

43k

10k

30k

20k

10k

SIGNAL

-MATER

-Z

SEP

-VOL

-L

SEP

-VOL

-H

SW11

-IN

-GND

-IN

DET

-OUT

MRC

-IN

MUTE

SW12

DET

-ADJ

SYS-PS+15V

SYS-PS-GND

SYS-PS---15V

DZ1

SYS-PS+12V

CENTER-MATER

AM-STREO-OUT

AM-STREO-OUT-GND

1st-IF-OUT

SW13

SW14

FM-IF-INPUT

SW40
SW41

RF-MIX-VCC

RF-MIX-VCC-G

AM-VCC

AM-ANT-INPUT

AM-ANT-DUMP

FM-ANT-INPUT

SW01

FM-ANT-DUMP

FM-AGC

FM-MIX-INPUT

10k

6.8k

10k

100

10k

240k

L78MO5T

82pF

8200pF

750pF

82pF

SVC203

2.2k

150pF

6800pF

112LDA

30pF

0.015

16V/100

0.01

-V

SW18

OSC

-BUFF

-OUT

-HPF

-OUT

SW02

CF SW

SW03

SW04

SW05

GATE

-OUT

L -

-OUT

-LPF

-OUT

-CH

-OUT

-SD

SW06

VF/IMZ

-G

VF/IMZ

-S

VF/IMZ

-F

PLL -VCC

VT-OUT

2nd-OSC-BUFF

IOZ

SW17

X-IN

DUT-CCB-CE

DUT-CCB-CL

DUT-CCB-DI

IO1

SW16

IF-COUNT-IN

IF-COUNT-BUFF

MRC-SENSOR-OUT

SW07

MPX-FREO

SIGNAL-MATER-1

MRC-OUT

SW08

SW09

VDDSNC/HCC1

FMIF AM NC MPX V

PLL

-IN

+5V

--5V

0.01

+12V

+15V

0.1

+15V

--15V

0.1

0.01

0.1

--15V

+15V

+5V

--5V

--15V

+12V

0.1

--15V

0.1

0.01

+5V

--5V

0.01

0.022

330

0.1

PLL VCC

0.022

+5V

--5V

0.01

+5V

--5V

0.01

5pF

10pF

18pF

100pF

150

200k

30k

510

100

30k

200k

3SK263

30k

150

560

100k

0.01

2200pF

180pF

180k

100k

10pF

15pF

18k

1SV234

1000pF

16V/100

15pF

1000pF

16V/47

0.01

L79MO5T

A13289

Test Circuit

No. 6522-6/54

LA17000M

No. 6522-7/54

[FM IF Selectivity Switching Circuit]

Features

1) Comprises an FM/AM one-chip system.
2) Up conversion method is adopted for AM.
3) Uses an IF filter with a center frequency that is the same as the middle frequency of FM.
4) Uses a narrowband filter in AM mode.
5) Uses a narrowband filter in FM mode only during SEEK or when there is interference from adjacent frequencies.
6) Uses a wideband filter for normal reception in FM mode.
7) For an RDS AF search, switches to a narrowband filter and detects SD.
8) High sensitivity for detecting interference from adjacent frequencies.

Advantages

1) This FM/AM one-chip tuner system (an IC that includes a microcontroller interface) allows for improved adjacent

frequency interference characteristics without increased cost.

2) Prevents SD and IF count misdetection (station detection) during seek search, RDS AF search, and auto memory

operations.

3) Permits adoption of an IC for certain functions without increasing the number of IC pins.
4) CF selectivity can be switched by the software in the microcontroller that controls the tuner, making it easy to

achieve performance differentiation through the software.
(The software can freely set the CF switching timing and conditions.)

5) Detects the radio wave status in the field through detection of SD, desired station field intensity, IF count output, and

adjacent station field intensity. This IC offers improved adjacent frequency interference characteristics by switching
the CF automatically when interference is being generated from an adjacent frequency.

[IF Band Switching Circuit]

Purpose

This AM/FM one-chip tuner IC automatically switches the FM selectivity, prevents misdetection during SEEK opera-
tions, and offers improved adjacent frequency interference characteristics without any increase in cost.

New Technological Features

Comprises an AM/FM one-chip IC.

Because the narrowband CF that is used by the AM UP conversion system is also used for FM, additional external
components required by earlier systems can be eliminated.

Uses a wideband CF during normal FM reception for high sound quality.

Uses a narrowband CF for AM reception, and if interference is being generated from adjacent frequencies during
FM reception.

Uses a narrowband CF during SEEK and RDSAF search operations, preventing misdetection of SD and IF count
due to adjacent stations.

CF switching is performed at the first IF amp input, and the amp gain is adjusted automatically to a suitable level
according to the CF band form AM/FM or FM.

Switching of the CF input and the first IF amp gain is controlled by a microcontroller through the interface. The
pins that are controlled are connected to the I/O ports of the microcontroller, and are controlled by the
microcontroller's internal software.

Detection of adjacent frequency interference during FM reception is based on S-meter output, SD, and IF count
output. The IF count buffer frequency fluctuates when interference is being generated from adjacent frequencies.
This fluctuation is used to make the detection of interference from adjacent frequencies possible. (Related patents
have been applied for.)

Conventional Technologies

Comprised of a dedicated IC for IF band switching, or of multiple ICs.

None of the AM/FM all-in-one chip systems include the functions provided by the LA17000M.

Requires a narrowband CF especially for FM, resulting in increased costs. (Does not share the AM narrowband CF.)

Because CF switching control is handled by analog circuits or logic circuits, the switching timing can only be
controlled through uniform conditions. Control by software is not possible.

LA17000M

No. 6522-9/54

I/O Port Assignment Table

I/O-0

DI data

I/O-1

I/O-2

DI data

I/O-3

DO data

OUTPUT
PLL output port

INPUT
PLL input port

OUTPUT
PLL output port

INPUT
I/O-3 = 0 (input port)
OUT3 = 1 (OPEN or high)
PLL input port

Cannot be set as output port

L: Reception mode
H: Seek mode

OPEN: RDS

Unused

H: Dx mode
L: Lo mode

When reception mode is set
H: Monaural
L: Stereo

When seek mode is set
H: SD ON
L: SD OFF

The MRC sensor reads DO data from the PLL microcontroller's 6-bit A/D converter.

Currently, aside from the CCB data lines, only three lines are connected to the controller microcontroller: CF/SW,
AUDIO mute, and AM/FM band switching port.

Selectivity Switching Evaluation Software State-based Data Switching Table

Tuner processing

Seek

Manual preset

Receiving

Remarks

I/O port state

CF switching

WIDE

NARROW

AUDIO mute output

Switchable but fixed by software

OFF

Switchable but fixed by software

Lo/Dx

Processing is performed according

to the setting

Processing is performed according

to the setting

Mode switching

Seek mode

I/O-3 is SD output

Reception mode

I/O-3 is monaural/stereo output

RDS mode

I/O-3 is SD output

IF count

Output ON

Seek mode

RDS mode

Output OFF

Reception mode

LA17000M

No. 6522-10/54

Additional Settings (Added to the LC72144M)

Output (DI)

Mode

Settings

When set

Seek mode

For seek

Tuner mode switch

Reception mode

For seek-stop and for receiving

RDS mode

For AF search

Lo mode

When setting Lo mode

Lo/Dx switch

Dx mode

When setting Dx mode

Mute ON

For tuning processing

Hard mute *1

Mute OFF

When switching reception mode

DI data IN2
I/O-0 = 1 (output port)
OUT0 = 1 (Hi)

DI data IN2
I/O-0 = 1 (output port)
OUT0 = 0 (Lo)

DI data IN2
I/O-0 = 0 (input port)
OUT0 = 1 (OPEN)

DI data IN2
I/O-2 = 0 (output port)
OUT2 = 0 (Lo)

DI data IN2
I/O-2 = 1 (output port)
OUT2 = 1 (Hi)

DI data IN2
I/O-0 = 1 (output port)
OUT1 = 1 (Hi)

DI data IN2
I/O-0 = 1 (output port)
OUT1 = 1 (Lo)

Note: *1. Depends on the I/O ports usage.

Input (DO)

DO data

Conditions

When the tuner mode is set to
reception mode

Sensor

When the tuner mode is set to seek or
RDS mode

MRC output

Start AD conversion and then read
after conversion is completed.
3.3 V at 6-bit resolution

OUT data I3 = 1 (Hi)
Monaural state
OUT data I3 = 0 (Lo)
Stereo state

OUT data I3 = 1 (Hi)
SD ON
OUT data I3 = 0 (Lo)
SD OFF

OUT data ADC0
AD00 to AD05
6 bit

Monaural/stereo

Note: *2. I/O-3 = 0 (input port) and OUT3 = 1 (Hi) must already be set in the DI data (IN2) settings.

Other settings

In the LA17000

Setting

When set

For normal operation

CF switch

Pin 10

When there is interference from
adjacent frequencies

Soft mute (AUDIO mute)

Pin 49

Hi: Forced mute

When setting mute

Lo: Mute off

When cancelling mute

AM/FM switch

Pin 6

Lo: AM

For AM reception

Hi: FM

For FM reception

Hi: Wide (wideband setting)

Lo: Narrow (narrowband
setting)

LA17000M

No. 6522-11/54

Correspondence of Pins Between the LA17000M, the LA1781M, and the LC72144M

LA1781

Pin Function

LA17000M

Pin Function

LC72144M

Pin No.

FN ANTD

FM RF AGC

FE GND

FM OSC

AM/FM OSC buff.

FE V

AM V

Noise AGC-Sense

Noise AGC-ADJ

AM 2nd OSC

Gate Out

Memory circuit pin

Pilot In

NC, MPX GND

MPX L-Out

MPX R-Out

Seek

AM/FM SD

Both I/O-3 and SD/ST-IND

Stop

FM ST IND

FMIN

PD1

PDS

XBUF

I/O-2

XIN

XOUT

I/O-1

HCTR/I-6

I/O-0

MRC sensor output

Pilot Can. ADJ

MPX VCO

GND

PHASE COMP.

AM/FM S-meter

MRC OUT

Continued on next page.

Both ADC0 and MRC
sensor output

IF count buffer and
seek/stop switch

LA17000M

No. 6522-12/54

Continued from preceding page.

LA1781

Pin Function

LA17000M

Pin Function

LC72144M

Pin No.

SNC control input

HCC control input

Noise canceller IN

AM/FM detector output

FM S-meter output

MUTE drive

AFC IN

QD OUT

CD IN

VREF

FMSD

GND Keyed AGC

HCC capacitor

AM L.C.

Pilot detector

IF AGC

AM IFT (IF output)

AM ANTD

W-AGC IN

FM Mute ON ADJ

RF AGC

AM 2nd MIX IN

FM IF BYPASS

FM IF IN

AM IF IN

1st IF amplifier output

AM MIX OUT

W-AGC IN

AM SD ADJ

1st IF IN

AM RF AGC OUT

N-AGC IN

1st MIX OUT

F.E.V

FM MIX IN

1st IF narrow IN

AM MIX IN

FM MIX IN

LA17000M

No. 6522-13/54

PLL Block Functions

· High-speed programmable divider

· FMIN

: 10 to 160 MHz .......................... Pulse swallower method

· General-purpose counter

· HCTR

: 0.4 to 25.0 MHz ........................ Frequency measurement

· Crystal oscillator

: Two frequencies selectable: 10.35/10.25 MHz

· Reference frequencies : 12 frequencies selectable:

50, 30, 25, 12.5, 6.25, 3.125, 10, 9, 3, 5, and 1kHz
*1 *1 *1
*1: Not available when using the 10.25 MHz crystal oscillator

· Phase comparator

· Dead zone can be controlled
· Unlock detection circuit
· Sub-charge pump for high-speed locking
· Deadlock clear circuit on chip

· A/D converter ................................ 6 bits: 1 input (linked directly to MRC sensor output)
· Serial data I/O

Communications with controller possible in CCB format

· Power-on reset circuit
· On-chip crystal oscillator output buffer
· 2nd IF injection signal for AM up conversion (10.35/10.25 MHz)
· I/O port .......................................... General-purpose I/O: four ports

LA17000M

No. 6522-15/54

PLL Block Pin Description

Symbol

Pin No.

Description

Function

Pin Circuit

XIN

X'tal OSC

XOUT

PLL IN

Chip enable

Clock

Input data

Output data

Power supply

Ground

· This is the PLL ground pin.

I/O-1

I/O-2

STSD SW

SEEK SW

ADC0

ADC input

Continued on next page.

A13297

A13298

A13302

A13303

A13299

A13300

A13301

A13304

Local
oscillator
signal input

· For connecting the crystal oscillator.

(10.35, 10.25, 7.2 or 4.5 MHz)

· FMIN is selected when DVS in the serial data

input is set to 1.

· The input frequency range is from 10 to

160 MHz.

· The signal is transmitted to the swallow

counter.

· The divisor can be set to a value in the range

272 to 65535.

· This pin is set high during serial data input to

the PLL (DI) or during serial data output (DO).

· This pin is the clock for data synchronization

during serial data input to the PLL (DI) or
during serial data output (DO).

· This is the input pin for serial data that is

transferred from the controller to the PLL.

· This is the output pin for serial data that is

transferred from the controller to the PLL.

· This is the PLL power supply pin. Supply 4.5 V

to 5.5 V to this pin when the PLL is operating.

· When power is first applied to this pin, the

power-on reset circuit operates.

· These are general-purpose I/O ports.
· The output circuits open-drain.
· During a power-on reset, I/O-1 and I/O-2

become input ports. STSD SW becomes an
output port, and is fixed low.

· These ports can be switched between input

and output according to the serial data that is
transferred from the controller (I/O-1, I/O-2,
STSD SW).

· This is a general-purpose I/O port.
· The output circuits are complementary

circuits.

· During a power-on reset, this port becomes

an input port.

· This port can be specified as an input or

output port by the serial data that is trans-
ferred from the controller.

· This is the A/D converter input pin.

The converter is a 6-bit successive-approxi-
mation A/D converter.
For details, refer to the page that describes
the A/D converter configuration.

General-
purpose
I/O ports

General-
purpose
I/O port

A13305

LA17000M

No. 6522-16/54

Continued from preceding page.

Symbol

Pin No.

Description

Function

Pin Circuit

PD1

PDS

HCTR

XBUF

Main
charge
pump
output

· This is the PLL charge pump output pin.

When the frequency of the local oscillation
signal frequency is divided by N is higher than
the reference frequency, a high level signal is
output from the PD1 pin. When the frequency
is lower, a low level signal is output. If the
frequencies match, the pin goes to high
impedance.

· A high-speed lockup circuit can be formed by

using this pin in combination with the main
charge pump.

· For details, refer to page that describes the

charge pump configuration.

· Serial data: HCTR is selected if CTS1 = 1 is

set.
· The input frequency is 0.4 to 25 MHz.
· The signal is passed through to the general-

purpose counter internally, via the 1/2
frequency divider. An integrating count can
also be kept.

· The count result is output from the MSB of

the general-purpose counter through the
output pin DO.

· For details, refer to page that describes the

general-purpose counter configuration.

· Serial data: Prohibited when HCTR = 0.

· This is the output buffer for the crystal

oscillator circuit.

· Serial data: When XB = 1 is set, the output

buffer operates and the crystal oscillator
signal (pulse) is output.
When XB = 0, this pin outputs a low level.
(When a power-on reset is executed, XB = 0
and the output buffer is fixed at the low level.)

Sub-charge
pump
output

General-
purpose
counter

X'tal
oscillator
buffer

A13306

A13307

A13309

A13308

XOUT

LA17000M

No. 6522-17/54

Procedures for Input and Output of Serial Data

Data I/O is handled through the Computer Control Bus (CCB), SANYO's audio IC serial bus format. This IC uses CCB
with 8-bit addressing.

I/O mode

Address

Description

[1]

IN1

· Control data input (serial data input) mode.
· 32-bit data input

[2]

IN2

· Control data input (serial data input) mode.
· 32-bit data input

[3]

OUT

· Data output (serial data output) mode.
· The bit count output is equal to the clock cycle count.

First Data IN1/2

First Data OUT

A13310

I/O mode setting

i) Serial Data Input (IN1/IN2)

ii) Serial data output (OUT)

*1: Because the DO pin is an N-channel open drain pin, the data transition time varies according to the pull-up resistance

and the board capacitance.

*2: The DO pin is normally open.

CTS0 CTS1 GT0

GT1

tEH

tEC

tES

tHD

tSU

tSUtHDtEStECtEH 0.45s
tLC 0.45s

tLC

A13311

AD13 AD12 AD11 AD10

tEH

tEC

tES

tHD

tSU

tSUtHDtEStECtEH 0.45s
tLCtDH 0.2s (*1)

tDH

tDC

(*2)

A13312

Internal data

LA17000M

No. 6522-19/54

Description of DI Control Data

No.

Control block/Data

Description

Related data

Programmable divider data

· This data sets divisor for the programmable divider. P15 is a binary value that is

designated as the MSB. The LSB changes depending on DVS and SNS.

P0 to P15

* DVS = 1 (DVS = 0: Prohibited)

· These values select the signal input pin (PLL IN) for the programmable divider,

and switch the input frequency range.

DVS, SNS

* For details, refer to "Programmable Divider Configuration."

Sub-charge pump

· This data controls the sub-charge pump.

control data

PDC, PDC1

* The sub-charge pump can be used to form a high-speed lockup circuit in

combination with PD0 and PD1 (main charge pump).

· For details, refer to the page on charge pump.

Reference divider data

· This is the reference frequency (fref) selection data.

R0 to R3

*1: Prohibited when X'tal OSC = 10.25 MHz.
*2: PLL INHIBIT (backup mode)

The programmable divider block stops, the PLL IN pin is pulled down to
GND, and the charge pump output goes to the floating state.

Continued on next page.

DVS

SNS

ISB

Divisor setting (N)

272 to 65535

DVS

SNS

Input pin

Input pin frequency range

PLLIN

10 to 160 MHz

PDC1

PDC0

Subcharge pump status

High impedance

Charge pump on (when unlocked)

Charge pump on (normal operation)

Reference frequency

Prohibited

12.5

6.25

3.125

9 *1

30 *1

*2 PLL INHIBIT + X'tal OSC STOP

*2 PLL INHIBIT

UL0, UL1,
DLC

(2)

(1)

(3)

LA17000M

No. 6522-20/54

Continued from preceding page.

No.

Control block/Data

Description

Related data

DO, I/O-5 pin control data

· This data determines the output on the DO pin and the I/O-5 pin.

ULD

DT0, DT1

IL0, IL1

end-AD: End of conversion by the A/D converter
end-UC: End of conversion by the general-purpose counter

* 1

* However, if the I/O-1 and I/O-2 pins are specified as output ports, these pins

are open.

Note: Cannot be used when X'tal OSC is set to STOP. (DO does not change.)

[When the reference divider data: R3 = R2 = R1 = 1 and R0 = 0]

A/D converter control data

· A/D converter conversion start data.

ADS = 1: A/D conversion reset and start

0: A/D conversion reset

ADS

ADI0

Continued on next page.

ULD

DT1

DT0

DO pin

Low when unlocked

end-AD

end-UC

IN (*1)

I/O-1

I/O-2

(4)

(5)

CEHi

A13315

Start

End

(I-1 changes)

IL1

Open

I-1 (pin status)

I-2 (pin status)

If I-1 changes, DO goes low. (Note)

ADI1

ADI0

AD input pin

Stopped

ADC0

Not usable

LA17000M

No. 6522-21/54

Continued from preceding page.

No.

Control block/Data

Description

Related data

· This data sets the general-purpose counter input pin (HCTR).

· General-purpose counter measurement start data

CTE = 1: Count start

= 0: Count reset

· This data determines the measurement time (frequency mode) and number of

periods (period mode) for the general-purpose counter.

· CTP = 0: When a count reset is executed (CTE = 0), the general-purpose

counter input is pulled down.

= 1: When a count reset is executed (CTE = 0), the general-purpose

counter input is not pulled down, and the wait time is reduced.
However, immediately after CTP = 1 is set, the start of the count
must wait until the general purpose counter input pin is biased.

· The input sensitivity is reduced when CTC = 1. (Sensitivity: 10 to 30 mVrms)

I/O port control data

· This data specifies whether an I/O port is an input port or an output port.

"data"= 0: Input port

= 1: Output port

I/O-1 to I/0-2

* During a power-on reset, I/O-0 and I/O-2 become input ports.

STSD SW becomes an output port.

· This data determines the status of the SEEK SW pin.

"data" = 0: 2.5[V] output

SEEK SW

* This pin is open and the midpoint bias is output by an external circuit.
"data" = 1: 0[V] or 5[V] output

* Determined by the OUT0 data.

· AM/FM SD, FM-ST IND output dual-purpose pin

SDST SW

"data" = 0: Fixed

= 1: Prohibited

Output port data

· This data determines the output on output ports O-0 through O-3.

"data" = 1: Open or Hi

OUT0 to OUT2

= 0: Low

* Invalid if specified as an input port or unlocked output.

· This data converts the general-purpose counter pin to an input port.

HCTR = 0: Prohibited

= 1: HCTR (general-purpose counter)

Continued on next page.

CTS1

Measurement time

Measurement mode

HCTR

Frequency

Not measured

HCTR

(6)

Frequency measurement mode

Period

GT1

GT0

Measurement Wait time (ms)

measurement

time (ms)

CTP = 0

CTP = 1

mode

3 to 4

1 to 2

1 period

3 to 4

1 to 2

1 period

7 to 8

1 to 2

2 periods

7 to 8

1 to 2

2 periods

OUT0 to OUT3

ULD

I/O-0 to I/O-3

ULD

I/O-0 to I/O-3

ULD

I/O-0 to I/O-3

ULD

CTS1

(7)

(8)

(9)

(10)

(11)

General-purpose counter

control data

CTS0, CTS1

CTE

GT0, GT1

CTP

CTC

General-purpose counter

input control data

HCTR

LA17000M

No. 6522-22/54

Continued from preceding page.

No.

Control block/Data

Description

Related data

Unlock detection data

· This data selects the phase error (øE) detection width that is used for evaluating

PLL lock.
If a phase error that exceeds the øE detection width in the following table is
generated, the signal is deemed to be unlocked. When the signal is unlocked,
the detection pin (DO or I/O-5) goes low.

UL1, UL0

· This is the crystal oscillator selection data.

* When a power-on reset is executed, 10.25 MHz is selected.

· Crystal oscillator buffer (XBUF) output control data.

XB = 0: Buffer output: OFF (This mode is selected when a power-on reset is

executed.)

XB = 1: Buffer output ON
* For FM reception (using the PD0 pin), XBUF output must be off.

· This data controls the phase comparator dead zone.

· When a power-on reset is executed, DZA is selected.

· This data is used to force the charge pump output to the low level (V

level).

DLC = 1: Low level

= 0: Normal operation

* If a deadlock occurs because the VCO control voltage (Vtune) is 0 V and VCO

oscillation is stopped, it is possible to escape the deadlock by forcing the
charge pump output to low level and setting Vtune to V

When a power-on reset is executed, normal operation mode is selected.

· This is the IC test data.

Set TEST0 = 0.
TEST1 = 0
TEST2 = 0

* When a power-on reset is executed, all the test data is set to zero.

(12)

ULD

DT0, DT1

R0 to R3

(13)

UL1

DT0

øE detection width

Detection pin output

Stop

Open

Direct output of øE

±0.5

Extend øE by 1 to 2 ms

±1

Extend øE by 1 to 2 ms

Unlocked output

1 to 2ms

A13316

XS1

XS0

X'tal OSC

Prohibited

10.25 MHz

10.35 MHz

DZ1

DZ0

Dead zone mode

DZA

DZB

DZC

DZD

(14)

(15)

(16)

Extention

Crystal oscillator circuit

XS0, XS1

Phase comparator control

data

DZ0, DZ1

Charge pump control data

DLC

IC test data

TEST0
TEST1
TEST2

LA17000M

No. 6522-23/54

DO Output Data (Serial Data Output) Configuration

[3] OUT mode

0 1 0 1 0 1 0 0

(2) U-CTR

(1) IN-PORT

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

AD05

AD04

AD03

AD02

AD01

AD00

(3) ADC0

(4) ADC1

First Data OUT

A13317

Address

: "0" data

No.

Control block/Data

Description

Related data

I/O port data

· I0 to I3 is the latched data reflecting the status of the input ports: I/O-0 to I/O-3.

The data is latched at the point that data output mode is set.

I3 to I0

The pin status is latched regardless of the input/output specification.
Pin status = Hi: 1

Low: 0

General-purpose counter

· C19 to C0 is the latched data reflecting the contents of the general-purpose

binary data

counter (a 20-bit binary counter).

C19

MSB of binary counter

C19 to C0

LSB of binary counter

A/D converter

· AD05 to AD00 is the latched data reflecting the results when the ADC0 pin

input signal undergoes AD conversion.

AD05

MSB

AD05 to AD00

AD00

LSB

(1)

(2)

(3)

I/O-1 to I/O-2

SEEK SW

HCTR

CTS0
CTS1

CTE

ADI1

ADS

ADC0 data

LA17000M

No. 6522-24/54

Programmable Divider Configuration

DVS SNS

Input pin

Divisor setting (N)

Input frequency range

(A)

PLL IN

272 to 65535

10 to 160 MHz

Minimum input sensitivity f[MHz]

(A) PLL IN

f < 130

130

f <160

40 mVrms

70 mVrms

General-purpose Counter Configuration

In the LA17000M, the general-purpose counter consists of a 20-bit binary counter. The count results can be read
through the DO pin, MSB first.

When using the general-purpose counter for cycle measurement, the measurement period can be selected from among 4,
8, 32, and 64 ms through the GT0 and GT1 data. The cycle of the signal that is input to the HCTR pin or the LCTR pin
can then be measured by counting the number of pulses that are input to the general-purpose counter within this mea-
surement period.
When using the general-purpose counter to measure a cycle, it is also possible to measure the cycle of a signal that is
input to the LCTR pin according to the number of check signals (refer to the "Check Signal Frequency" table below)
input to the general-purpose counter within one or two cycles of the signal that is input to the LCTR.

Check Signal Frequency

X tal OSC

10.25 MHz

10.35 MHz

fref = 30, 9, 3 kHz

fref other than 30, 9, 3 kHz

Check signal

10.25 kHz

1030 kHz

1150 kHz

CTS1

Input pin

Measurement mode

Frequency range

Input sensitivity

HCTR

Frequency

0.4 to 25.0 MHz

40 mVrms *1

*1 CTC = 0: 40 mVrms; however, when CTC = 1, the frequency range is HCTR: 8 to 12 MHz

CTC = 1: 70 mVrms

PLL IN

4bits

(A)

12bits

fvco/N

fref

fvco = fref × N

Swallow
Counter

Programmable

Divider

A13318

HCTR

3 4

7 8

11 12

1516

4/8/32/64

(FIF)

L
S
B

M
S
B

CTE

C = FIF × GT

GT1, GT0

A13319

1
2

CTS

General-purpose counter

(20-bit binary counter)

DO pin

LA17000M

No. 6522-25/54

CTC data: This is the input sensitivity switch data; when CTC = 1, the input sensitivity is degraded.

HCTR: Minimum input sensitivity standard f [MHz]

CTC

0.4

f < 8

f < 12

f < 25

0 (Normal mode)

40 mVrms

(1 to 10 mVrms)

1 (Degraded mode)

70 mVrms

(30 to 40 mVrms)

--: Not stipulated (operation not guaranteed)
( ): Actual performance estimates (reference value)

CTP data: This is data that determines the status of the general-purpose counter input pin (HCTR/LCTR) when a

general-purpose counter reset (CTE = 0) is executed.
CTP = 0: Pulls down the general-purpose counter input pin.

= 1: Does not pull down the general-purpose counter input pin, reducing the wait time to 1 or 2 ms.

When setting CTP = 1, do so at least 4 ms prior to starting the count (CTE = 1). If the counter is not to be
used, set CTP = 0.

IF Counter Operation

Before starting counting with the general-purpose counter, the general-purpose counter must first be reset by setting CTE
= 0. The general-purpose counter is made to start counting by setting serial data CTE = 1. The serial data is finalized
within the PLL by changing CE from high to low, but input to the HCTR pin must be started within the wait period after
CE is sent low at the very latest. After measurement ends, the count results from the general-purpose counter must be
read while CTE = 1. (Once CTE is set to zero, the general-purpose counter is reset.) Furthermore, the signal that was
input to the HCTR pin is passed through to the general-purpose counter after having been divided by 1/2 internally.
Therefore, the general-purpose count results are actually 1/2 the actual frequency of the signal that was input to the
HCTR pin.

Frequency measurement mode

Cycle

GT1

GT0

Measurement Wait time

measurement

time

CTP = 0

CTP = 1

mode

4 ms

3 to 4 ms

1 cycle

1 to 2 ms

7 to 8 ms

2 cycles

A13320

40 mVrms or more*
(when measuring frequency)
* CTC = 0: 40 mVrms

CTC = 1: 70 mVrms

Signal input

Measurement

time

Wait time

Frequency measurement time

CTE = 1
data

LA17000M

No. 6522-26/54

Integrated Count

* CTE: 0

· General-purpose counter reset

· General-purpose counter start
· Setting to "1" again causes a restart.

When using integrated counting, the count value is accumulated in the general-purpose counter.
Be careful about counter overflows.
Count value: 0

to FFFFF

(1048575)

When using integrated counting, resending serial data (IN1) with CTE = 1 restarts measurement with the
general-purpose counter, and the count results are added to the previous count results.

A/D Converter Configuration

This is a 6-bit successive-approximation converter with a conversion time of 0.56 ms. Full scale (when the data is 3F

)

is (63/96) x V

Count end

CTE=1

Start

Restart

Reset

CTE=1

CTE=0

A13321

Internal data latch

(CTE)

General-purpose counter

(integration)

ADO0

ADO1

ADO2

ADO3

ADO4

ADO5

ADS

ADC0

MSB

LSB

ADI0 ADI1

Vref

63
96

Vref max=×VDD

VDD

A13322

Multi-
plexer

Comparator

Evaluation

circuit

Decoder

: "0" data

DO pin

end-UC

LA17000M

No. 6522-27/54

ADI1

ADI0

Input pin

Prohibited

ADC0

Prohibited

Charge Pump Configuration

PDC1 PDC0

PDS (sub-charge pump status)

High impedance

Charge pump on (when unlocked)

Charge pump on (at all times)

If the unlocked state is detected during a channel change, the PDS (sub-charge pump) operates, R1

R1M/R1S, the

low-pass filter time constant is reduced, and lockup is accelerated.

* Unlock detection data: UL1 = 1 must be set. This sets the unlock detection width to "±0.5

s" or "±1

s" mode; if a

phase difference that is greater than the value in question is detected, the signal is unlocked and the sub-charge pump
operates. As the locked condition is approached and the phase difference falls to less than the unlocked detection
width, the sub-charge pump stops operating (goes to high impedance).

* Since the PLL block in the LA17000M does not provide an

external pin for ADI1, the function cannot be used. ADI0
is linked directly to the pin 34 MRC sensor output, and is
used exclusively for multipath signal intensity detection.

Conversion start

A13324

A13323

PDC0 PDC1

Unlock

PDS

PD1

DLC

CTS=1

tWA1

tAD

ADC0

tWA10.08 to 0.11ms
tWA20.08 to 0.09ms
tAD 0.56 to 0.62ms

end-AD

fvco/N

fref

Clock

UL0

UL1

DZ1

DZ0

Phase
Detector

Unlock
Detector
and
Subcharge
Pump Cont

(SUB)

(MAIN)

Conversion

Conversion end

D0, I/O-5 pin

DLC

PD1, PDS

Normal operation

Forced low

A13325

PD0

R1M

Vtune

VCC

R1S

PDS

LA17000M

No. 6522-28/54

Other Items

[1] Notes on the Phase Comparator Dead Zone

DZ1

DZ0

Dead zone mode

Charge pump

Dead zone

DZA

ON/OFF

0 s

DZB

ON/ON

0 s

DZC

OFF/OFF

+0 s

DZD

OFF/OFF

++0 s

Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the
ON/ON state, the loop can easily become unstable. This point requires special care when designing application
circuits.

The following problems may occur in the ON/ON state.
· Side band generation due to reference frequency leakage
· Side band generation due to both the correction pulse envelope and low frequency leakage

Schemes in which a dead zone is present (OFF/ON) have good loop stability, but have the problem that acquiring a
high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in
which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA
or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in
which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD,
which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which
either AM stereo is not used or an adequate AM stereo pilot margin can be achieved.

Dead Zone
The phase comparator compares fp to a reference frequency (fr) as shown in Fig. 1. Although the characteristics of
this circuit (see Fig. 2) are such that the output voltage is proportional to the phase difference ø (line A), a region
(the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal
circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide
a high S/N ratio.
However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularly-
priced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the
VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit
outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF
signal.

[2] Notes on the PLL IN and HCTR pins

Coupling capacitors must be placed extremely close to these pins. The capacitance should be about 100 pF. If a
capacitor with a capacitance of 100 pF or less is not used with HCTR in particular, there will be a long wait until the
bias level is reached, which may sometimes cause miscounting.

[3] Notes on IF counting

When using the general-purpose counter for IF counting, be certain to have the microcontroller determine whether
the IF-IC SD (Station Detector) signal is present or not, and to turn on the IF count buffer output and conduct the
count, but only if the SD signal is present. Conducting an auto search using only the IF count is not reliable, since
there is a possibility of stopping even where there is no station due to leaked output from the IF count buffer.

[4] Using the DO pin

Aside from data output mode, the DO pin can also be used to check for the completion of counting by the general-
purpose counter, unlock detection output, and to check for changes in the input pins. It is also possible to input the
status of the input pins (I/O-1, I/O-2) to the controller, unchanged, via the DO pin.

A13326

A13327

Dead Zone

Reference Divider

Programmable Divider

Phase
Detector

MIX

(ns)

(B)

(A)

LFP

VCO

Leak

Fig. 1

Fig. 2

LA17000M

No. 6522-29/54

[5] Cautions concerning the use of XBUF

When the XBUF output is on (AM up conversion is being used), the XBUF signal may leak to the adjacent pins
(PD0, I/O-3), so do not use PD0 and I/O-3 for AM reception control. (Use the PD1 pin for the AM reception charge
pump.) When using PD0 and I/O-3 for FM reception control, the XBUF output must be turned off (XB data = 0).

[6] Power supply pins

To filter out noise, insert a capacitor of at least 2000 pF between the power supply pins V

and V

. The capacitor

must be located as close to the pins as possible.

Tuner Block Pin Description

Pin No.

Function

Equivalent circuit

Description

Antenna damping drive
pin.

RF AGC

FET 2nd gate voltage control pin.

F.E.GND

OSC

OSC pin with built-in Tr. capacitor for
oscillator circuit.

ANT

1000pF

100

300

VCC

RF
AGC

AGC

DET

AGC

DET

KEYED

AGC

ANT

DAMPING
DRIVER

VCC

12k

FET

2ND GATE

VCC

18pF

20pF

60pF

The antenna damping current flows
to this pin when the pin 2: RF AGC
voltage is V

-V

A13328

A13329

A13330

Continued on next page.

Pin 62

LA17000M

No. 6522-30/54

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Description

F.E.V

, AM/FM switch

Pin 6 is shared for FM F.E.V

and

the AM/FM SW circuit.

AM OSC

First OSC for AM.
Permits oscillation up to the SW
band.
ALC circuit connected.

Noise AGC sensitivity

AGC adjusting pin

AM 2nd OSC

A13366

FM.F.E

AGC

VCC

510

100k

3.3V

GND

AM/FM Switch
Circuit

V6 voltage

Mode

OPEN

VCC

A L C

15k

0.01F

0.47F

200

Pin 8 is the noise sensitivity setting
pin. After setting a moderate field
(approximately 50 dB

), use the pin 9

AGC adjusting pin to make the
setting for weak fields (approximately
20 to 30 dB

Shared pin.
CF selectivity switch.
Select either 10.7 MHz 1st IF input
pin 72 or pin 78.
· A second local oscillation signal is

injected by the PLL XBuffer.

* The PLL X'tal is as follows:

AM 9 kHz step 10.35 MHz
AM 10 kHz step 10.25 MHz

(NDK AT-51 type: XTAL oscillator)

10k

51k

10k

5.6V

100pF

TO 2nd
MIX

PLL
XBuffer

A13331

A13332

A13367

Continued on next page.

SWON

pin 78 input

SOWOPen pin 78 input

LA17000M

No. 6522-34/54

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Description

AM/FM S-meter

Constant current drive-type S-meter
output.

Dedicated FM S-meter

When AM is set, pin 48 outputs a
1 mA current, which turns HCC OFF.

MRC control voltage
time constant

SNC control input pin

HCC control input pin

A13341

A13343

A13345

Continued on next page.

Controls sub-output with an input of 0
to 1 V.
SNC voltage is determined by the RA
and RB component voltage. This
sets the separation blend curve.

RB = 5 k

on chip

RA is external

10k

VCC

AM/FM

MRC

S-meter

AM/FM

The MRC detection time constant is
determined 1 k

and C2 when

discharging and by a constant
current of 7

A and C2 when

charging.

500

VCC

VREF

VCC

VREF

VCC

A13344

Controls high frequency output with
an input of 0 to 1 V.

Control through the MRC output is
also possible.

Use at least a 100 k

resistor when

using pin 48 FM S-meter for control.

to pin 44

LA17000M

No. 6522-35/54

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Description

Noise canceller input

AM/FM detection
output

IF S-meter output and
MRC DC input pin

Mute driver output

A13346

A13347

Continued on next page.

detec-

tion

output

detec-

tion

FM S-meter output block
MRC AC input block

Adjust an external 1-k

resistor to

attenuate and control the MRC AC
input.

A13348

1) The mute time constant is

determined by an external CR as
follows:
Attack time
T

= 10 k

Release time
T

= 50 k

2) Noise convergence adjustment

Fine adjustments can be made
when there is no input to the ANT
input by inserting a resistor
between pin 49 and GND.

3) Mute off function

Short pin 49 with GND using a
4-k

resistor.

VCC

10k

50k

4.2V

Pin 46: N.C. input
Input impedance 50 k

Pin 47: AM.FM detection output
For FM: Low impedance
For AM: 10 k

output

To improve low-band separation, use
a coupling capacitor of at least 10

HOLE

DET

SOFT

MUTE

SEEK
OFF

VCC

0.1F

50k

10k

50k

MUTE
AMP.

SD circuit

BAND
MUTE

MRC input

LA17000M

No. 6522-36/54

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Description

AFC

QD output

QD input

REF

FM SD Adi

Keyed AGC
AM stereo buffer

A13349

A13350

Continued on next page.

A13351

· R1: Resistor that determines the

band muting function.
Increasing the value of R1 narrows
the band
Reducing the value of R1 widens
the band.

· Null voltage

Voltage between pins 50 and 53
during tuning:
V

50-53

= 0 V

Band muting turns on when
|V

50-53

0.7 V.

= 4.9V

HOLE

DET

0.1F VREF

VCC

390

3pF

Quadrature

detection

Current of 130

A flows from pin 54

and comparison voltage is
determined by external resistance.

The keyed AGC operates when the
voltage divided by the 6.4-k

and

3.6-k

resistors on S-meter output

pin 42 falls below the voltage
determined by the resistor between
pin 55 and GND.

Shared pin for the AM stereo decoder
IF buffer.

KEYED

AGC

SD ADJ

130A

6.4k

3.6k

1.3V

50pF

150

90A

VCC

AM IF out

S-meter

BAND
MUTE

1F limiter AMP

Comparator

LA17000M

No. 6522-40/54

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Description

69
72
78

MIX output 130

MIX input

W-AGC IN
AM SD Adjust

N-AGC IN
mute attenuation
adjusting pin

A13362

A13363

Continued on next page.

A13364

· 1ST.IF amplifier I/O pin
· Inversion amplifier
V78 = 2 V Narrow 1st IF input
V72 = 2 V Wide 1st IF input
Input impedance
R

= 330

V59 = 5.3 V
Output impedance
R

OUT

= 330

When SW1 open, SW2 short
When SW1 short, SW2 open
Switched by the CF band, switched
by voltage on pin 10.

Pin 71, 74 DC cut capacitors are on
chip.
The AGC on level is determined by
the capacitance of C1 and C2.

Pin 71 is the SD sensitivity adjusting
pin for AM.

Output current I71 = 50

A, and V71

varies according to the external
resistance.
SD is put into operation by
comparing V71 with the S-meter
voltage.

Wire the MIX coil that is connected to
the pin 70 MIX output to pin 56
(V

Pin 65 MIX input.
Input impedance
330

IF OUT

W IF IN

N IF IN

2.75V

300

500

1.3k

SW2

SW1

VCC

300

W-AGC

OSC

330

N-AGC

30pF

50pF

50A

AM SD

MIX
IN

MIX

OUT

Pin 56
V

pin 56

Pin 77
V

S-meter

IF amplifier output
IF amplifier input wide
input
IF amplifier input
narrow input

LA17000M

No. 6522-42/54

Methods for Using the LA17000M

(1) About V

and GND

Pin 56

for FM IF, AM, NC, MPX, and MRC

Pin 39

GND for FM IF and AM

Pin 14

GND for NC, MPX and MRC

Pin 77

for FM FE, AM 1st MIX, and 1st OSC

*Pin 6

for FM FE and AGC, and AM/FM switch

Pin 3

GND for FM FE, AM 1st MIX, and 1st OSC

(2) Notes on AM coil connection

for the 1st OSC coil that is connected to pin 7 should have the same electric potential as pin 77.

Connect pin 61 IFT to pin 70 MIX coil. V

should have the same electric potential as pin 56.

(3) AM/FM switch

Pin 6 serves as FM, FE, and RFAGC V

(4) Relationship between pin 38 and pin 17

4-1. For FM

Pin 17

STEREO indicator and SD dual-purpose pin

Pin 38

DC input SEEK, STOP pin (control pin)
AC output IF count buffer pin

SW1

SW2

Pin 38 voltage

Pin 17

OPEN

5 V

IF count buffer on

OPEN

2.5 V

IF count buffer on

High-speed SD

0.7 V or less

OFF

Stereo indicator

Relationship Between Pin 38 Control Method and Output from Pins 38 and 17

6pin

3.3

A13369

Pin 6 voltage

Mode

OPEN

IF count buffer

51k

100k

51k

SW1

SW2

A13370

A13371

0 to several k

LA17000M

No. 6522-43/54

Relationship between FMSD, IF count buffer output, S-meter, and mute drive output

ON as

OFF

SD ON

V38DC

V38AC

V17

V49

V54

V42

2.5V

A13372

Note: IF count output is off in the LA1780/81. Turn the

IF count output on in the LA17000M only.
(This is done for use in detecting interference from
adjacent frequencies.)

S-meter

larger

smaller

V49

0.7 V or

IF count output ON

IF count

buffer

Monaural

Stereo

V49

0.7 V or

Switch this mode for use in SD
detection in RDSAF search, etc.

Use 2.5 V mode for detecting interference
from adjacent frequencies, and confirm
the IF count frequency.

Band

mute

About FM SD

FM IF

HOLE

CLET

STEREO

IND

4.9V

2.5V 5V

SD
STEREO/MONO

A13373

51k

Connected
directly to PLL
and I/O-3

IF count output

IF count buffer

Mute drive

output

S-

meter

LA17000M

Block Diagram

No. 6522-48/54

FM
ANTD

ANT

FM RF
AGC

FE
GND

FM
OSC

AM/FM
SW

AM
OSC

NC
Sens

NC
AGC

AM
OSC

Gore
OUT

MPX
Pdot IN

NC MPX

GND

SD
ST-IND

PLL IN

PD1

AM/FM
S-METER

MRC
OUT

SNC

HCC

DET
OUT

SEP
ADJ

FM
S-METER

MUTE
DRIVE

AFC
IN

QD
OUT

QD
IN

VREF

FM
SD

KEYED
AGC

VCC

C.
HCC

AM
LC

PILOT
DET

IF
AGC

PLL
VSS

PDS

XBUFF

I/O-2

X' IN

X' OUT

I/O-1

HCTR

SEEKSW

MPX VCO

IF COUNT BUFF
SEEK/STOP

switch

CSB912TF108

GND

PHASE
COMP

AM DET

AM ANTD
WIDE AGC

FM MUTE
ON ADJ

RF AGC

2nd MIX IN

FM IF BYPASS

VSM
SHIFTER

FM IF
IN

1st IF OUT

AM MIX OUT

AM SD ADJ

WIDE AGC IN

1st IF IN

AM RF AGC OUT

N-AGC IN
MUTE ATT ADJ

MIX OUT

FE VCC

1st IF
Narrow IN

AM 1st
MIX IN

FM
MIX IN

3.3

0.022

0.01

0.47

0.01

0.022

0.015

6800pF

0.01

30k

350

51k

30k

10k

22k

51k

10k

11k

300

51k

470

100k

510

10k

24k

30k

12k

62k

82k

560

56k

33k

1000pF

10k

50k

5.6k

47k

100k

51k

10k

100k

10k

10pF

300pF

150pF

100pF

30pF

VCC=8V

FM ANT IN

5pF

AGC

HPH

HOLE

DET

F.F.19k

PHASE

COMP.

VCO

PILOT

DET.

CCB

I/F

POWER

RESET

PHASE

DETECTOR

CHARGE

PUMP

F.F.19k

F.F.30k

F.F.

PILOT

CAN.

UNTVERSAL

COUNTER

DATA SHIFT REGISTER

LATCH

12Bits

PROGRAMMABLE

DIVIDER

SWALLOW

COUNTER

1/16,1/17 4Bits

REFERENCE

DIVIDER

TRIG

HCC

SNC

VCO

STOP

OC-C

DET

AFC

CI AMP

LPF

TRIG

GATE

MIX

ANT

OSC

BUFF

OSC

Q.DET

MUTE

AMP.

MUTE

DRIVE

DET

AGC

L.C.

BUFF

OSC

BUFF

1ST

OSC

BUFF

IF LIMIT

AMP.

Keyed

AGC

MAIN

SUB
DEC

MAT

RIX

F.E

REG

FM/AM

SWICH

AM/FM

VREF

W.B AGC

RF AGC

AM SM

AM SD

FM SM

FM SD

IF BUFFER

MRC

RF AGC

WB AGC

0.015

0.22

3.3

15pF

0.022

100

0.022

FC18

100

1MH

0.022

100

2.2

0.47

0.22

2200pF

0.1

0.47

0.01

0.22

0.47

0.01

0.022

Pdot C
ADJ

100pF

24pF

micro contlorrer

10.25

MHz

PLL VDD=5V

FM BF GND

L-CH

CF SW

R-CH

FMIF AMNC

MPX VCC

FM/AM

FMIF AM

GND

SEEK

AM/FM SD

STOP

FM ST IND

SDSTSW

I/O-1

To
microcontroller

MUTE
OFF(RDS)

AM
(STEFEO)
IF OUT

MRC
SENOR
AUTO ADJ

200k

100

100k

220

30k

100k

150

0.022

5pF

0.022

0.1

0.022

100

1000pF

37pF

6pF

1000pF

8pF

1000pF

18pF

62pF

AM ANT IN

AM V

A13385

LA17000M

No. 6522-49/54

Recommended External Components

Component name

Manufacturer

Component

Component model number

number

AM loading coil

Toko

7TL-269ANS-0720Z

Sumida Electronics Co., Ltd.

SA-1062

AM ANT-IN

Toko

7PSU-385BNS-027Z

Sumida Electronics Co., Ltd.

SA-1048

AM RF LPF

Toko

5VUS-A286LBIS-15327

Sumida Electronics Co., Ltd.

SA-1051

AM choke coil

Toko

8RB-187LY-222J

Sumida Electronics Co., Ltd.

RC875-222J

AM 2nd MIX coil

Toko

5PG-5PGLC-5310N

Sumida Electronics Co., Ltd.

SA-264

AM IF coil

Toko

7PSGTC-50002Y=S

Sumida Electronics Co., Ltd.

SA-1063/SA-1112

AM OSC1 coil

Toko

7KSS-V666SNS-213BY

Sumida Electronics Co., Ltd.

SA-359

AM/FM MIX coil with

Toko

L10

7PSG-8261N-5202D=S

selectivity switch

AM/FM MIX coil

Sumida Electronics Co., Ltd.

L10

SA-266

without selectivity switch

Toko

371DH-1108FYH

FM detection coil

Sumida Electronics Co., Ltd.

L14

SA-208

Toko

DM600DEAS-8407GLF

FM OSC coil

Sumida Electronics Co., Ltd.

L11

SA-125 (JP), SA-278 (US)

Toko

T-666NF-251APZ (JP), T-666SNF-2471B (US)

FM RF coil

Sumida Electronics Co., Ltd.

L12

SA-143 (JP), SA-250 (US)

Toko

T-666NF-269X (JP), T-666SNF-246JA (US)

FM ANT coil

Sumida Electronics Co., Ltd.

L13

SA-144 (JP), SA-231 (US)

Toko

T-666NF-268Z (JP), T-666SNF-244X (US)

MPX ceramic oscillator

Murata Manufacturing Co., Ltd.

VCO1

CSB912JF108 (912 kHz)

Kyocera

KRB-912F108 (912kHz)

PLL X'tal oscillator

Nihon Dempa kogyo

VCO2

LN-P-0001 (10.25, 10.35 MHz)

FM ceramic filter

Murata Manufacturing Co., Ltd.

CF1

SFE 10.7MS3A50K-A

FM/AM narrow band

Murata Manufacturing Co., Ltd.

CF2

SFE 10.7 MTE

ceramic filter

AM ceramic filter

Toko

CF3

LFCM450H

Murata Manufacturing Co., Ltd.

SFPS450H

AM pin diode

SANYO Electric Co., Ltd.

PIN1

1SV234/267

AMRF FET+TR

SANYO Electric Co., Ltd.

FET1

FC18

AM OSC1 varactor

SANYO Electric Co., Ltd.

VD2

SVC252/253

FM pin diode

SANYO Electric Co., Ltd.

PIN2

1SV234

FM RF amplifier FET

SANYO Electric Co., Ltd.

FET2

3SK263/264

FM RF/ANT/OSC varactor

SANYO Electric Co., Ltd.

VD3

SVC231/208

LA17000M

No. 6522-52/54

-80

-100

-60

-40

-20

-80

-100

-60

-40

-20

100

120

140

-20

100

120

140

-60

-80

-40

-20

-60

-80

-40

-20

100

120

140

100

120

140

VSM

MOD ON

MOD OFF

THD 100

THD 80
fm=400Hz

THD 30
fm=400Hz

THD 30

80dBSN

60dBSN

40dBSN

40dBIN

60dBIN

80dBIN

fud modu ON

SEP

AMR

, THD - V, %

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz

VCC=8.5V

fD=1000kHz

fm=400Hz

modu=30

fuD=1040kHz

fm=1kHz ON/OFF

modu=30

VCC=8.5V

fD=1000kHz

fm=400Hz

modu=30

fuD=1400kHz

fm=1kHz ON/OFF

modu=30

VCC=8.4V

fr=1MHz
fm=1kHz
dev=30

-40

-20

100

-40

-20

100

-40

-20

100

-40

-20

100

dev=75kHz

VSM=60dB

40dB

20dB

-20dB

dev=22.5kHz

- dB

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=kHz
ANT IN=80dB

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz
ANT IN=80dB

FM I/O Characteristics

AM I/O Characteristics

AF output, noise dB

AM2 Signal Interference Characteristics

ANT input, IN dB

otal harmonic distortion,

THD %

S-meter voltage,

FM Antenna input Temperature Characteristics (1)

FM Antenna input Temperature Characteristics (2)

Ambient temperature, Ta °C

Separation, Sep -- dB

FM Antenna input Temperature Characteristics (3)

FM Antenna input Temperature Characteristics (4)

LA17000M

No. 6522-53/54

-40

-20

100

-40

-20

100

-40

-20

100

-40

-20

100

120

100

dev=80

dev=30

VSM=60dB

40dB

20dB

-20dB

AGCFOM

AGCFOM - dB

VCC=8.4V

fr=1MHz
fm=400Hz
dev=30
ANT IN=80dB

VCC=8.4V

fr=1MHz
fm=400Hz
dev=30

VCC=8.4V

fr=1MHz
fm=400Hz
dev=30

VCC=8.4V

fr=1MHz
fm=400Hz
ANT IN=80dB

-40

-20

100

-40

-20

100

-40

-20

100

-60

-40

-80

-20

S/N

W-AGC

N-AGC

AMR

S/N, AMR - dB

SD, W-AGC N-AGC

- dB

100

120

fm=1kHz

fm=10kHz

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz
ANT IN=80dB

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz

VCC=8.4V

fr=98.1MHz
fm=1kHz
dev=22.5kHz

FM Antenna input Temperature Characteristics (5)

FM Antenna input Temperature Characteristics (6)

Ambient temperature, Ta °C

Output voltage,

dBm

Ambient temperature, Ta °C

FM Antenna input Temperature Characteristics (7)

AM Antenna input Temperature Characteristics (1)

AM Antenna input Temperature Characteristics (2)

otal harmonic distortion,

THD %

S-meter voltage,

Ambient temperature, Ta °C

SD sensitivity

, SD dB

AM Antenna input Temperature Characteristics (3)

AM Antenna input Temperature Characteristics (4)

LA17000M

No. 6522-54/54

-40

-20

100

-40

-20

100

-40

-20

100

120

100

120

W-AGC

N-AGC

W-AGC, N-AGC - dB

S/N - dB

-40

-60

-80

-20

S/N

VCC=8.4V

fr=1MHz
fm=400Hz
dev=30
ANT IN=80dB

VCC=8.4V

fr=1MHz
fm=400Hz
dev=30
ANT IN=80dB

VCC=8.4V

fr=1MHz
fm=400Hz
dev=30

AM Antenna input Temperature Characteristics (5)

AM Antenna input Temperature Characteristics (6)

AM Antenna input Temperature Characteristics (7)

Output voltage,

dBm

Ambient temperature, Ta °C

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

This catalog provides information as of June, 2001. Specifications and information herein are subject to
change without notice.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LA17000M

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: LA17000M