Ordering number : ENN7256

80102AS (OT) No. 7256 -1/14

Overview

The LB11870 is a three-phase brushless motor driver
developed for driving the motors used with the polygonal
mirror in laser printers and plain paper copiers. It can
implement, with a single IC chip, all the circuits required
for polygonal mirror drive, including speed control and
driver functions. The LB11870 can implement motor drive
with minimal power loss due to its use of direct PWM
drive.

Functions and Features

· Three-phase bipolar drive
· Direct PWM drive
· Includes six high and low side diodes on chip.
· Output current control circuit
· PLL speed control circuit
· Phase lock detection output (with masking function)
· Includes current limiter, thermal protection, rotor

constraint protection, and low-voltage protection circuits
on chip.

· Deceleration type switching circuit (free running or

reverse torque)

· PWM oscillator
· Power saving circuit

Package Dimensions

unit: mm

3265-HSSOP48

17.8

10.5

0.65

7.9

(4.9)

0.1

2.4max

(2.2)

(6.2)

0.2

1.5

0.65

(0.45)

1.3

0.2

SANYO: HSSOP48 (375 mil)

[LB11870]

LB11870

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Three-Phase Brushless Motor Driver

for Polygonal Mirror Motors

Monlithic Digital IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

max

Output current

max

500 ms

1.8

Allowable power dissipation 1

Pd max1

Independent IC

0.85

Allowable power dissipation 2

Pd max2

Mounted on a PCB (114.3

76.1

1.6 mm, glass epoxy)

1.72

Operating temperature

Topr

20 to +80

°C

Storage temperature

Tstg

55 to +150

°C

Specifications

Absolute Maximum Ratings

at Ta = 25°C

No. 7256 -2/14

LB11870

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage range

9.5 to 28

5 V constant voltage output current

IREG

0 to 20

LD pin applied voltage

VLD

0 to 28

LD pin output current

ILD

0 to 15

FGS pin applied voltage

VFGS

0 to 28

FGS pin output current

IFGS

0 to 10

Allowable Operating Ranges

at Ta = 25°C

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply current 1

Supply current 2

In stop mode

3.5

5.0

[5 V Constant Voltage Output Circuit]

Output voltage

VREG

4.65

5.0

5.35

Voltage regulation

VREG1

= 9.5 to 28 V

130

Load regulation

VREG2

= 5 to 20 mA

Temperature coefficient

VREG3

Design target value

mV/°C

[Output Block]

Output saturation voltage 1

Vosat1

= 0.5 A, V

(SINK) + V

(SOURCE)

1.9

2.4

Output saturation voltage 2

Vosat2

= 1.2 A, V

(SINK) + V

(SOURCE)

2.6

3.2

Output leakage current

leak

100

µA

Lower diode forward voltage 1

VD1-1

ID = 0.5 A

1.0

1.3

Lower diode forward voltage 2

VD1-2

ID = 1.2 A

1.4

1.8

Upper diode forward voltage 1

VD2-1

ID = 0.5 A

1.2

1.6

Upper diode forward voltage 2

VD2-2

ID = 1.2 A

1.9

2.4

[Hall Amplifier Block]

Input bias current

IHB

0.5

µA

Common-mode input voltage range

VICM

VREG 2.0

Hall input sensitivity

mVp-p

Hysteresis width

(HA)

Input voltage: Low to high

VSLH

Input voltage: High to low

VSHL

[FG Schmitt Block]

Input bias current

IB (FGS)

0.5

µA

Common-mode input voltage range

VICM (FGS)

VREG 2.0

Input sensitivity

(FGS)

mVp-p

Hysteresis width

(FGS)

Input voltage: Low to high

VSLH (FGS)

Input voltage: High to low

VSHL (FGS)

[PWM Oscillator]

High-level output voltage

(PWM)

2.65

2.95

3.25

Low-level output voltage

(PWM)

0.9

1.2

1.5

External capacitor charge current

ICHG

VPWM = 2 V

µA

Oscillator frequency

f (PWM)

C = 680 pF

kHz

Amplitude

V (PWM)

1.45

1.75

2.05

Vp-p

[FGS Output]

Output saturation voltage

(FGS) IFGS = 7 mA

0.15

0.5

Output leakage current

IL (FGS)

= V

µA

[CSD Oscillator Circuit]

High-level output voltage

(CSD)

3.2

3.5

3.8

Low-level output voltage

(CSD)

0.9

1.1

1.3

Amplitude

V (CSD)

2.15

2.4

2.65

Vp-p

External capacitor charge current

ICHG1

13.5

9.5

5.5

µA

External capacitor charge current

ICHG2

µA

Oscillator frequency

f (CSD)

C = 0.068 µF

Electrical Characteristics

at Ta = 25°C, V

= VM = 24 V

Continued on next page.

No. 7256 -3/14

LB11870

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

[Phase Comparator Output]

High-level output voltage

VPDH

= 100 µA

VREG 0.2

VREG 0.1

Low-level output voltage

VPDL

= 100 µA

0.2

0.3

Output source current

IPD+

VPD = VREG/2

0.5

Output sink current

IPD

VPD = VREG/2

1.5

[Lock Detection Output]

Output saturation voltage

(LD)

ILD = 10 mA

0.15

0.5

Output leakage current

IL (LD)

= V

µA

[Error Amplifier Block]

Input offset voltage

(ER)

Design target value

Input bias current

IB (ER)

µA

Output H level voltage

(ER)

= 500 µA

VREG 1.2

VREG 0.9

Output L level current

(ER)

= 500 µA

0.9

1.2

DC bias level

VB (ER)

VREG/2

[Current limiter Circuit]

Drive gain 1

GDF1

When the phase is locked

0.4

0.5

0.6

deg

Drive gain 2

GDF2

When not locked

0.8

1.0

1.2

deg

Limiter voltage

VRF

-V

0.45

0.5

0.55

[Thermal Shutdown Operation]

Thermal shutdown operating temperature

TSD

Design target value (junction temperature)

150

175

°C

Hysteresis width

TSD

Design target value (junction temperature)

°C

[Low-Voltage Protection]

Operating voltage

VSD

8.1

8.45

8.9

Hysteresis width

VSD

0.2

0.35

0.5

[CLD Circuit]

External capacitor charge current

ICLD

4.3

µA

Operating voltage

(CLD)

3.25

3.5

3.75

[CLK Pin]

External input frequency

fI (CLK)

0.1

kHz

High-level input voltage

(CLK)

3.5

VREG

Low-level input voltage

(CLK)

1.5

Input open voltage

(CLK)

VREG 0.5

VREG

Hysteresis width

(CLK)

0.35

0.5

0.65

High-level input current

(CLK)

VCLK = VREG

µA

Low-level input current

(CLK)

VCLK = 0 V

280

210

µA

[S/S Pin]

High-level input voltage

(SS)

3.5

VREG

Low-level input voltage

(SS)

1.5

Input open voltage

(SS)

VREG 0.5

VREG

Hysteresis width

(SS)

0.35

0.5

0.65

High-level input current

(SS)

VS/S = VREG

µA

Low-level input current

(SS)

VS/S = 0 V

280

210

µA

[BRSEL Pin]

High-level input voltage

(BRSEL)

3.5

VREG

Low-level input voltage

(BRSEL)

1.5

Input open voltage

(BRSEL)

VREG 0.5

VREG

High-level input current

(BRSEL)

BRSEL

= VREG

µA

Low-level input current

(BRSEL)

BRSEL

= 0 V

220

160

µA

No. 7256 -4/14

LB11870

Three-Phase Logic Truth Table (IN = [H] indicates a condition in which: IN+ > IN)

IN1

IN2

IN3

OUT1

OUT2

OUT3

Pin Arrangement

Pdmax -- Ta Characteristics Curve

LB11870

VREG

OUT3

VCC2

S/S

CLK

BRSEL

FGS

CLD

FRAME

GND1

FGIN

PWM

GND2

FGIN+

FRAME

IN3

IN2

IN2+

OUT1

IN3+

OUT2

VCC1

GND3

VM1

VM2

CSD

FGFIL

TOC

IN1

IN1+

2.0

0.8

1.6

1.2

0.4

100

0.85W

0.476W

0.963W

1.72W

Mounted on a board (114.3

76.1

1.6mm, glass epoxy)

Pd max -- Ta

Ambient temperature, Ta --

Power dissipation, Pd max -- W

Independent IC

No. 7256 -5/14

LB11870

Pin Functions

Pin No.

OUT1

OUT2

OUT3

Outputs

The PWM signal controls the duty from the low side transistor.

IN1+, IN1

IN2+, IN2

IN3+, IN3

11, 12

9, 10

6, 8

Hall inputs for the three phases

The logic H state means that V

+ is greater than V

FG IN+

FG comparator noninverting input

FG IN

FG comparator inverting input

GND1

Control system ground

GND2

Subsidiary ground.

PWM

Sets the PWM oscillator frequency. Insert a capacitor between this pin and ground.

Current control circuit frequency characteristics correction. Insert a capacitor between this pin and ground.

Phase comparator output. Outputs the phase error as changes in the pulse duty.

Error amplifier input

Error amplifier output

TOC

Torque command input. This pin is normally connected to the EO pin. When the TOC potential falls, the low side output
transistor on duty is changed and the torque increases.

FGFIL

FG filter connection. Insert a capacitor between this pin and ground if noise on the FG signal is a problem.

CSD

Sets the operating time for the rotor constraint protection circuit and the initial reset operation.

Insert a capacitor between this pin and ground. If the rotor constraint protection circuit is not used, insert a resistor in
parallel with this capacitor.

CLD

Sets the phase locked signal mask time. Insert a capacitor between this pin and ground. Leave this pin open if there is no
need to mask.

FGS

FG Schmitt output. This is an open-collector output.

Phase locked state detection output. This output goes to the on state when the PLL phase is locked. This is an open-
collector output.

S/S

Start/stop control input. Low: start, High or open: stop.

CLK

Clock input. The maximum input frequency is 10 kHz.

BRSEL

Deceleration control switching input. Low: Reverse torque control, High or open: free running.

An external Schottky barrier diode is required on the output low side if reverse torque control is used.

Smoothes the RF waveform. Insert a capacitor between this pin and ground.

VREG

5 V regulator output (control circuit power supply). Insert a capacitor between this pin and ground for power supply
stabilization.

VM1

Output block power supply. Short this pin to VM2.

VM2

Output current detection. Insert a resistor between this pin and V

The maximum output current IOUT is set to be IOUT = 0.5/Rf.

Upper diode cathode connection. Short this pin to V

Power supply. Insert a capacitor between this pin and ground to assure that noise does not enter the IC.

GND3

Output circuit block ground.

FRAME

Connect this pin to ground. The FRAME pin is connected internally to the metal surface on the back of the package. To
improve thermal dissipation, solder this metal surface to the PCB.

2, 4, 5, 7

18, 20, 30

31, 41, 42

43, 45, 47

Since these pins are not connected to the IC internally, they can be used for wiring connections.

No. 7256 -7/14

LB11870

Pin Functions

Pin No.

Function

Equivalent circuit

Motor drive output

OUT1

OUT2

OUT3

300

VCC1

VREG

300

Output block ground

GND3

Output block power supply and current detection.

Insert the resistor Rf between this pin and V

The output current will be limited to the current value
I

OUT

= VRF/Rf.

VM1

VM2

Upper diode cathode connection. Short this pin to V

Hall element inputs.

The high state is when IN+ is greater than IN-, and the
low state is the reverse.

An amplitude of at least 100 mVp-p (differential) is
desirable for the Hall element signal inputs. If noise on
the Hall signals is a problem, insert capacitors between
the IN+ and IN inputs.

IN1+

IN1

IN2+

IN2

IN3+

IN3

VREG

300

FG input.

If noise on the FG signal input is a problem, connect a
filter consisting of either a capacitor or a capacitor and a
resistor.

FGIN+

FGIN

Control circuit block ground

GND1

SUBGND pin

GND2

Continued on next page.

No. 7256 -9/14

LB11870

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Torque command voltage input.

This pin is normally connected to the EO pin. When the
TOC voltage falls, the lower output transistor on duty is
increased.

TOC

VREG

300

FG filter connection.

If noise on the FG signal input is a problem, insert a
capacitor (up to about 2200 pF) between this pin and
ground.

FGFIL

VREG

Sets the rotor constraint protection circuit operating time
and the initial reset pulse.

A protection operating time of about 8 seconds can be
set by insert a capacitor of about 0.068 µF between this
pin and ground. If the rotor constraint protection circuit is
not used, insert a resistor and a capacitor in parallel
between this pin and ground. (Values: about 220 k

and

4700 pF)

CSD

VREG

300

Sets the phase lock state signal mask time.

A mask time of about 90 ms can be set by inserting a
capacitor of about 0.1 µF between this pin and ground.
Leave this pin open if masking is not required.

CLD

VREG

300

FG Schmitt output

FGS

VREG

Continued on next page.

No. 7256 -10/14

LB11870

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Phase lock state detection output.

This output goes to the on state (low level) when the
phase is locked.

VREG

Start/stop control input

Low: 0 to 1.5 V

High: 3.5 V to VREG

Hysteresis: 0.5 V

Low: start. This pin goes to the high level when open.

S/S

VREG

22k

Clock input.

Low: 0 to 1.5 V

High: 3.5 V to VREG

Hysteresis: 0.5 V

CLK

= 10 kHz (maximum)

If noise is a problem, use a capacitor to remove that
noise at this input.

CLK

VREG

22k

Deceleration switching control input.

Low: 0 to 1.5 V

High: 3.5 V to VREG

This pin goes to the high level when open.

Low: reverse torque control, High: free running. An
external Schottky barrier diode is required on the output
low side if reverse torque control is used.

BRSEL

VREG

30k

RF waveform smoothing.

If noise on the RF waveform is a problem, insert a
capacitor between this pin and ground.

VREG

500

Continued on next page.

Overview of the LB11870

1. Speed Control Circuit

This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (falling edges
on the FGIN+ and FGS signals), and the IC uses the detected error to control motor speed.
During this control operation, the FG servo frequency will be the same as the CLK frequency.

(servo) = f

CLK

2. Output Drive Circuit

To minimize power loss in the output circuits, this IC adopts a direct PWM drive technique. The output transistors are
always saturated when on, and the IC adjusts the motor drive output by changing the output on duty. The low side
output transistor is used for the output PWM switching.
Both the high and low side output diodes are integrated in the IC. However, if reverse torque control mode is selected
for use during deceleration, or if a large output current is used and problems occur (such as incorrect operation or
waveform disruption due to low side kickback), a Schottky diode should be inserted between OUT and ground. Also,
if it is necessary to reduce IC heating during steady-state (constant speed) operation, it may be effective to insert a
Schottky diode between V

and OUT. (This is effective because the load associated with the regenerative current

during PWM switching is born not by the on-chip diode but by the external diode.)

3. Current Limiter Circuit

The current limiter circuit limits the peak level of the current to a level determined by I = VRF/Rf (where VRF =
0.5 V (typical) and Rf is the value of the current detection resistor). The current limiter operates by reducing the
output on duty to suppress the current.
The current limiter circuit detects the reverse recovery current of the diode due to PWM operation. To assure that the
current limiting function does not malfunction, its operation has a delay of about 2 µs. If the motor coils have a low
resistance or a low inductance, current fluctuations at startup (when there is no reactive power in the motor) will be
rapid. The delay in this circuit means that at such times the current limiter circuit may operate at a point well above
the set current. Designers must take this increase in the current due to the delay into account when setting the current
limiter value.

4. Power Saving Circuit

This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is
implemented by removing the bias current from most of the circuits in the IC. However, the 5 V regulator output is
provided in the power saving state.

5. Reference Clock

Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although
the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor.
If the IC is set to the start state when the reference clock signal is not present, if the rotor constraint protection circuit
is used, the motor will turn somewhat and then motor drive will be shut off. However, if the rotor constraint
protection circuit is not used, and furthermore reverse torque control mode is selected for deceleration, the motor will
be driven at ever increasing speed in the reverse direction. (This is because the rotor constraint protection circuit
oscillator signal is used for clock cutoff protection.) Applications must implement a workaround for this problem if
there is any possibility whatsoever for it to occur.

6. Notes on the PWM Frequency

The PWM frequency is determined by the value of the capacitor C (in F) connected to the PWM pin.

PWM

=. 1 / (43000

If a 680 pF capacitor is used, the circuit will oscillate at about 34 kHz. If the PWM frequency is too low, the motor
will emit switching noise, and if it is too high, the power loss in the output will be excessive. A PWM frequency in
the range 15 to 50 kHz is desirable. To minimize the influence of the output on this circuit, the ground lead of this
capacitor should be connected as close as possible to the IC control system ground (the GND1 pin).

No. 7256 -12/14

LB11870

7. Hall Input Signals

Signals with an amplitude in excess of the hysteresis (42 mV maximum) must be provided as the Hall input signals.
However, an amplitude of over 100 mV is desirable to minimize the influence of noise. If the output waveforms are
disturbed (at phase switching) due to noise on the Hall inputs, insert capacitors across these inputs.

8. FG Input Signal

Normally, one phase of the Hall signals is input as the FG signal. If noise is a problem the input must be filtered with
either a capacitor or an RC filter circuit. Although it is also possible to remove FG signal noise by inserting a
capacitor between the FGFIL pin and ground, the IC may not be able to operate correctly if this signal is damped
excessively. If this capacitor is used, its value must be less than about 2200 pF. If the location of this capacitor's
ground lead is inappropriate, it may, inversely, make noise problems even more likely to occur. Thus the ground lead
location must be chosen carefully.

9. Rotor Constraint Protection Circuit

This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is
constrained. If the LD output is high (unlocked) for over a certain fixed period with the IC in the start state, the low
side transistor will be turned off. The time constant is determined by the capacitor connected to the CSD pin.

=. 120

C (µF)

If a 0.068 µF capacitor is used, the protection time will be about 8 seconds. The set time must be selected to have an
adequate margin with respect to the motor startup time. This protection circuit will not operate during deceleration
when the clock frequency is switched. To clear the rotor constraint protection state, the IC must be set to the stopped
state or the power must be turned off and reapplied.
Since the CSD pin also functions as the initial reset pulse generation pin at startup, the logic circuit will go to the
reset state and the IC will not be able to function if this pin is connected to ground. Therefore, both a 220 k

resistor

and a 4700 pF capacitor must be inserted between this pin and ground if the rotor constraint protection circuit is not
used.

10. Phase Lock Signal

(1) Phase lock range

Since this IC does not include a counter or similar functionality in the speed control system, the speed error range
in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the
changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the
motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in
states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at
startup and when unlocked due to switching clock frequencies.

(2) Masking function for the phase lock state signal

A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pull-
in. However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CLD pin and ground.

=. 0.9

C (µF)

When a 0.1 µF capacitor is used, the masking time will be about 90 ms. In cases where complete masking is required,
a masking time with fully adequate margin must be used. If no masking is required, leave the CLD pin open.

No. 7256 -13/14

LB11870

PS No. 7256 -14/14

LB11870

11. Power Supply Stabilization

Since this IC provides a large output current and adopts a switching drive technique, the power supply line level can
be disrupted easily. Thus capacitors large enough to stabilize the power supply voltage must be inserted between the
VCC pins and ground. The ground leads of these capacitors must be connected to the three pins that are the power
grounds, and they must be connected as close as possible to the pins themselves. If these capacitors (electrolytic
capacitors) cannot be connected close to their corresponding pins, ceramic capacitors of about 0.1 µF must be
connected near these pins.
If reverse torque control mode is selected for use during deceleration, since there are states where power is returned to
the power supply system, the power supply line levels will be particularly easily disrupted. Since the power line level
is most easily disrupted during lock pull-in at high motor speeds, this state needs extra attention; in particular,
capacitors that are adequately large to handle this situation must be selected.
If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected
with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must
be used.

12. VREG Stabilization

A capacitor of at least 0.1 µF must be used to stabilize the VREG voltage, which is the control circuit power supply.
The ground lead of that capacitor must be connected as close as possible to the IC control system ground (GND1).

13. Error Amplifier External Component Values

To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC
as possible. In particular, they must be located as far from the motor as possible.

14. FRAME Pin and the IC Metallic Rear Surface

The FRAME pin must be connected to the GND1 and GND2 pins, and the ground side of the electrolytic capacitor
must be connected to GND3. The IC's metallic rear surface is connected to the FRAME pin internally to the IC.
Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC
package to the PCB with, for example, a solder with good thermal conductivity.

This catalog provides information as of August, 2002. Specifications and information herein are subject to
change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

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