Ordering number : ENN7257A

91002AS (OT) No. 7257 -1/13

Overview

The LB11872H is a three-phase brushless motor driver
developed for driving the motors used for the polygonal
mirror in laser printers and similar applications. It can
implement, with a single IC chip, all the circuits required
for polygonal mirror drive, including speed control and
driver functions. The LB11872H can implement motor
drive within minimal drive noise due to its use of current
linear drive.

Functions and Features

· Three-phase bipolar current linear drive + midpoint

control circuit

· PLL speed control circuit
· Speed is controlled by an external clock signal.
· Supports Hall FG operation.
· Built-in output saturation prevention circuit
· Phase lock detection output (with masking function)
· Includes current limiter, thermal protection, rotor

constraint protection, and low-voltage protection circuits
on chip.

· On-chip output diodes.

Package Dimensions

unit: mm

3233A-HSOP28H

(6.2)

0.8

15.2

2.7

0.3

4.9

10.5

0.65

0.25

(0.8)

7.9

(2.25)

2.45max

0.1

2.0

SANYO: HSOP28H

[LB11872H]

LB11872H

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Three-Phase Brushless Motor Driver

for Polygonal Mirror Motors

Monolithic Digital IC

Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

max

Output current

max

500 ms

1.2

Allowable power dissipation 1

Pd max1

Independent IC

0.8

Allowable power dissipation 2

Pd max2

Mounted on a PCB (114.3

76.1

1.6 mm, glass epoxy)

2.0

Operating temperature

Topr

20 to +80

°C

Storage temperature

Tstg

55 to +150

°C

Specifications

Absolute Maximum Ratings

at Ta = 25°C

No. 7257 -2/13

LB11872H

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage range

10 to 28

6.3 V regulator-voltage output current

IREG

0 to 20

LD pin applied voltage

VLD

0 to 28

LD pin output current

ILD

0 to 15

FGS pin applied voltage

VFG

0 to 28

FGS pin output current

IFG

0 to 10

Allowable Operating Ranges

at Ta = 25°C

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

Supply current 1

Stop mode

Supply curren 2

Start mode

[Output Saturation Voltages VAGC = 3.5 V]

SOURCE (1)

VSAT1-1

= 0.5 A, RF = 0

1.7

2.2

SOURCE (2)

VSAT1-2

= 1.0 A, RF = 0

2.0

2.7

SINK (1)

VSAT2-1

= 0.5 A, RF = 0

0.4

0.9

SINK (2)

VSAT2-2

= 1.0 A, RF = 0

1.0

1.7

Output leakage current

(LEAK) V

= 28 V

100

µA

[6.3 V Regulator-Voltage Output]

Output voltage

VREG

5.90

6.25

6.60

Voltage regulation

VREG1

= 9.5 to 28 V

100

Load regulation

VREG2

Iload = 5 to 20 mA

Temperature coefficient

VREG3

Design target value

mV/°C

[Hall Amplifier Block]

Input bias current

IB (HA)

Differential input: 50 mVp-p

µA

Differential input voltage range

SIN wave input

600

mVp-p

Common-phase input voltage range

VICM

Differential input: 50 mVp-p

2.0

2.5

Input offset voltage

VIOH

Design target value

[FG Amplifier and Schmitt Block (IN1)]

Input amplifier gain

GFG

deg

Input hysteresis (high to low)

VSHL

Input hysteresis (low to high)

VSLH

Hysteresis width

VFGL

Input conversion

[Low-Voltage Protection Circuit]

Operating voltage

VSD

8.4

8.8

9.2

Hysteresis width

VSD

0.2

0.4

0.6

[Thermal Protection Circuit]

Thermal shutdown operating temperature

TSD

Design target value (junction temperature)

150

180

°C

Hysteresis width

TSD

Design target value (junction temperature)

°C

[Current Limiter Operation]

Acceleration limit voltage

VRF1

0.53

0.59

0.65

Deceleration limit voltage

VRF2

0.32

0.37

0.42

[Error Amplifier]

Input offset voltage

VIO (ER)

Design target value

Input bias current

IB (ER)

µA

High-level output voltage

(ER)

= 500 µA

VREG 1.2

VREG 0.9

Low-level output voltage

(ER)

= 500 µA

0.9

1.2

DC bias level

VB (ER)

1/2VREG

[Phase Comparator Output]

High-level output voltage

VPDH

= 100 µA

VREG 0.2

VREG 0.1

Low-level output voltage

VPDL

= 100 µA

0.2

0.3

Output source current

IPD+

VPD = VREG/2

500

µA

Output sink current

IPD

VPD = VREG/2

1.5

Electrical Characteristics

at Ta = 25°C, V

= VM = 24 V

Continued on next page.

Note

: Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input

amplitudes should be held to under 350 mVp-p.

No. 7257 -3/13

LB11872H

Continued from preceding page.

Parameter

Symbol

Conditions

Ratings

Unit

min

typ

max

[Lock Detection Output]

Output saturation voltage

VLD (SAT) ILD = 10 mA

0.15

0.5

Output leakage current

ILD (LEAK) VLD = 28 V

µA

[FG Output]

Output saturation voltage

VFG (SAT) IFG = 5 mA

0.15

0.5

Output leakage current

IFG (LEAK) VFG = 28 V

µA

[Drive Block]

Dead zone width

VDZ

With the phase is locked

100

300

Output idling voltage

VID

Forward gain 1

GDF+1

With phase locked

0.4

0.5

0.6

deg

Forward gain 2

GDF+2

With phase unlocked

0.8

1.0

1.2

deg

Reverse gain 1

GDF1

With phase locked

0.6

0.5

0.4

deg

Reverse gain 2

GDF2

With phase unlocked

0.8

1.0

1.2

deg

Acceleration command voltage

VSTA

5.0

5.6

Deceleration command voltage

VSTO

0.8

1.5

Forward limiter voltage

VL1

Rf = 22

0.53

0.59

0.65

Reverse limiter voltage

VL2

Rf = 22

0.32

0.37

0.42

[CSD Oscillator Circuit]

Oscillation frequency

OSC

C = 0.022 µF

High-level pin voltage

CSDH

4.3

4.8

5.3

Low-level pin voltage

CSDL

0.75

1.15

1.55

External capacitor charge and discharge current

CHG

µA

Lock detection delay count

CSDCT1

Clock cutoff protection operating count

CSDCT2

Lock protection count

CSDCT3

Initial reset voltage

RES

0.60

0.80

[Clock Input Block]

External input frequency

CLK

400

10000

High-level input voltage

(CLK) Design target value

2.0

VREG

Low-level input voltage

(CLK)

Design target value

1.0

Input open voltage

(CLK)

2.7

3.0

3.3

Hysteresis width

(CLK) Design target value

0.1

0.2

0.3

High-level input current

(CLK)

V (CLK) = VREG

140

185

µA

Low-level input current

(CLK)

V (CLK) = 0 V

185

140

µA

[S/S Pin]

High-level input voltage

(S/S)

2.0

VREG

Low-level input voltage

(S/S)

1.0

Input open voltage

(S/S)

2.7

3.0

3.3

Hysteresis width

(S/S)

0.1

0.2

0.3

High-level input current

(S/S)

V (S/S) = VREG

140

185

µA

Low-level input current

(S/S)

V (S/S) = 0 V

185

140

µA

Three-Phase Logic

OUT1 to OUT3 (H: Source, L: Sink)

For IN1 to IN3, "H" means that IN+ is greater than IN, and "L" means IN is greater than IN+.
For OUT1 to OUT3, "H" means the output is a source, and "L" means that it is a sink.

IN1

IN2

IN3

OUT1

OUT2

OUT3

No. 7257 -5/13

LB11872H

Pin Functions

Pin No.

Symbol

FRAME

GND

GND pin

NC (No connection) pin

2 to 7

IN1+ to IN3+

IN1 to IN3

Hall sensor input pins

These pins input the Hall effect sensor signal for each
phase.

The logic of these inputs is that the input is "high" when
VIN+ is greater than VIN.

AGC

Frequency characteristics correction pin

Insert a capacitor between pin 8 and ground.

Test pin

This pin must be left open.

CSD

Phase lock detection chattering prevention pin

Insert a capacitor between pin 12 and ground.

FG output pin

This is an open-collector output

S/S

Start/stop switching pin

Low: start mode

CLK

Clock signal input pin

Phase lock detection output pin

This pin goes to the on state when the phase is locked. It is
an open-collector output.

Phase comparator output pin

Error amplifier input pin

Error amplifier output pin

Frequency characteristics correction pin

Insert a capacitor between pin 21 and ground.

VREG

Stabilized power supply output pin

Insert a capacitor between pin 22 and ground.

Power supply pin

SUB

SUBGND pin

Connect this pin to ground.

Output current detection pin

Insert a resistor between pin 25 and ground.

26 to 28

OUT1 to 3

Output pins

No. 7257 -7/13

LB11872H

Pin Circuits and Functions

Pin No.

Function

Equivalent circuit

Hall effect sensor signal inputs

These inputs are high when IN+ is greater than IN- and
low when IN- is greater than IN+.

Insert capacitors between the IN+ and IN pins to
reduce noise.

An amplitude of over 50 mA p-p and under 350 mVp-p is
desirable for the Hall input signals.

Kickback can occur in the output waveform if the Hall
input amplitude is over 350 mVp-p.

IN2+

IN2

IN1+

IN1

IN3+

IN3

300

Vcc

AGC amplifier frequency characteristics correction.

Insert a capacitor (about 0.022 µF) between this pin and
ground.

AGC

300

VREG

Monitor pin
This pin should be left open in normal operation.

Used for both initial reset pulse generation and as the
reference time for constraint protection circuits.

Insert a capacitor between this pin and ground.

CSD

VREG

300

FG pulse output.

This is an open-collector output.

VREG

Start/stop control.

Low: Start 0 to 1.0 V

High: Stop 2.0 V to VREG

This pin goes to the high level when open.

S/S

VREG

33k

30k

Continued on next page.

No. 7257 -9/13

LB11872H

Continued from preceding page.

Pin No.

Function

Equivalent circuit

Control amplifier frequency correction.

Inserting a capacitor (about 5600 pF) between this pin
and ground will stop closed loop oscillation in the current
control system. The output current response
characteristics will be degraded if the capacitor is too
large.

VREG

Stabilized power supply (6.3 V)

Insert a capacitor (about 0.1 µF) between this pin and
ground for stabilization.

VREG

Vcc

Power supply

300

VREG

Vcc

SUB pin.

Connect this pin to ground.

SUB

Motor drive outputs.

If the output oscillates, insert a capacitor (about 0.1 µF)
between this pin and ground.

Output current detection.

Insert low-valued resistors (Rf) between these pins and
ground. The output current will be limited to the value
set by the equation I

OUT

= V

OUT1

OUT2

OUT3

No connection (NC) pins.

These pins may be used for wiring connections.

Ground

FRAME

GND

Overview of the LB11872H

1. Speed Control Circuit

This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter.
This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges
(low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed.
During this control operation, the FG servo frequency will be the same as the CLK frequency.

(servo) = f

CLK

2. Output Drive Circuit

To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint
control technique to prevent ASO destruction of the output transistors.
Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the
drive is cut and the motor is left in the free-running state.
Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1 µF) must be inserted
between the OUT pins and ground.

3. Hall Input Signals

This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input
amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the
individual phases, discrepancies in the output phase switching timing may occur.
An amplitude (differential) of at least 50 mVp-p is required in the Hall input signals. However, if the input amplitude
exceeds 350 mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output.
If Hall signal input frequencies in excess of 1 kHz (the frequency in a single Hall input phase) are used, internal IC
heating during startup and certain other times (that is, when the output transistors are saturated) may increase.
Reducing the number of magnetic poles can be effective in dealing with problem.
The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a
problem, a capacitor must be inserted across this input. However, since this could result in differences between the
signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases.
Although V

can be used as the Hall element bias power supply, using VREG can reduce the chances of problems

occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned
with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only
on the low side.

4. Power Saving Circuit

This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is
implemented by removing the bias current from most of the circuits in the IC. However, the 6.3 V regulator output is
provided in the power saving state.

5. Reference Clock

Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although
the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor.
This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the
formula below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode.

f (Hz)

=. 0.64 ÷ C

CSD

(µF): The capacitor inserted between the CSD pin and ground.

When a capacitor of 0.022 µF is used, the frequency will be about 29 Hz.

If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat
and then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will
not be restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied
before the rotor constraint protection time elapses.

No. 7257 -10/13

LB11872H

6. Rotor Constraint Protection Circuit

This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is
constrained physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the
IN1 signal) does not switch within a fixed time, output drive will be turned off. The time constant is determined by
the capacitor connected to the CSD pin.

=. 30.5

1.57

CSD

(µF)

If a 0.02 µF capacitor is used, the protection time will be about 1.05 seconds.
To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off
and reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection
circuit may not operate normally.

7. Phase Lock Signal

(1) Phase lock range

Since this IC does not include a counter or similar functionality in the speed control system, the speed error range
in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the
changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the
motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in
states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at
startup and when unlocked due to switching clock frequencies.

(2) Masking function for the phase lock state signal

A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pull-
in. However, this results in the lock state signal output being delayed by the masking time.
The masking time is determined by the capacitor inserted between the CSD pin and ground.

=. 6.5

1.57

CSD

(µF)

When a 0.022 µF capacitor is used, the masking time will be about 225 ms. In cases where complete masking is
required, a masking time with fully adequate margin must be used.

8. Initial Reset

To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero
until it reaches 0.63 V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good
approximation using the following formula.

=. 0.13

CSD

(µF)

A reset time of over 100 µs is required.

9. Current Limiter Circuit

The current limit value is determined by the resistor Rf inserted between the RF pin and ground.

LIM

= V

/Rf V

= 0.59 V (typical) (during acceleration) and 0.37 V (typical) (during deceleration)

10. Power Supply Stabilization

An adequately large capacitor must be inserted between the V

pin and ground for power supply stabilization. If

diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected
with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must
be used.
If high-frequency noise is a problem, a ceramic capacitor of about 0.1 µF must also be inserted in parallel.

No. 7257 -11/13

LB11872H

11. VREG Stabilization

A capacitor of at least 0.1 µF must be used to stabilize the VREG voltage, which is the control circuit power supply.
The capacitor must be connected as close as possible to the pins.

12. Error Amplifier External Component Values

To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC
as possible.

13. FRAME Pin and Heat sink Area

The FRAME pin and the heat sink area function as the control circuit ground terminal. It is desirable that this ground
line and the Rf resistor ground line be grounded at a single point at the ground for the electrolytic capacitor.
Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC
package to the PCB with, for example, a solder with good thermal conductivity.

14. CSD Pin

The capacitor connected to the CSD pin influences several operational aspects of this IC, including the rotor
constraint protection time and the phase lock signal mask time. The following are possible ways of determining the
value of this capacitor.
(1) If removing chattering from the phase lock state signal is most important:

Select a capacitance that can assure an adequate mask time.

(2) If startup time is more important than chattering:

Select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that
there are no problems with the clock cutoff protection circuit and initial reset time.
Operation of the rotor constraint protection circuit may hinder the study of motor characteristics in the
uncontrolled state. It is possible to only operate the initial reset function and not operate the rotor constraint
protection circuit by inserting a resistor (about 390 k

) in parallel with the capacitor between the CSD pin and

ground.

15. FC Pin

The capacitor connected to the FC pin is required for current limiter loop phase compensation. If the value is too low,
the output will oscillate. If the value is too large, it will be easier for currents in excess of the limit value to flow
during the current limit time (time before the circuit operates) in states where the output is saturated. (This is because
the control response characteristics become worse.)

16. AGC Pin

A capacitance that allows a certain amount of smoothing of the AGC pin voltage in the motor speed range used must
be selected for the capacitor connected to the AGC pin. It is also desirable to use a capacitance that allows the AGC
voltage to reach an essentially stabilized voltage before the initial reset is cleared. (If the capacitance is too large, the
rate of change of the AGC voltage will become slower.)

No. 7257 -12/13

LB11872H

PS No. 7257 -13/13

LB11872H

This catalog provides information as of September 2002. Specifications and information herein are
subject to change without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.

Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.

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