LB1928
No. 6198-1/11
LB1928
Package Dimensions
unit: mm
3147B-DIP28H
Overview
The LB1928 is a 3-phase brushless motor driver well suited
for drum and paper feed motors in laser printers, plain-paper
copiers and other office automation equipment. Direct PWM
drive allows control with low power losses. Peripheral
circuitry including speed control circuit and FG amplifier is
integrated, thus allows drive circuit to be constructed with a
single chip.
Functions and Features
Three-phase bipolar drive (30V, 3.1A)
Direct PWM drive technique
Built-in diode for absorbing output lower-side kickback
Speed discriminator and PLL speed control
Speed lock detection output
Built-in forward/reverse switching circuit
Built-in protection circuitry includes current limiter,
overheat protection, motor restraint protection, etc.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
D1099TH(KI)/73099RM(KI)
Ordering number : ENN6198A
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Monolithic Digital IC
Three-Phase Brushless Motor Driver
for Office Automation Equipment
[LB1928]
SANYO : DIP28H
Specifications
Absolute Maximum Ratings
at Ta = 25
C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
Vcc
max
30
V
Maximum output current
I
O
max
T
500 ms
3.1
A
Allowable power dissipation 1
Pd max 1
IC only
3
W
Allowable power dissipation 2
Pd max 2
With an arbitrary large heat sink
20
W
Operating temperature
Topr
20 to +80
C
Storage temperature
Tstg
55 to +150
C
Allowable Operating Ranges
at Ta = 25
C
Parameter
Symbol
Conditions
Ratings
Unit
Power supply voltage range 1
Vcc
9.5 to 28
V
Regulator voltage output current
I
REG
0 to 20
mA
LD output current
I
LD
0 to 15
mA
1
14
28
15
0.4
0.6
4.0
4.0
27.0
20.0
R1.7
8.4
1.93
1.78
1.0
12.7
11.2
LB1928
No. 6198-2/11
Electrical Characteristics
at Ta = 25C, Vcc = VM = 24V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Power supply current 1
Icc1
23
30
mA
Power supply current 2
Icc2
In STOP mode
3.5
5
mA
[Output block]
Output saturation voltage 1
Vosat1
Io = 1.0A, Vo(SINK) + Vo(SOURCE)
2.0
2.5
V
Output saturation voltage 2
Vosat2
Io = 2.0A, Vo(SINK) + Vo(SOURCE)
2.6
3.2
V
Output leak current
Ioleak
100
A
Lower-side diode forward voltage 1
V
D
1
I
D
= 1.0A
1.2
1.5
V
Lower-side diode forward voltage 2
V
D
2
I
D
= 2.0A
1.5
2.0
V
[5V regulator voltage output]
Output voltage
V
REG
Io = 5 mA
4.65
5.00
5.35
V
Voltage fluctuation
V
REG
1
Vcc = 9.5 to 28V
30
100
mV
Load fluctuation
V
REG
2
Io = 5 to 20 mA
20
100
mV
[Hall amplifier]
Input bias current
I
HB
2
0.5
A
Common mode input voltage range
V
ICM
1.5
V
REG
V
1.5
Hall input sensitivity
80
mVp-p
Hysteresis width
V
IN
15
24
42
mV
Input voltage L -> H
V
SLH
12
mV
Input voltage H-> L
V
SHL
12
mV
[PWM oscillator]
Output High level voltage
V
OH(PWM)
2.5
2.8
3.1
V
Output Low level voltage
V
OL(PWM)
1.2
1.5
1.8
V
Oscillator frequency
f
(PWM)
C = 3900 pF
18
kHz
Amplitude
V
(PWM)
1.05
1.30
1.55
Vp-p
[CSD circuit]
Operating voltage
V
OH(CSD)
3.6
3.9
4.2
V
External capacitance charge current
I
CHG
17
12
9
A
Operating time
t
(CSD)
C = 10
F Design target value
3.3
s
[Current limiter operation]
Limiter
V
RF
V
CC
-VM
0.45
0.5
0.55
V
[Thermal shutdown operation]
Thermal shutdown operating temperature
TSD
Design target value (junction temperature)
150
180
C
Hysteresis width
TSD
Design target value (junction temperature)
50
C
[FG amplifier]
Input offset voltage
V
IO(FG)
10
+10
mA
Input bias current
I
B(FG)
1
+1
A
Output High level voltage
V
OH(FG)
I
FGO
= 0.2 mA
V
REG
V
REG
V
1.2
0.8
Output Low level voltage
V
OL(FG)
I
FGO
= 0.2 mA
0.8
1.2
V
FG input sensitivity
Gain 100 times
3
mV
Next-stage Schmitt comparator width
Design target value
100
180
250
mV
Operating frequency range
2
kHz
Open-loop gain
f(FG) = 2 kHz
45
51
dB
[Speed discriminator]
Output High level voltage
V
OH(D)
I
DO
= 0.1 mA
V
REG
V
REG
V
1.0
0.7
Output Low level voltage
V
OL(D)
I
DO
= 0.1 mA
0.8
1.1
V
Count number
512
[PLL output]
Output High level voltage
V
OH(P)
I
PO
= 0.1 mA
V
REG
V
REG
V
REG
V
1.8
1.5
1.2
Output Low level voltage
V
OL(P)
I
PO
= 0.1 mA
1.2
1.5
1.8
V
[Lock detection]
Output Low level voltage
V
OL(LD)
I
LD
= 10 mA
0.15
0.5
V
Lock range
6.25
%
Continued on next page
LB1928
No. 6198-3/11
Continued from preceding page
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Integrator]
Input bias current
I
B(INT)
0.4
+0.4
A
Output High level voltage
V
OH(INT)
I
INTO
= 0.2 mA
V
REG
V
REG
V
1.2
0.8
Output Low level voltage
V
OL(INT)
I
INTO
= 0.2 mA
0.8
1.2
V
Open-loop gain
f(INT) = 1 kHz
45
51
dB
Gain bandwidth product
Design target value
450
kHz
Reference voltage
Design target value
5% V
REG
/2
5%
V
[Crystal oscillator]
Operating frequency range
fOSC
3
10
MHz
Low level pin voltage
V
OSCL
I
OSC
= 0.5 mA
1.65
V
High level pin current
I
OSCH
V
OSC
= V
OSCL
+ 0.3V
0.4
mA
[Start/stop pin]
High level input voltage range
V
IH(S/S)
3.5
V
REG
V
Low level input voltage range
V
IL(S/S)
0
1.5
V
Input open voltage
V
IO(S/S)
V
REG
V
REG
V
0.5
Hysteresis width
V
IN
0.35
0.50
0.65
V
High level input current
I
IH(S/S)
V
(S/S)
= V
REG
10
0
10
A
Low level input current
I
IL(S/S)
V
(S/S)
= 0V
280
210
A
[Forward/reverse pin]
High level input voltage range
V
IH(F/R)
3.5
V
REG
V
Low level input voltage range
V
IL(F/R)
0
1.5
V
Input open voltage
V
IO(F/R)
V
REG
V
REG
V
0.5
Hysteresis width
V
IN
0.35
0.50
0.65
V
High level input current
I
IH(F/R)
V
(F/R)
= V
REG
10
0
+10
A
Low level input current
I
IL(F/R)
V
(F/R)
= 0V
280
210
A
LB1928
No. 6198-4/11
Truth Table
Source
F/R = "L"
F/R = "H"
Sink
IN1
IN2
IN3
IN1
IN2
IN3
1
OUT2 -> OUT1
H
L
H
L
H
L
2
OUT3 -> OUT1
H
L
L
L
H
H
3
OUT3 -> OUT2
H
H
L
L
L
H
4
OUT1 -> OUT2
L
H
L
H
L
H
5
OUT1 -> OUT3
L
H
H
H
L
L
6
OUT2 -> OUT3
L
L
H
H
H
L
Pin Assignment
Relationship between crystal oscillator frequency fosc and FG frequency fFG is as follows.
fFG (servo) = fosc/ (ECL divide-by-16
count number)
= fosc/8192
20
0
20
40
60
80
100
120
Ambient temperature, Ta
C
0
4
3
8
12
16
20
24
With an arbitrary large heat sink
Without heat sink
Allowable power dissipation, Pd max - W
Pd max
Ta
27
26
28
24
23
25
21
20
22
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OUT1
F/R
IN3+ IN3 IN2+ IN2
OUT2 OUT3 GND2 VCC
VM
IN1+ IN1 GND1
S/S FGIN+ FGIN FGOUT LD
VREG PWM CSD
XI
XO INTOUT INTIN POUT DOUT
Top view
LB1928
LB1928
No. 6198-5/11
Equivalent Circuit Block Diagram
FG
RST
LOCK
DET
SPEED
D
I
S
CRI
ECL
1/16
Xtal
OS
C
CS
D
CIRCUIT
CURR
LIM
+
+
PLL
+
S/S
F/R
5VREG
LOGIC
HALL HYS
AMP
DRIVER
COMP
TS
D
PWM OSC
1/512
BGP
VREF
OUT1
OUT2
OUT3
VM
Rf
Vc
c
Vc
c
PW
M
CS
D
I
N
T
.
OUT
I
N
T
.IN
DOUT
P
OUT
LD
LD
FGOUT
FG
I
N
FG
I
N
+
FG A
M
P
GND1
XI
XO
S/S
F/R
VREG
I
N
1
I
N2
I
N
3
GND2
VREF
VREG
VREG
/2
INT AMP
LB1928
No. 6198-6/11
Pin number
28
1
2
3
5
4
6
7
8
9
10
Pin name
OUT1
OUT2
OUT3
GND2
VM
V
CC
VREG
PWM
CSD
XI
XO
Equivalent circuit
Pin Description
Pin function
Motor drive output pins.
Connect a Schottky diode between these
outputs and V
CC
.
Output ground pin.
Output block power supply and output
current detection pin.
Connect a resistor (Rf) between this pin and
V
CC
to detect the output current as a voltage.
The output current is limited according to the
equation I
OUT
= VRF/Rf.
Power supply pin (except for output block)
Regulated power supply output pin (5V
output)
Connect a capacitor (approx. 0.1
F) between
this pin and ground to stabilize the output.
PWM frequency setting pin.
Connect a capacitor between this pin and
ground.
C = 3900 pF results in a frequency of about
18 kHz.
Lock protection circuit operation time
setting pin.
Connecting a capacitor of about 10
F
between this pin and ground results in a
protection circuit operation time of about 3.3
seconds.
Quartz oscillator pins.
Connect to quartz oscillator to generate the
reference clock.
When an external clock (of several MHz) is
used, the clock signal should be input via a
resistor of about 5.1 k
connected in series
with the XI pin. In this case, the XO pin must
be left open.
Continued on next page
5
3
1
2
28
VCC
300
VM
A12983
6
VCC
A12984
7
200
2k
VREG
A12985
10
9
VREG
A12987
8
300
1k
VREG
A12986
LB1928
No. 6198-7/11
Pin number
11
12
13
14
15
Pin name
INT
OUT
INT
IN
POUT
DOUT
LD
Equivalent circuit
Pin function
Integrator output pin (speed control pin)
Integrator input pin.
PLL output pin.
Speed discriminator output pin.
Acceleration: High, Deceleration: Low
Speed lock detection pin.
When motor rotation is within lock range
(
6.25%): Low
Withstand voltage: 30V max.
Continued on next page
Continued from preceding page
11
VREG
PWM comparator
40k
A12988
12
300
VREG
A12989
13
300
VREG
A12990
14
300
VREG
A12991
15
VREG
A12992
LB1928
No. 6198-8/11
Pin number
16
17
18
19
20
22
21
24
23
26
25
27
Pin name
FG
OUT
FGIN
FGIN+
S/S
GND1
IN1+
IN1
IN2+
IN2
IN3+
IN3
F/R
Equivalent circuit
Pin function
FG amplifier output pin.
FG amplifier input pin.
By connecting a capacitor (approx. 0.1
F)
between FGIN+ and ground, the logic circuitry
is reset.
Start/stop control pin.
Start (Low): 0V to 1.5V
Stop (High): 3.5V to VREG
High when open.
Hysteresis width: approx. 0.5V.
Ground pin (except for output block).
Hall input pins.
High when IN+ > IN, Low when IN+ < IN.
Hall signal should have an amplitude of at least
100 mVpp (differential operation). When Hall
signal noise is a problem, connect a capacitor
between IN+ and IN.
Forward/reverse control pin.
Forward (Low): 0V to 1.5V
Reverse (High): 3.5V to VREG
High when open.
Hysteresis width: approx. 0.5V.
Continued from preceding page
16
VREG
FG schmitt comparator
40k
A12993
18
17
300
300
20k
20k
VREG
FG reset circuit
A12994
22k
19
2k
VREG
A12995
22
24
26
300
25
23
21
300
VREG
A12996
22k
27
2k
VREG
A12997
LB1928
No. 6198-9/11
Description of the LB1928
1.
Speed control circuit
The IC performs speed control through combined use of a speed discrimination circuit and PLL circuit. The speed
control circuit counts FG cycles and outputs a deviation signal every 2 FG cycles. The PLL circuit outputs a phase
deviation signal every FG cycle.
The FG servo frequency is determined by the following equation. The motor rotation speed is set by the number of
FG pulses and the crystal oscillator frequency.
fFG (servo) = fOSC/8192
fOSC: Crystal oscillator frequency
2.
Output drive circuit
In order to reduce power loss at the output, the LB1928 uses the PWM drive technique. While ON, the output
transistors are always saturated, and motor drive power is adjusted by varying the output ON duty ratio. Because
output PWM switching is performed by the lower-side output transistor, a Schottky diode must be connected
between OUT and V
CC
. (If the reverse recovery time of the diode is too long, a feedthrough current will flow at the
instant when the lower-side transistor goes ON.) An internal diode is provided between OUT and GND. If large
output current causes a problem (waveform distortion during lower-side kickback, etc.), an external rectifying diode
or Schottky diode should be connected.
The output diode is integrated only on the lower side.
3.
Current limiting circuit
The current limiting circuit limits the peak current to the value I = VRF/Rf (VRF = 0.5 V typ., Rf: current detector
resistance). Current limiting is achieved by reducing the ON duty ratio of the output, which reduces the current.
4.
Power save circuit
In order to reduce current drain in the STOP condition, the IC goes into power save mode. In this condition, bias
current to most circuits is cut off, but the 5V regulator output remains active.
5.
Reference clock
The reference clock for speed control can be input using one of the following two methods.
[1] Using a crystal oscillator
When a crystal is used for oscillation, connect the crystal, capacitors, and a resistor as shown in the figure
below.
C1, R1: For stable oscillation
C3: For crystal coupling
C2: For overtone oscillation prevention
R1
C1
VREG
XI
XO
C2
C3
LB1928
No. 6198-10/11
The circuit configuration and values are for reference only. The crystal oscillator's characteristics as well as the
possibility of floating capacitance and noise due to layout factors must be taken into consideration when
designing an actual application.
[Precautions for wiring layout design]
Since the crystal oscillator circuit operates at high frequencies, it is susceptible to the influence of floating
capacitance from the circuit board. Wiring should be kept as short as possible and traces should be kept
narrow.
When designing the external circuitry, pay special attention to the wiring layout between the oscillator and C3
(C2), to minimize the influence of floating capacitance.
[2] External clock input (equivalent to crystal oscillator, several MHz)
When using an external signal source instead of a crystal oscillator, the clock signal should be input from the
XO pin through a resistor of about 5.1 k
connected to the pin in series. The XO pin should be left open.
Signal input level
Low : 0 to 0.8V
High : 2.5 to 5.0V
6.
Speed lock range
The speed clock range is
6.25% of the rated speed. When the motor rotation is within the lock range, the LD pin
becomes Low (open collector output). When the motor rotation goes out of the lock range, the ON duty ratio of the
motor drive output is varied according to the amount of deviation to bring the rotation back into the lock range.
7.
PWM frequency
The PWM frequency is determined by the capacitance connected to the PWM pin.
f PWM
=
1/(14400
C)
The PWM frequency should be between 15 and 25 kHz.
8.
Hall input signal
The Hall input requires a signal with an amplitude of at least the hysteresis width (42 mV max.). Taking possible
noise influences into consideration, an amplitude of at least 100 mV is desirable.
9.
Forward/reverse switching
Forward/reverse switching of motor rotation is carried out with the F/R pin. If this is performed while the motor is
running, the following points must be observed:
Feedthrough current during switching is handled by proper circuit design. However, the V
CC
voltage rise
during switching (caused by momentary return of motor current to power supply) must not exceed the rated
voltage (30V). If problems occur, the capacitance between V
CC
and GND must be increased.
If the motor current after switching exceeds the current limiter value, the lower-side transistors go OFF but the
upper-side transistors go into the short brake state, which causes a current flow. The magnitude of the current
is determined by the motor counterelectromotive voltage and the coil resistance. This current may not exceed
the rated current (3.1A). (Forward/reverse switching at high speed therefore is not safe.)
(Reference values)
Oscillator frequency (MHz)
C1 (
F)
C2 (pF)
C3 (pF)
R1 (
)
3 to 5
0.1
10
47
330k
5 to 8
0.1
None
47
330k
8 to 10
0.1
None
22
330k
.
.
LB1928
No. 6198-11/11
10. Motor restraint protection circuit
To protect the IC and the motor itself when rotation is inhibited, a restraint protection circuit is provided. If the LD
output is High (unlocked) for a certain interval in the start condition, the lower-side transistors are turned off. The
length of the interval is determined by the capacitance at the CSD pin. A capacitance of 10
F results in a set
interval of about 3.3 seconds. (Tolerance approx.
30%)
Set interval (s)
=
0.33
C (
F)
If the capacitor arrangement is subject to leak current, possible adverse effects such as setting time tolerances must
be taken into consideration.
When the restraint protection circuit has been activated, the condition can only be canceled by setting the system to
the stop condition or by turning the power off and on again (in the stop condition). When wishing not to use the
restraint protection circuit, connect the CSD pin to ground.
If the stop time when releasing the restraint protection is short, the capacitor charge will not be fully dissipated.
This in turn will cause a shorter restraint protection activation time after the motor has been restarted. The stop time
should therefore be designed to be sufficiently long, using the equation shown below (also when restarting in the
motor start transient state).
Stop time (ms)
15
C (
F)
11. Power supply regulation
Because this IC has a high output current, power supply line fluctuations can occur easily. Therefore a capacitor of
sufficient capacitance must be connected between the V
CC
pin and ground to assure stable operation. If a diode is
used in the power line for reverse-connection protection, the likelihood of power line fluctuations increases further,
which will require more capacitance.
.
.
This catalog provides information as of December, 1999. Specifications and information herein are subject to change
without notice.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
I n t h e e v e n t t h a t a n y o r a l l S A N Y O p r o d u c t s ( i n c l u d i n g t e c h n i c a l d a t a , s e r v i c e s ) d e s c r i b e d o r
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be exported without obtaining the export license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
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