Overview
The LC372100PP, LC372100PM and LC372100PT are
262,144-word
8-bit organization (2,097,152-bit) mask
programmable read only memories.
The LC372100PP-10, LC372100PM-10 and
LC372100PT-10 feature an access time of 100 ns, an OE
access time of 40 ns, and a standby current of 30 A, and
are optimal for use in 5-V systems that require high-speed
access.
The LC372100PP-20LV, LC372100PM-20LV and
LC372100PT-20LV feature an access time of 200 ns, an
OE access time of 80 ns, and a standby current of 4 A,
and thus are optimal for use in 3-V systems that use
batteries. Additionally, they provide high-speed access in
3.3-V systems (3.0 to 3.6 V) with a 150-ns access time
and a 60-ns OE access time.
These ROMs adopt the JEDEC standard pin assignment
which allows them to replace EPROM easily. To prevent
bus line collisions in multi-bus microcontroller systems,
pin 24 can be mask programmed to be either active high or
active low.
Features
262144 words
8 bits organization
Power supply
LC372100PP, PM, PT-10:
5.0 V 10%
LC372100PP, PM, PT-20LV: 2.7 to 3.6 V
Fast access time (t
AA
, t
CA
)
LC372100PP, PM, PT-10:
100 ns (max.)
LC372100PP, PM, PT-20LV: 200 ns (max.)
150 ns
(V
CC
= 3.0 to 3.6 V)
Operating current
LC372100PP, PM, PT-10:
70 mA (max.)
LC372100PP, PM, PT-20LV: 20 mA (max.)
Standby current
LC372100PP, PM, PT-10:
30 A (max.)
LC372100PP, PM, PT-20LV: 5 A (max.)
Full static operation (internal clocked type)
Fully TTL compatible (5 V supply)
3 state outputs
JEDEC standard pin configuration
Package type
LC372100PP-10/20LV:
DIP32 (600 mil)
LC372100PM-10/20LV: SOP32 (525 mil)
LC372100PT-10/20LV: TSOP32 (8 mm
20 mm)
Package Dimensions
unit: mm
3192-DIP32
unit: mm
3205-SOP32
unit: mm
3224-TSOP32
CMOS IC
53098HA (OT)/51195TH (OT)/41095TH (OT) No. 5088-1/5
Preliminary
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
2 MEG (262144 words
8 bits) Mask ROM
Internal Clocked Silicon Gate
LC372100PP, PM, PT-10/20LV
Ordering number : EN
*
5088C
SANYO: DIP32
[LC372100PP]
SANYO: TSOP32 (type-I)
[LC372100PT]
SANYO: SOP32
[LC372100PM]
No. 5088-2/5
LC372100PP, PM, PT-10/20LV
Pin Assignments
Block Diagram
Truth Table
X: H or L level should be offered.
Pin Functions
A0 to A17
Address input
D0 to D7
Data output
CE/CE
Chip enable input
OE/OE
Output enable input
V
CC
Power supply
V
SS
Ground
CE/CE
OE/OE
Output
Current drain
L/H
X
High-impedance
Standby mode
H/L
L/H
High-impedance
Operating mode
H/L
H/L
DOUT
Operating mode
No. 5088-3/5
LC372100PP, PM, PT-10/20LV
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
CC
max
0.3 to +7.0
V
Supply input voltage
V
IN
0.3
*
2
to V
CC
+ 0.3
V
Supply output voltage
V
OUT
0.3 to V
CC
+ 0.3
V
Allowable power dissipation
Pd max
Ta = 25C; Reference values for the SANYO DIP package
1.0
W
Operating temperature
Topr
0 to +70
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
*
1
Note: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to Recommended
Operating Conditions.
2. V
IN
(min) = 3.0 V (pulse width
30 ns)
Note: 1. t
OD
is measured from the earlier edge of the CE (CE) or OE(OE)'s going high impedance.
This parameter is periodically sampled and not 100% tested.
2. Guaranteed at V
CC
= 3.0 to 3.6 V
Note:
*
This parameter is periodically sampled and not 100% tested.
Note:
*
Guaranteed at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input capacitance
C
IN
V
IN
= 0 V; Reference values for the SANYO DIP package
8
pF
Output capacitance
C
OUT
V
OUT
=
0 V; Reference values for the SANYO DIP package
10
pF
Input/Output Capacitance
* at Ta = 25C, f = 1.0 MHz
3 V Operation
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
CC
max
2.7
3.0
3.6
V
Input high level voltage
V
IH
0.8 V
CC
V
CC
+ 0.3
V
Input low level voltage
V
IL
0.3
+0.4
V
DC Recommended Operating Ranges
at Ta = 0 to +70C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Operating supply current
I
CCA1
CE = 0.2 V (CE = V
CC
0.2 V), V
I
= V
CC
0.2 V/0.2 V
15
mA
I
CCA2
CE = V
IL
(CE = V
IH
), I
O
= 0 mA, V
I
= V
IH
/V
IL
, f = 5 MHz
20
mA
Standby supply current
I
CCS1
CE = V
CC
0.2 V (CE = 0.2 V)
5 (0.5
*
)
A
I
CCS2
CE = V
IH
(CE = V
IL
)
50 (10
*
)
A
Input leakage current
I
LI
V
IN
= 0 to V
CC
1.0
A
Output leakage current
I
LO
CE or OE = V
IH
(CE or OE = V
IL
), V
OUT
= 0 to V
CC
1.0
A
Output high level voltage
V
OH
I
OH
= 0.5 mA
V
CC
0.2
V
Output low level voltage
V
OL
I
OL
= 0.5 mA
0.2
V
DC Electrical Characteristics
at Ta = 0 to +70C, V
CC
= 2.7 to 3.6 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Cycle time
t
CYC
200 (150
*
2
)
ns
Address access time
t
AA
200 (150
*
2
)
ns
CE access time
t
CA
200 (150
*
2
)
ns
OE access time
t
OA
80 (60
*
2
)
ns
Output hold time
t
OH
25
ns
Output disable time
*
1
t
OD
*
1
50
ns
AC Characteristics
at Ta = 0 to +70C, V
CC
= 2.7 to 3.6 V
No. 5088-4/5
LC372100PP, PM, PT-10/20LV
5 V Operation
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
CC
max
4.5
5.0
5.5
V
Input high level voltage
V
IH
2.2
V
CC
+ 0.3
V
Input low level voltage
V
IL
0.3
+0.6
V
DC Recommended Operating Ranges
at Ta = 0 to +70C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Operating supply current
I
CCA1
CE = 0.2 V (CE = V
CC
0.2 V), V
I
= V
CC
0.2 V/0.2 V
30
mA
I
CCA2
CE = V
IL
(CE = V
IH
), I
O
= 0 mA, V
I
= V
IH
/V
IL
, f = 10 MHz
70
mA
Standby supply current
I
CCS1
CE = V
CC
0.2 V (CE = 0.2 V)
30 (1.0
*
)
A
I
CCS2
CE = V
IH
(CE = V
IL
)
1.0 (300
*
)
mA (A)
Input leakage current
I
LI
V
IN
= 0 to V
CC
1.0
A
Output leakage current
I
LO
CE or OE = V
IH
(CE or OE = V
IL
), V
OUT
= 0 to V
CC
1.0
A
Output high level voltage
V
OH
I
OH
= 1.0 mA
2.4
V
Output low level voltage
V
OL
I
OL
= 2.0 mA
0.4
V
DC Electrical Characteristics
at Ta = 0 to +70C, V
CC
= 5.0 V 10%
Note:
*
Guaranteed at Ta = 25C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Cycle time
t
CYC
100
ns
Address access time
t
AA
100
ns
CE access time
t
CA
100
ns
OE access time
t
OA
40
ns
Output hold time
t
OH
20
ns
Output disable time
*
t
OD
30
ns
AC Characteristics
at Ta = 0 to +70C, V
CC
= 5.0 V 10%
AC Test Conditions
Output Load (5 V measurement)
Note:
*
t
OD
is measured from the earlier edge of the CE (CE) or OE(OE)'s going high impedance.
This parameter is periodically sampled and not 100% tested.
Input pulse levels
0.4 V to 0.8 V
CC
(3 V measurement),
0.4 V to 2.8 V (5 V measurement)
Input rise/fall time
5 ns
Input timing level
1.5 V
Output timing level
1.5 V
Output load
70 pF (3 V measurement)
See figure (5 V measurement)
PS No. 5088-5/5
LC372100PP, PM, PT-10/20LV
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
s
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
s
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
s
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Timing Chart
System Design Notes
These LSIs adopt an internal synchronization technique in which operation is started by detecting changes in either the
CE input or the address inputs. As a result, the output data immediately after power on is invalid. Once power has been
applied, valid data is output after the application changes the value of either the CE input or at least one of the address
inputs.
Another point due to the use of the ATD technique is that these LSIs are extremely sensitive to input noise. Applications
must take precautions to provide stable input signals, both for the CE input and the address inputs, to prevent incorrect
operation.
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