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Электронный компонент: LC4608C

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Overview
The LC4608C is a driver for ink-jet printer heads with 64-
bit output. It converts 4-bit parallel input into 16-step gray
scale output by regulating the transmission gate's output
time.
Features
This 64-bit CMOS driver with 16-step gray scale output
and high withstand voltage offers the following features.
Built-in 64
4-bit static shift register
Built-in 64
4-bit static latch
16-step gray scale output from 4-bit parallel input
Built-in 64
2-channel transmission gate output
Transmission gate on resistance of 60
(typ.) 100
(max)
CMOS process with high withstand voltage (42 V)
CMOS IC
33198RM (OT) No. 5782-1/11
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Printer Head Driver
LC4608C
Ordering number : EN5782
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage (logic)
V
DD
0.5 to +7.0
V
Supply voltage (high withstand voltage circuits)
V
H
0.5 to +42
V
Driver output breakdown voltage
BV
DO
0.5 to +42
V
Driver output current
I
DO
Peak value within allowable operating range
400
mA
Input current
I
IN
20 to +20
mA
Input voltage (logic)
V
IN
1
0.5 to V
DD
+0.5
V
Input voltage (COM, output)
V
IN
2
0.5 to V
H
+0.5
V
Operating temperature
Topr
10 to +90
C
Storage temperature
Tstg
65 to +150
C
Junction temperature
Tj
10 to +125
C
Specifications
Maximum Ratings
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
4.5
5.0
5.5
V
V
H
*
1
24.0
40.0
V
Input voltage
V
IN
0
V
DD
V
COM
0
V
H
V
Output current DOn
I
DO
V
H
= 40 V
*
2
200
400
mA
Clock frequency
f
clk
8.0
MHz
Data setup time
t
ds
40
ns
Data hold time
t
dh
40
ns
Latch setup time
t
Ls
140
ns
Clock pulse width
t
wCLK
50
ns
Latch pulse width
t
wLAT
80
ns
Allowable Operating Ranges
at V
DD
= 5.0 V10%, Topr = 10 to +90C unless otherwise specified
Continued on next page.
No. 5782-2/11
LC4608C
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
STBCLK frequency
f
STB
1.0
MHz
CLK
LOAD setup time
t
SL
80
ns
LOAD
CLK hold time
t
HL
80
ns
LOAD pulse width
t
WL
80
ns
STBCLK
LOAD setup time
t
STBL
80
ns
LOAD
STBCLK hold time
t
LSTB
80
ns
Clock rising edge time
t
r
35
ns
Clock falling edge time
t
f
35
ns
Latch rising edge time
t
lr
70
ns
Latch falling edge time
t
lf
70
ns
Operating temperature
Tjopr
1.0
+90
C
Continued from preceding page.
Note : 1. The figures for normal operation are a load capacitance Cpzt of 1 nF, a power supply voltage V
H
of 30 V, and a max input level COMmax of 25 V.
2. Value for V
H
= 40 V, COMmax = 40 V, frequency = 35 kHz, and duty factor = 1/100.
Note : 1. The sign is negative for incoming current and positive for outgoing current.
2. I
IH
1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB3. I
IH
applies to the following input pins: STB4
and STB5.
3. I
IL
1 applies to the following input pins: SI0 to SI3, CLK, LAT, LOAD, STBCLK, and STB1 to STB5.
Note : 5. The figures are for a load capacitance Cpzt of 1 nF and a power supply voltage V
H
of 30 V as measured with R
L
= 3 k
and COMn = 25 V DC.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input high-level voltage
V
IH
V
DD
0.7
V
DD
+0.3
V
Input low-level voltage
V
IL
0.3
V
DD
0.3
V
Input high-level current
*
2
I
IH
1
V
DD
= 5.0 V, V
IH
= 5.0 V
0
0.5
A
I
IH
2
V
DD
= 5.0 V, V
IH
= 5.0 V
0
50
100
A
Input low-level current
*
3
I
IL
V
DD
= 5.0 V
0
0.5
A
Output high- level voltage
V
OH
I
O
= 400 A
V
DD
0.5
V
Output low-level voltage
V
OL
I
O
= 400 A
0.5
V
Output high-level current transmission gate
V
OHT
V
DD
= 5.0 V, V
H
= 40 V, COMn = 40 V,
39
39.4
V
voltage
I
OHT
= 10 mA
Output low-level current transmission gate
V
OLT
V
DD
= 5.0 V, V
H
= 40 V, COMn = 40 V,
0.6
1.0
V
voltage
I
OHT
= 10 mA
Transmission gate on resistance
R
ON
V
H
= 40 V, V
DS
= 3 V
60
100
Within chip
Transmission gate on resistance variation
Rx
15
+15
Current drain
I
DD
1
V
DD
GND, fclk = 3.5 MHz, f
Sln
= 1.75 MHz
15
+15
Leakage current between pins
INL
Leakage current between pins
0
10
A
Output leakage current
I
LEAK
V
DD
= 5.0 V, V
H
= 42 V
0
100
A
Electrical Characteristics
DC Characteristics
at V
DD
= 5.0 V10%, Tjopr = 10 to +90C unless otherwise specified
2 (MAX MIN)
100
--------------------
MAX + MIN
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
SOn output rising edge time
t
or
C
L
= 10 pF
50
ns
SOn input rising edge time
t
of
C
L
= 10 pF
50
ns
STBn
DOn propagation delay time
t
dor
*
5
1.0
s
t
dof
*
5
1.0
s
CLK
SOn propagation delay time
t
sor
C
L
= 10 pF
140
ns
t
sof
C
L
= 10 pF
140
ns
Switching Characteristics
at V
DD
= 5.0 V10%, Tjopr = 10 to +90C unless otherwise specified
Timing Chart 1
No. 5782-3/11
LC4608C
Timing Chart 2
Timing Chart 3
No. 5782-4/11
LC4608C
Usage Note
The power on and power off sequences must use the following orders.
Power on sequence: V
DD
5-V input circuits
V
H
COMn
Power off sequence: COMn
V
H
5-V input circuits
V
DD
Block Diagram
Timing Chart 4
Level shift circuit
Gray scale
control logic
4-bit
counter
4-bit latche
64
4-bit shift register
64
Pad Layout Diagram
No. 5782-5/11
LC4608C
Output pad
PP
140 m
dimensions WSM, LSM
116 m
WM, LM
106 m
WSC, LSC
96 m
WJP, LJ
90 m
Input pad
PP (min)
200 m
dimensions WSM, LSM
116 m
WM, LM
106 m
WSC, LSC
96 m
WJP, LJ
90 m
Chip size
2.67 mm
9.48 mm