Overview
The LC72191, LC72191M and LC72191JM are PLL
frequency synthesizers for electronic tuning. The
LC72191, LC72191M and LC72191JM are optimal for
AM/FM tuner circuits that require high mounting
densities.
Features
Designed for use in car stereos, the LC72191 provides a
rich set of reference frequencies, I/O ports, a general-
purpose counter, and an unlock detection circuit.
Functions
Programmable dividers
-- FMIN pin: 130 MHz at 70 mVrms and 160 MHz at
100 mVrms input (built-in prescaler)
-- AMIN pin: Pulse swallower and direct division
techniques
Reference frequencies: Ten selectable frequencies:
1, 5, 9, 10, 3.125, 6.25, 12.5 25, 50 and 100 kHz
Output ports: 7 pins
Complementary outputs: 2 pins
N-channel open drain outputs: 5 pins
Input ports: 2 pins
General-purpose counter: For measuring IF and other
signals (Also used for station detection when
functioning as an IF counter.)
-- HCTR pin: Frequency measurement (for inputs up to
70 MHz)
-- LCTR pin: Frequency and period measurement
PLL unlock detection circuit
Detects phase differences of 0.55, 1.11, 2.22 and 3.33 s.
Controller clock output: 400 kHz
Clock time base output: 8 Hz
Serial data I/O
-- Supports CCB format communication with the
system controller.
Package: LC72191: DIP24S
LC72191M: MFP24
LC72191JM: MFP24S
Package Dimensions
unit: mm
3067-DIP24S
CMOS LSI
Ordering number : EN 3985C
D3096HA (OT)/D2593JN/6182JN No. 3985-1/16
SANYO: DIP24S
[LC72191]
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
PLL Frequency Synthesizer
for Electronic Tuning in Car Stereo Tuners
LC72191, 72191M, 72191JM
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
Pin Symbols
XIN, XOUT:
Crystal oscillator (7.2 MHz)
FMIN, AMIN:
Local oscillator signal input
CE, CL, DI, DO: Serial data I/O
OUT0 to OUT6: Output ports
IN0, IN1:
Input ports
HCTR, LCTR:
General-purpose counter inputs
PD1, PD2:
Charge pump outputs
SYC:
Control clock (400 kHz)
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
No. 3985-3/16
LC72191, 72191M, 72191JM
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
0.3 to +7.0
V
Input voltage
V
IN
(1)
CE, CL, DI, IN0, IN1
0.3 to +7.0
V
V
IN
(2)
Input pins other than V
IN
(1)
0.3 to V
DD
+ 0.3
V
V
OUT
(1)
DO, SYC
0.3 to +7.0
V
Output voltage
V
OUT
(2)
OUT1, OUT2
0.3 to V
DD
+ 0.3
V
V
OUT
(3)
OUT3 to OUT6, OUT0
0.3 to +15
V
V
OUT
(4)
Output pins other than V
OUT
(1), V
OUT
(2) and V
OUT
(3)
0.3 to V
DD
+ 0.3
V
Ta
85C
:LC72191
350
Allowable power dissipation
Pd max
:LC72191M
300
mW
:LC72191JM
200
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Block Diagram
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
= 0 V
Note: 1.
DV and SP are bits in the serial data.
*
: don't care
2. Frequency measurement
3. Frequency measurement
4. Period measurement
5. f
IN
(2): 10 to 160 MHz/V
IN
(2)
0.100 Vrms (minimum)
6. f
IN
(4): 10 to 70 MHz/V
IN
(4)
0.100 Vrms (minimum)
No. 3985-4/16
LC72191, 72191M, 72191JM
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
(1)
V
DD
4.5
6.5
V
V
DD
(2)
V
DD
: Crystal oscillator guaranteed operation
3.5
6.5
V
Input high level voltage
V
IH
(1)
CE, CL, DI, IN0, IN1
2.2
6.5
V
V
IH
(2)
LCTR: Pulse waveform, DC coupling
*
4
0.7 V
DD
(1)
V
DD
(1)
V
Input low level voltage
V
IL
(1)
CE, CL, DI, IN0, IN1
0
0.7
V
V
IL
(2)
LCTR
*
4
0
0.3 V
DD
(1)
V
Output voltage
V
OUT
(1)
DO, SYC
6.5
V
V
OUT
(2)
OUT3 to OUT6, OUT0
13
V
f
IN
(1)
XIN: Sine wave capacitor coupling, V
DD
(2)
1.0
7.2
8.0
MHz
f
IN
(2)
FMIN: Sine wave capacitor coupling, V
DD
(1)
*
1
10
130 (160)
*
5
MHz
Input frequency
f
IN
(3)
AMIN: Sine wave capacitor coupling, V
DD
(1)
*
1
0.5
40
MHz
f
IN
(4)
HCTR: Sine wave capacitor coupling, V
DD
(1)
*
2
10
60 (70)
*
6
MHz
f
IN
(5)
LCTR: Sine wave capacitor coupling, V
DD
(1)
*
3
15
500
kHz
f
IN
(6)
LCTR: Pulse wave DC coupling, V
DD
(1)
*
4
1.0
20
10
3
Hz
Crystal oscillators for which
Xtal
X
IN
, X
OUT
: CI
50
3.0
7.2
8.0
MHz
operation is guaranteed
V
IN
(1)
X
IN
: Sine wave capacitor coupling, V
DD
(1)
0.5
1.5
Vrms
V
IN
(2)
FMIN: Sine wave capacitor coupling, V
DD
(1)
0.070
1.5
Vrms
(0.100)
*
5
Input amplitude
V
IN
(3)
AMIN: Sine wave capacitor coupling, V
DD
(1)
0.070
1.5
Vrms
V
IN
(4)
HCTR: Sine wave capacitor coupling, V
DD
(1)
*
2
0.070
1.5
Vrms
(0.100)
*
6
V
IN
(5)
LCTR: Sine wave capacitor coupling, V
DD
(1)
*
3
0.070
1.5
Vrms
DV
SP
Input frequency
1/2 divider
1/16, 17 swallow
12-bit main divider
Input pin
1
*
10 to 130 (160) MHz
q
q
q
q
q
q
FMIN
0
1
2 to 40 MHz
--
q
q
q
q
AMIN
0
0
0.5 to 10 MHz
--
--
q
q
AMIN
Electrical Characteristics
for the Allowable Operating Ranges
Note: A capacitor of at least 2000 pF must be inserted between the power supply V
DD
and V
SS
potentials.
No. 3985-5/16
LC72191, 72191M, 72191JM
Parameter
Symbol
Conditions
min
typ
max
Unit
Rf (1)
XIN
1.0
M
Rf (2)
FMIN
500
k
Internal feedback resistance
Rf (3)
AMIN
500
k
Rf (4)
HCTR
500
k
Rf (5)
LCTR
500
k
Hysteresis
V
H
LCTR
0.1 V
DD
0.6 V
DD
V
I
IH
(1)
CE, CL, DI: V
I
= 6.5 V
5.0
A
I
IH
(2)
IN0, IN1: V
I
= V
DD
5.0
A
Input high level current
I
IH
(3)
XIN: V
I
= V
DD
20
A
I
IH
(4)
FMIN, AMIN: V
I
= V
DD
40
A
I
IH
(5)
HCTR, LCTR: V
I
= V
DD
40
A
I
IL
(1)
CE, CL, DI: V
I
= V
SS
5.0
A
I
IL
(2)
IN0, IN1: V
I
= V
SS
5.0
A
Input low level current
I
IL
(3)
XIN: V
I
= V
SS
20
A
I
IL
(4)
FMIN, AMIN: V
I
= V
SS
40
A
I
IL
(5)
HCTR, LCTR: V
I
= V
SS
40
A
Output high level voltage
V
OH
(1)
OUT1, OUT2: I
O
= 1 mA
V
DD
1.0
V
V
OH
(2)
PD1, PD2: I
O
= 0.5 mA
V
DD
1.0
V
V
OL
(1)
OUT1, OUT2: I
O
= 1 mA
1.0
V
V
OL
(2)
PD1, PD2: I
O
= 0.5 mA
1.0
V
Output low level voltage
V
OL
(3)
OUT3 to OUT6: I
O
= 5 mA
1.0
V
V
OL
(4)
OUT0: I
O
= 1 mA
1.0
V
V
OL
(5)
DO: I
O
= 5 mA
1.0
V
V
OL
(6)
SYC: I
O
= 0.5 mA (V
DD
= 3.5 to 6.5 V)
1.0
V
I
OFF
(1)
OUT3 to OUT6, OUT0: V
O
= 13 V
5.0
A
Output off leakage current
I
OFF
(2)
DO: V
O
= 6.5 V
5.0
A
I
OFF
(3)
SYC: V
O
= 6.5 V (V
DD
= 3.5 to 6.5 V)
5.0
A
Three-state high level
I
OFFH
PD1, PD2: V
O
= V
DD
0.01
10.0
nA
off leakage current
Three-state low level
I
OFFL
PD1, PD2: V
O
= V
SS
0.01
10.0
nA
off leakage current
Input capacitance
C
IN
FMIN, HCTR
1
2
3
pF
V
DD
: f
IN
(2) = 130 MHz, V
IN
(2) = 70 mVrms,
I
DD
(1)
with a 7.2 MHz crystal, other input pins at V
SS
,
20
30
mA
Current drain
output pins open
V
DD
: PLL block stopped (PLL inhibit state), crystal
I
DD
(2)
oscillator operating (SYC, TB), with a 7.2 MHz crystal,
1.0
mA
other input pins at V
SS
, output pins open
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