Ordering number : ENN6167
12100RM (OT) No. 6167-1/29
Overview
The LC72711W and LC72711LW are data demodulator
ICs for receiving FM multiplex broadcasts for mobile
reception in the DARC format. This IC includes an on-
chip bandpass filter for extracting the DARC signal from
the FM baseband signal. Furthermore, since this IC
supports all of the IT-R recommended FM multiplex
frame structures (methods A, A', B, and C), it is optimal
for worldwide market radios that provide FM multiplex
reception. The LC72711W and LC72711LW support both
parallel and CCB serial CPU interfaces.
Functions
Adjustment-free 76 kHz SCF bandpass filter
Supports all FM multiplex frame structures (methods A,
A', B, and C) under CPU control.
MSK delay detection system based on a 1T delay.
Error correction function based on a 2T delay (in the
MSK detection stage)
Digital PLL based clock regeneration function
Shift-register 1T and 2T delay circuits
Block and frame synchronization detection circuits
Functions for setting the number of allowable BIC errors
and the number of synchronization protection
operations.
Error correction using (272, 190) codes
Built-in layer 4 CRC code checking circuit
On-chip frame memory and memory control circuit for
vertical correction
7.2 MHz crystal oscillator circuit
Two power saving modes: STNBY and EC_STOP
Applications can use either a parallel CPU interface
(DMA) or a CCB serial interface.
Supply voltage: 4.5 to 5.5 V (LC72711W), 2.7 to 3.6 V
(LC72711LW)
Package Dimensions
unit: mm
3190-SQFP64
10.0
12.0
1.25
0.5
1.25
1.25
0.5
1.25
0.18
12.0
1
16
17
32
33
48
49
64
10.0
0.5
1.7max
0.5
0.1
0.15
SANYO: SQFP64
[LC72711W, 72711LW]
LC72711W, 72711LW
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Mobile FM Multiplex Broadcast (DARC)
Receiver IC
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
No. 6167-2/29
LC72711W, 72711LW
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
(0.3 to +5.5) 0.3 to +7.0
V
Input voltage
V
IN
(1)
A0/CL, A1/CE, A2/DI, RST, STNBY
0.3 to +7.0
V
V
IN
(2)
Pins other than V
IN
(1)
0.3 to V
DD
+ 0.3
V
Output voltage
V
OUT
(1)
DO
0.3 to +7.0
V
V
OUT
(2)
Pins other than V
OUT
(1)
0.3 to V
DD
+ 0.3
V
Output current
I
OUT
(1)
INT, RDY, DREQ, and D0 to D15
0 to 4.0
mA
I
OUT
(2)
Pins other than I
OUT
(1)
0 to 2.0
mA
Allowable output current (total)
I
TTL
Total for all the output pins
20
mA
Allowable power dissipation
Pdmax
Ta
+85C
200
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = +25C, V
SS
= 0 V. Items in parentheses refer to the LC72711LW.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
4.5
5.5
V
High-level input voltage
V
IH
1
A0/CL, A1/CE, A2/DI, RST, STNBY
0.7 V
DD
5.5
V
V
IH
2
DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2
0.7 V
DD
V
DD
V
Low-level input voltage
V
IL
1
Pins for which V
IH
1 applies
V
SS
0.3 V
DD
V
V
IL
2
Pins for which V
IH
2 applies
V
SS
0.3 V
DD
V
Oscillator frequency
FOSC
This IC operates with a frequency precision of 250 ppm
7.2
MHz
X
IN
input sensitivity
VXI
With a sine wave input to X
IN
, capacitor coupling,
400
1500
mVrms
V
DD
= +4.5 to +5.5 V
Input amplitude
VMPX
With a 100% modulated composite signal input to
150
400
mVrms
MP
XIN
, V
DD
= +4.5 to +5.5 V
Clock low-level period
t
CL
A0/CL
0.7
s
Clock high-level period
t
CH
A0/CL
0.7
s
Data setup time
t
SU
A0/CL, A2/DI
0.7
s
Data hold time
t
HD
A0/CL, A2/DI
0.7
s
CE wait time
t
EL
A0/CL, A1/CE
0.7
s
CE setup time
t
ES
A0/CL, A1/CE
0.7
s
CE hold time
t
EH
A0/CL, A1/CE
0.7
s
Data latch change time
t
LC
A1/CE
0.7
s
Data output time
t
DDO
DO, A0/CL
277
555
ns
CRC4 change time
t
CRC
CRC4, A0/CL
0.7
s
[LC72711W]
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
= 0 V
Serial I/O
No. 6167-3/29
LC72711W, 72711LW
[LC72711W]
Allowable Operating Ranges: Parallel Interface
at Ta = 40 to +85C, V
SS
= 0 V
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the "RD low-level width" and the "Corrected output RD width" values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 250 ns (minimum).
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Address to RD setup
t
SARD
A0/CL, A1/CE, A2/DI, A3, RD
20
ns
RD to address hold
t
HARD
A0/CL, A1/CE, A2/DI, A3, RD, t
WRDL
250 ns
20
ns
RD low-level width
t
WRDL
1
RD
250
ns
RD low-level width (when RDY is used)
t
WRDL
2
RD
100
250
ns
RD cycle wait
t
CYRD
A0/CL, A1/CE, A2/DI, A3, RD
150
ns
RDY width (Register read)
t
WRDY
RDY
60
210
ns
RD data hold
t
RDH
RD, DATn
0
ns
Address to WR setup
t
SAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR to address hold
t
HAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR cycle wait
t
CYWR
A0/CL, A1/CE, A2/DI, A3, WR
150
ns
WR low-level width
t
WWRL
WR
200
ns
WR data hold
t
WDH
WR, DATn
0
ns
RDY output delay
t
DRDY
RD, RDY
0
30
ns
Corrected output RD width
t
WDRD
1
RD (BUSWD = L 8 bits)
300
ns
RD (BUSWD = H 16 bits)
540
ns
Corrected output RD width
t
WDRD
2
RD (BUSWD = L 8 bits)
100
300
ns
(when RDY is used)
RD (BUSWD = H 16 bits)
300
540
ns
RDY width (corrected output read)
t
WDRDY
RDY (BUSWD = L 8 bits)
60
210
ns
RDY ((BUSWD = H 16 bits)
300
490
ns
DACK to DREQ delay
t
DREQ
DREQ, DACK
260
ns
DMA cycle wait
t
CYDM
RD, DREQ
420
ns
RD low-level width (DMA)
t
WRDM
RD
300
ns
Parallel I/O
No. 6167-4/29
LC72711W, 72711LW
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
2.7
3.6
V
High-level input voltage
V
IH
1
A0/CL, A1/CE, A2/DI, RST, STNBY
0.7 V
DD
5.5
V
V
IH
2
DACK, WR, RD, CS, SP, BUSWD, A3, IOCNT1, IOCNT2
0.7 V
DD
V
DD
V
Low-level input voltage
V
IL
1
Pins for which V
IH
1 applies
V
SS
0.3 V
DD
V
V
IL
2
Pins for which V
IH
2 applies
V
SS
0.3 V
DD
V
Oscillator frequency
FOSC
This IC operates with a frequency precision of 250 ppm
7.2
MHz
X
IN
input sensitivity
VXI
With a sine wave input to X
IN
, capacitor coupling.
400
900
mVrms
V
DD
= +2.7 to +3.6 V
VMPX1
With a 100% modulated composite signal input to
120
350
mVrms
Input amplitude
MP
XIN
. V
DD
= +3.3 V
VMPX2
With a 100% modulated composite signal input
120
180
mVrms
to MP
XIN
. V
DD
= +2.7 V
Clock low-level period
t
CL
A0/CL
0.7
s
Clock high-level period
t
CH
A0/CL
0.7
s
Data setup time
t
SU
A0/CL, A2/DI
0.7
s
Data hold time
t
HD
A0/CL, A2/DI
0.7
s
CE wait time
t
EL
A0/CL, A1/CE
0.7
s
CE setup time
t
ES
A0/CL, A1/CE
0.7
s
CE hold time
t
EH
A0/CL, A1/CE
0.7
s
Data latch change time
t
LC
A1/CE
0.7
s
Data output time
t
DDO
DO, A0/CL
277
555
ns
CRC4 change time
t
CRC
CRC4, A0/CL
0.7
s
[LC72711LW]
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
= 0 V
Serial I/O
No. 6167-5/29
LC72711W, 72711LW
[LC72711LW]
Allowable Operating Ranges: Parallel Interface
at Ta = 40 to +85C, V
SS
= 0 V
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the "RD low-level width" and the "Corrected output RD width" values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the "RD low-level width" will be 280 ns (minimum).
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Address to RD setup
t
SARD
A0/CL, A1/CE, A2/DI, A3, RD
20
ns
RD to address hold
t
HARD
A0/CL, A1/CE, A2/DI, A3, RD, t
WRDL
250 ns
20
ns
RD low-level width
t
WRDL
1
RD
280
ns
RD low-level width (when RDY is used)
t
WRDL
2
RD
100
280
ns
RD cycle wait
t
CYRD
A0/CL, A1/CE, A2/DI, A3, RD
150
ns
RDY width (Register read)
t
WRDY
RDY
60
230
ns
RD data hold
t
RDH
RD, DATn
0
ns
Address to WR setup
t
SAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR to address hold
t
HAWR
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR cycle wait
t
CYWR
A0/CL, A1/CE, A2/DI, A3, WR
150
ns
WR low-level width
t
WWRL
WR
200
ns
WR data hold
t
WDH
WR, DATn
0
ns
RDY output delay
t
DRDY
RD, RDY
0
50
ns
Corrected output RD width
t
WDRD
1
RD (BUSWD = L 8 bits)
300
ns
RD (BUSWD = H 16 bits)
540
ns
Corrected output RD width
t
WDRD
2
RD (BUSWD = L 8 bits)
100
300
ns
(when RDY is used)
RD (BUSWD = H 16 bits)
300
540
ns
RDY width (corrected output read)
t
WDRDY
RDY (BUSWD = L 8 bits)
60
230
ns
RDY ((BUSWD = H 16 bits)
300
490
ns
DACK to DREQ delay
t
DREQ
DREQ, DACK
260
ns
DMA cycle wait
t
CYDM
RD, DREQ
420
ns
RD low-level width (DMA)
t
WRDM
RD
300
ns
Parallel I/O
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