CMOS IC
Ordering number : ENN6488
42800TN (OT) No. 6488-1/14
LC72720Y, 72720YV
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Overview
The LC72720Y and LC72720YV are single-chip system
ICs that implement the signal processing required by the
European Broadcasting Union RDS (Radio Data System)
standard and by the US NRSC (National Radio System
Committee) RDBS (Radio Broadcast Data System)
standard. These ICs include band-pass filter, demodulator,
synchronization, and error correction circuits as well as
data buffer RAM on chip and perform effective error
correction using a soft-decision error correction technique.
Functions
Band-pass filter: Switched capacitor filter (SCF)
Demodulator: RDS data clock regeneration and
demodulated data reliability information
Synchronization: Block synchronization detection (with
variable backward and forward protection conditions)
Error correction: Soft-decision/hard-decision error
correction
Buffer RAM: Adequate for 24 blocks of data (about 500
ms) and flag memory
Data I/O: CCB interface (power on reset)
Features
Error correction capability improved by soft-decision
error correction.
The load on the control microprocessor can be reduced
by storing decoded data in the on-chip data buffer RAM.
Two synchronization detection circuits provide
continuous and stable detection of the synchronization
timing.
Data can be read out starting with the backward-
protection block data after a synchronization reset.
Fully adjustment free.
Low voltage (supply voltage: 3.0 V min) type.
Operating power-supply voltage: 3.0 to 3.6 V
Operating temperature: 40 to +85C
Package: DIP24S, SSOP30
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
Single-Chip RDS
Signal-Processing System IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
Pin Assignment
Block Diagram
No. 6488-2/14
LC72720Y, 72720YV
A13195
1
24
VREF
SYR
2
23
MPXIN
CE
3
22
Vdda
DI
4
21
Vssa
CL
5
20
FLOUT
DO
6
19
CIN
LC72720Y
Top view
RDS-ID
7
18
T1
SYNC
8
17
T2
T7(CORREC/ARI-ID/BEO)
9
16
T3(RDCL)
T6(ERROR/57K/BE1)
10
15
T4(RDDA)
Vssd
11
14
T5(RSFT)
Vddd
12
13
XOUT
XIN
A13196
1
30
VREF
SYR
2
29
MPXIN
CE
3
28
Vdda
DI
4
27
NC
NC
5
26
Vssa
CL
6
25
FLOUT
LC72720YV
Top view
DO
7
24
CIN
RDS-ID
8
23
NC
NC
9
22
T1
SYNC
10
21
T2
T7(CORREC/ARI-ID/BEO)
11
20
T3(RDCL)
NC
T4(RDDA)
T5(RSFT)
T6(ERROR/57K/BE1)
NC
Vssd
Vddd
12
19
13
18
14
17
15
16
XOUT
XIN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
SMOOTHING
FILTER
57kHz
BPF
(SCF)
TEST
+
PLL
(57kHz)
VREF
CLOCK
RECOVERY
(1187.5Hz)
DATA
DECODER
SYNC
DETECT-2
SYNC
DETECT-1
OSC/DIVIDER
MEMORY CONTROL
CLK(4.332MHz)
+3.3V
+3.3V
Vdda
Vssa
MPXIN
T2
T3 to T7
T1
CCB
DI
CE
CL
RAM
(24 BLOCK DATA)
ERROR CORRECTION
(SOFT DECISION)
SYNC/EC CONTROLLER
DO
XIN
XOUT
SYR
SYNC
RDS-ID
Vssd
Vddd
CIN
FLOUT
VREF
A13197
0.48
(3.25)
3.3
3.9max
0.51min
21.0
(0.71)
1.78
0.25
7.62
6.4
1
12
24
13
0.95
0.9
SANYO: DIP24S
[LC72720Y]
1
15
16
7.6
0.65
9.75
0.5
5.6
0.1
1.5max
30
0.22
(0.33)
0.15
(1.3)
SANYO: SSOP30
[LC72720YV]
Package Dimensions
unit: mm
3067A-DIP24S
unit: mm
3191A-SSOP30
Pin Functions
No. 6488-3/14
LC72720Y, 72720YV
Pin No.
Pin name
Function
I/O
Pin circuit
1
VREF
Reference voltage output (Vdda/2)
Output
2
MPXIN
Baseband (multiplexed) signal input
Input
5 / 6
FLOUT
Subcarrier output (filter output)
Output
6 / 7
CIN
Subcarrier input (comparator input)
Input
3
Vdda
Analog system power supply (+3.3 V)
--
--
4 / 5
Vssa
Analog system ground
--
--
12 / 15
XOUT
Crystal oscillator output (4.332/8.664 MHz)
Output
13 / 16
XIN
Crystal oscillator input (external reference signal input)
7 / 9
T1
Test input (This pin must always be connected to ground.)
Input
8 / 10
T2
Test input (standby control)
0: Normal operation, 1: Standby state (crystal oscillator stopped)
9 / 11
T3 (RDCL)
Test I/O (RDS clock output)
10 / 13
T4 (RDDA)
Test I/O (RDS data output)
11 / 14
T5 (RSFT)
Test I/O (soft-decision control data output)
16 / 20
T6 (ERROR/57K/BE1)
Test I/O (error status output, regenerated carrier output, error block count
I/O
*
output)
17 / 21
T7 (CORREC/ARI-ID/BE0)
Test I/O (Error correction status output, SK detection output, error block count
output)
18 / 22
SYNC
Block synchronization detection output
19 / 24
RDS-ID
RDS detection output
Output
20 / 25
DO
Data output
21 / 26
CL
Clock input
22 / 28
DI
Data input
Input
23 / 29
CE
Chip enable
24 / 30
SYR
Synchronization and RAM address reset (active high)
14 / 17
Vddd
Digital system power supply (+3.3 V)
--
--
15 / 18
Vssd
Digital system ground
--
--
Note:
*
Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user applications.
Pins 4, 8, 12, 19, 23, 27 are NC (NO CONNECT) Pins for the SSOP package version.
Serial data interface (CCB)
Vdda
Vssa
A13198
Vdda
Vssa
A13199
A13200
+
Vdda
VREF
Vssa
A13201
+
Vddd
Vssd
A13202
XOUT
XIN
A13203
Vssd
S
A13204
Vssd
A13205
Vssd
A13206
Vssd
S
No. 6488-4/14
LC72720Y, 72720YV
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
Vddd, Vdda
0.3 to +7.0
V
V
IN
1 max
CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC
0.3 to +7.0
V
Maximum input voltage
V
IN
2 max
XIN
0.3 to Vddd +0.3
V
V
IN
3 max
MPXIN, CIN
0.3 to Vdda +0.3
V
V
O
1 max
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7
0.3 to +7.0
V
Maximum output voltage
V
O
2 max
XOUT
0.3 to Vddd +0.3
V
V
O
3 max
FLOUT
0.3 to Vdda +0.3
V
I
O
1 max
DO, T3, T4, T5, T6, T7
6.0
mA
Maximum output current
I
O
2 max
XOUT, FLOUT
3.0
mA
I
O
3 max
SYNC, RDS-ID
20.0
mA
Allowable power dissipation
Pd max
Ta
85C
DIP24S: 350
mW
SSOP30: 150
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C, Vssd = Vssa = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
Vddd, Vdda
3.0
3.6
V
V
DD
2
Vddd: Serial data hold voltage
2.0
V
Input high-level voltage
V
IH
CL, DI, CE, SYR, T1, T2
0.7 Vddd
6.5
V
Input low-level voltage
V
IL
CL, DI, CE, SYR, T1, T2
0
0.3 Vddd
V
Output voltage
V
O
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7
6.5
V
V
IN
1
MPXIN : f = 57 2 kHz
50
mVrms
Input amplitude
V
IN
2
MPXIN : 100% modulation composite
100
mVrms
V
XIN
XIN
400
1500
mVrms
Guaranteed crystal oscillator frequencies
Xtal
XIN, XOUT : CI
120
(XS = 0)
4.332
MHz
XIN, XOUT : CI
70
(XS = 1)
8.664
MHz
Crystal oscillator frequency deviation
TXtal
XIN, XOUT : f
O
= 4.332 MHz, 8.664 MHz
100
ppm
Data setup time
t
SU
DI, CL
0.75
s
Data hold time
t
HD
DI, CL
0.75
s
Clock low-level time
t
CL
CL
0.75
s
Clock high-level time
t
CH
CL
0.75
s
CE wait time
t
EL
CE, CL
0.75
s
CE setup time
t
ES
CE, CL
0.75
s
CE hold time
t
EH
CE, CL
0.75
s
CE high-level time
t
CE
CE
20
ms
Data latch change time
t
LC
1.15
s
t
DC
DO, CL: Differs depending on the value of the
0.46
s
Data output time
pull-up resistor used.
t
DH
DO, CE: Differs depending on the value of the
0.46
s
pull-up resistor used.
Allowable Operating Ranges
at Ta = 40 to +85C, Vssd = Vssa = 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input resistance
Rmpxin
MPXINVssa : f = 57 kHz
23
k
Internal feedback resistance
Rf
XIN
1.5
M
Center frequency
fc
FLOUT
56.5
57.0
57.5
kHz
3 dB bandwidth
BW 3 dB FLOUT
2.5
3.0
3.5
kHz
Gain
Gain
MPXINFLOOUT : f = 57 kHz
28
31
34
dB
Att1
FLOUT :
f = 7 kHz
30
dB
Stop band attenuation
Att2
FLOUT : f < 45 kHz, f > 70 kHz
40
dB
Att3
FLOUT : f < 20 kHz
50
dB
Electrical Characteristics
at Ta = 40 to +85C, Vssd = Vssa = 0 V
Continued on next page.
No. 6488-5/14
LC72720Y, 72720YV
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Group delay deviation
G-Delay
FLOUT: f = 57
1.2 kHz
2.0 s
Reference voltage output
Vref
VREF : Vdda = 3.3 V
1.65
V
Hysteresis
V
HIS
CL, DI, CE, SYR, T1, T2
0.1 Vddd
V
Output low-level voltage
V
OL
1
DO, T3, T4, T5, T6, T7 : I = 2 mA
0.5
V
V
OL
2
SYNC, RDS-ID : I = 8 mA
0.5
V
Input high-level current
I
IH
1
CL, DI, CE, SYR, T1, T2 : V
I
= Vddd
5.0
A
I
IH
2
XIN : V
I
= Vddd
0.9
4.0
A
Input low-level current
I
IL
1
CL, DI, CE, SYR, T1, T2 : V
I
= 0 V
5.0
A
I
IL
2
XIN : V
I
= 0 V
0.9
4.0
A
Output off leakage current
I
OFF
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :
5.0
A
V
O
= 6.5 V
Current drain
IDD
Vddd + Vdda, Vddd = Vdda = 3.3 V
6
mA
Continued from preceding page.
CCB Output Data Format
Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
Any number of 32-bit output data blocks can be output consecutively.
When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit is remaining to be read, it will not be possible to reread that whole block.
The check bits (10 bits) are not output.
The data valid / invalid decision is made by referencing the error information flag (E0 to E2) but the offset word
detection flag (OWD) must not be referred to.
When the first leading bits are not "1010", the read in data is invalid, and the read operation is cancelled.
(1) Offset word detection flag (1 bit): OWD
OWD
Offset word detection
1
Detected
0
Not detected (protection function operating)
DI
DO
A13207
0
1
0
1
0 OWD B2 B1 B0 RE RF1 RF0 ARI SYC E2 E1 E0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
B1
B0
1
B2
1
B3
0
A0
1
A1
1
A2
0
A3
CCB address 6C
Output data/first bit
Last bit
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI (SK) detection flag
(4) RAM data remaining flags
(3) Consecutive RAM read out possible flag
(2) Offset word information flags
(1) Offset word detection flag
Fixed pattern (1010)
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