CMOS LSI
Ordering number : EN4828A
63096HA (OT)/N1594TH (OT) B8-1326, 1328 No. 4828-1/16
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Asynchronous Silicon Gate 1/2 Duty LCD Driver
with On-Chip Key Input Function
LC75852E, 75852W
Overview
The LC75852E and LC75852W are 1/2 duty dynamic
LCD display drivers. In addition to being able to directly
drive LCD panels with up to 90 segments, they can also
control up to four general-purpose output ports. These
products also include a key scan circuit which allows
them to accept input from keypads with up to 30 keys.
This allows end product front panel wiring to be
simplified.
Features
Up to 30 key inputs (Key scan is only performed when a
key is pressed.)
1/2 duty 1/2 bias (up to 90 segments)
Sleep mode and the all segments off function can be
controlled from serial data.
Segment output port/general-purpose output port usage
can be controlled from serial data.
Serial data I/O supports CCB format communication
with the system controller.
High generality since display data is displayed directly
without decoder intervention
Reset pin that can establish the initial state.
Package Dimensions
unit: mm
3159-QFP64E
unit: mm
3190-SQFP64
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
DD
0.3 to +7.0
V
Input voltage
V
IN
OSC, CE, CL, DI, RES, KI1 to KI5
0.3 to V
DD
+ 0.3
V
Output voltage
V
OUT
OSC, DO, S1 to S45, COM1, COM2, KS1 to KS6, P1 to P4
0.3 to V
DD
+ 0.3
V
I
OUT
1
S1 to S45
100
A
Output current
I
OUT
2
COM1, COM2, KS1 to KS6
1
mA
I
OUT
3
P1 to P4
5
mA
Allowable power dissipation
Pd max
Ta = 85C
200
mW
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO's original bus format and all the bus
addresses are controlled by SANYO.
[LC75852E]
SANYO: QIP64E
SANYO: SQFP64
[LC75852W]
Allowable Operating Ranges
at Ta = 40 to +85C, V
SS
= 0 V
Note:
*
Since DO is an open-drain output, these values differ depending on the pull-up resistor R
PU
and the load capacitance C
L
.
Electrical Characteristics in the Allowable Operating Ranges
No. 4828-2/16
LC75852E, 75852W
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
V
DD
4.5
6.0
V
Input high-level voltage
V
IH
1
CE, CL, DI, RES
0.8 V
DD
V
DD
V
V
IH
2
KI1 to KI5
0.6 V
DD
V
DD
V
Input low-level voltage
V
IL
CE, CL, DI, RES, KI1 to KI5
0
0.2 V
DD
V
Recommended external
R
OSC
OSC
62
k
resistance
Recommended external
C
OSC
OSC
680
pF
capacitance
Guaranteed oscillator range
f
OSC
OSC
25
50
100
kHz
Data setup time
t
ds
CL, DI: Figure 1
160
ns
Data hold time
t
dh
CL, DI: Figure 1
160
ns
CE wait time
t
cp
CE, CL: Figure 1
160
ns
CE setup time
t
cs
CE, CL: Figure 1
160
ns
CE hold time
t
ch
CE, CL: Figure 1
160
ns
High-level clock pulse width
t
H
CL: Figure 1
160
ns
Low-level clock pulse width
t
L
CL: Figure 1
160
ns
Rise time
t
r
CE, CL, DI: Figure 1
160
ns
Fall time
t
f
CE, CL, DI: Figure 1
160
ns
DO output delay time
t
dc
DO, R
PU
= 4.7 k
, C
L
= 10 pF
*
: Figure 1
1.5
s
DO rise time
t
dr
DO, R
PU
= 4.7 k
, C
L
= 10 pF
*
: Figure 1
1.5
s
RES switching time
t2
Figure 2
10
s
Parameter
Symbol
Conditions
min
typ
max
Unit
Hysteresis
V
H
CE, CL, DI, RES, KI1 to KI5
0.1 V
DD
V
Input high-level current
I
IH
CE, CL, DI, RES: V
I
= 6.0 V
5.0
A
Input low-level current
I
IL
CE, CL, DI, RES: V
I
= 0 V
5.0
A
Input floating voltage
V
IF
KI1 to KI5
0.05 V
DD
V
Pull-down resistance
R
PD
KI1 to KI5: V
DD
= 5.0 V
50
100
250
k
Output off leakage current
I
OFFH
DO: V
O
= 6.0 V
6.0
A
V
OH
1
KS1 to KS6: I
O
= 1 mA
V
DD
1.0
V
Output high-level voltage
V
OH
2
P1 to P4: I
O
= 1 mA
V
DD
1.0
V
V
OH
3
S1 to S45: I
O
= 10 A
V
DD
1.0
V
V
OH
4
COM1, COM2: I
O
= 100 A
V
DD
0.6
V
V
OL
1
KS1 to KS6: I
O
= 50 A
0.4
1.0
3.0
V
V
OL
2
P1 to P4: I
O
= 1 mA
1.0
V
Output low-level voltage
V
OL
3
S1 to S45: I
O
= 10 A
1.0
V
V
OL
4
COM1, COM2: I
O
= 100 A
0.6
V
V
OL
5
DO: I
O
= 1 mA
0.1
0.5
V
Output middle-level voltage
V
MID
1
COM1, COM2: V
DD
= 6.0 V, I
O
= 100 A
2.4
3.0
3.6
V
V
MID
2
COM1, COM2: V
DD
= 4.5 V, I
O
= 100 A
1.65
2.25
2.85
V
Current drain
I
DD
1
Sleep mode, Ta = 25C
5
A
I
DD
2
V
DD
= 6.0 V, output open, Ta = 25C, f
OSC
= 50 kHz
1.4
2.5
mA
1. When stopped with CL at the low level
2. When stopped with CL at the high level
Figure 1
Pin Assignment
No. 4828-3/16
LC75852E, 75852W
Block Diagram
Pin Functions
No. 4828-4/16
LC75852E, 75852W
Pin
Pin No.
Function
Active
I/O
Handling when
unused
S1/P1 to S4/P4
S5 to S43
COM1
COM2
KS1/S44,
KS2/S45,
KS3 to KS6
KI1 to KI5
OSC
CE
CL
DI
DO
RES
V
DD
V
SS
1 to 4
5 to 43
44
45
46
47
48 to 51
52 to 56
57
62
63
64
61
59
60
58
Segment outputs: Used to output the display data that is transmitted over the
serial data input. Pins S1/P1 to S4/P4 can be used as general-purpose outputs
according to control data specification.
Common driver outputs. The frame frequency f
O
is (f
OSC
/512) Hz.
Key scan outputs. When a key matrix is formed, normally a diode will be
attached to the key scan timing line to prevent shorts. However, since the
output transistor impedance is an unbalanced CMOS output, it will not be
damaged if shorted. Pins KS1/S44 and KS2/S45 can be used as segment
outputs according to control data specification.
Key scan inputs: Pins with a built-in pull-down resistor.
Oscillator connection: Oscillator circuit can be formed by connecting the pin to
a resistor and a capacitor.
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
DO: Output data
Serial data interface: Connected
to the controller. Since DO is an
open-drain output, it requires a
pull-up resistor.
Reset input that re-initializes the LSI internal states. During a reset, the display
segments are turned off forcibly regardless of the internal display data. All
internal key data is reset to low and the key scan operation is disabled.
However, serial data can be input during a reset.
Power supply connection. A supply voltage of between 4.5 and 6.0 V must be
provided.
Power supply ground connection. Must be connected to GND.
--
--
--
H
--
H
--
--
L
--
--
O
O
O
I
I/O
I
I
I
O
I
--
--
Open
Open
Open
GND
V
DD
GND
Open
GND
--
--
Serial Data Input
1. When stopped with CL at the low level
2. When stopped with CL at the high level
CCB address......................[42H]
D1 to D90 ...........................Display data
S0, S1 ................................Sleep control data
K0, K1 ................................Key scan output/segment output selection data
P0, P1 ................................Segment output port/general-purpose output port selection data
SC ......................................Segment on/off control data
No. 4828-5/16
LC75852E, 75852W
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