Ordering number : ENN6329
32400RM (OT) No. 6329-1/40
Overview
The LC78628E CMOS IC implements signal processing
and servo control for compact disc players, laser disc
players, CD-V, CD-I, and similar products. It provides
functions for demodulation of the EFM signal from the
optical pickup, deinterleaving, error detection and
correction, and processing servo system commands issued
by the system microprocessor. In addition to this basic CD
functionality, it also provides HDCD (High Definition
Compatible Digital) decoding functions and CD text
functions. It also includes a built-in EFM PLL circuit.
Functions
Full decoding and playback for discs encoded with the
HDCD technique developed by Pacific Microsonics,
Inc.
Slices the high-frequency input signal at an accurate
level, converts it into the EFM signal, and generates a
PLL clock with an average frequency of 4.3218 MHz
performing a phase comparison with an internal VCO.
Accurately generates a reference clock signal and all
necessary internal timings using an external 16.9344-
MHz crystal.
Controls the disc motor speed using a frame phase
difference signal created based on the reproduced clock
signal and the reference clock.
Performs detection, protection, and interpolation for the
frame synchronizing signal to assure stable data readout.
Demodulates the EFM signal, converting it to 8-bit
symbol data.
After applying a CRC check to the subcode Q signal,
outputs that data to the control microprocessor using
serial data transfer.
Continued on next page.
Package Dimensions
unit: mm
3174-QIP80E
0.15
1.6
14.0
17.2
0.8
1
24
25
40
41
64
65
80
21.6
0.8
3.0max
1.0
2.7
15.6
0.8
1.6
0.35
23.2
20.0
0.8
0.8
SANYO: QIP80E
[LC78628E]
LC78628E
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Compact Disc Player DSP with Built-in HDCD Decoder
CMOS IC
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft's
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
HDCD (High Definition Compatible Digital) is a registered trademark of Pacific Microsonics, Inc.
in the US and other countries.
A license from Pacific Microsonics, Inc. is required to use this product.
Sanyo Electric Co., Ltd. has acquired license for the use of HDCD technology from Pacific Microsonics, Inc.
The following patents apply to the design of this product:
USA: 5479168, 5638074, 5640161, 5808574, 5838274, 5854600, and 5872531.
Australia: 669114
Other patents have also been applied for.
Continued from preceding page.
Buffers the demodulated EFM signal data in internal
RAM and compensates for 4 frames of jitter due to
disc speed fluctuations.
Performs unscrambling and deinterleaving by reordering
the demodulated EFM signal data to the stipulated order.
Performs error detection and correction and flag
processing (C1: dual errors, C2: dual errors)
The C2 flags are set based on the C1 flags and the result
of the C2 processing, and the signal is interpolated or
muted according to the C2 flags. Four-sample
interpolation is adopted in the interpolation circuit.
Linear (average value) interpolation is applied if up to
three consecutive errors are indicated by the C2 flags,
and muting at the zero level is applied if four or more
consecutive errors are indicated.
Performs track jump, focus start, disc motor start/stop,
muting on/off, track count, and other operations by
executing 8- or 16-bit commands serially input from the
system microprocessor.
Supports high-speed disc access operations based on
arbitrary track counts.
Provides digital outputs.
Built-in
D/A converter based on a third-order noise
shaper.
Zero-cross muting
Digital attenuator and deemphasis filter
Support 2
speed playback
Bilingual function
Built-in text decoder
Five general-purpose I/O ports
Features
80-pin QFP package
Fabricated in a silicon gate CMOS process
3.3 and 5 V power supply voltages
No. 6329-2/40
LC78628E
EFMO
VV
DD
VV
SS
PDO
ISET
FR
PCK
TAI
TST11
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
V
SS
V
DD
3V
V
SS
LRSY
C2F
ROMXA
LRCKI
BCKI
DATAI
DOUT
GAIN
HDCD
DFOLO
DACKO
LRCKO
DFORO
RWC
COIN
CQCK
SQOUT
WRQ
CS
TEST6
V/P
Slice level
control
Synchronization
EFM demodulation
CLV
digital servo
Subcode
separation
Q CRC
Microprocessor
interface
Servo
commander
I/O ports
Text
decoder
Crystal oscillator
System timing generator
1-bit DAC
MUX
M
U
X
HDCD
decoder
Interpolation
mute
2k
8bits
RAM
C1 and C2 error
detection and correction
flag processing
VCO
clock control
RAM address
generator
Bilingual
MUX, SP
Digital
output
8Fs HDCD
interpolation
filter
De-emphasis
attenuator
CLV
CLV+
FSEQ
EFMIN
DEFI
MUTEL
LV
DD
LCHN LCHP
RV
SS
LV
SS
RCHP
MUTER
RV
DD
XV
DD
XOUT
XIN
XV
SS
FSX
CK2
4.2M
16M
EFLG
SRDT
DQSY
SCLK
EMPH
P4
P3
P2
P1
P0
TGL
RES
JP+
JP
TOFF
TES
PCCL
HFL
RCHN
A12795
Block Diagram
Pin Assignment
No. 6329-3/40
LC78628E
A12796
SQOUT
COIN
CQCK
RES
TST11
SCLK
DQSY
4.2M
LC78628E
SRDT
TEST5
CS
LRSY
CK2
ROMXA
C2F
TEST1
P2
P1
P0
GAIN
DACKO
DFOLO
DFORO
LRCKO
EMPH
TEST4
16M
JP
JP+
VDD3V
TEST3
HDCD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RWC
64
WRQ
63
FSX
62
BCKI
61
TEST6
60
DATAI
59
EFLG
58
LRCKI
57
DOUT
56
MUTER
55
RV
DD
54
RCHP
53
RCHN
52
RV
SS
51
LV
SS
50
LCHN
49
LCHP
48
LV
DD
47
MUTEL
46
XV
SS
45
XOUT
44
XIN
43
XV
DD
42
P3
41
DEFI
1
TAI
2
PDO
3
VV
SS
4
ISET
5
VV
DD
6
FR
7
V
SS
8
V
SS
9
EFMO
10
EFMIN
11
TEST2
12
CLV+
13
CLV
14
V/P
15
V
DD
16
P4
17
PCCL
18
HFL
19
TES
20
PCK
21
FSEQ
22
TOFF
23
TGL
24
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max1
V
DD
, VV
DD
, XV
DD
, LV
DD
, RV
DD
V
SS
0.3 to V
SS
+ 6.0
V
V
DD
max2
V
DD
3V
V
SS
0.3 to V
SS
+ 4.0
V
Input voltage
V
IN
5 max
V
SS
0.3 to V
DD
1 + 0.3
V
V
IN
3 max
V
SS
0.3 to V
DD
2 + 0.3
V
Output voltage
V
OUT
5 max
V
SS
0.3 to V
DD
1 + 0.3
V
V
OUT
3 max
V
SS
0.3 to V
DD
2 + 0.3
V
Allowable power dissipation
Pd max
500
mW
Operating temperature
Topr
20 to +75
C
Storage temperature
Tstg
40 to +125
C
Specifications
Absolute Maximum Ratings
at Ta = 25C, V
SS
= 0 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
V
DD
1
V
DD
, VV
DD
, XV
DD
, LV
DD
, RV
DD
4.5
5.0
5.5
V
V
DD
2
V
DD
3V
3.0
3.3
3.6
V
V
IH
1
DEFI, COIN, RES, HFL, TES, RWC, CQCK, TAI, SCLK,
0.8 V
DD
1
V
DD
1
V
High-level input voltage
CS, PCCL, LRCKI, BCKI, DATAI
V
IH
2
P0 to P4, TEST1 to TEST5, EMPH
0.7 V
DD
1
V
DD
1
V
V
IH
3
EFMIN
0.6 V
DD
1
V
DD
1
V
V
IL
1
DEFI, COIN, RES, HFL, TES, RWC, CQCK, TAI, SCLK,
0
0.2 V
DD
1
V
Low-level input voltage
CS, PCCL, LRCKI, BCKI, DATAI
V
IL
2
P0 to P4, TEST1 to TEST5, EMPH
0
0.3 V
DD
1
V
V
IL
3
EFMIN
0
0.4 V
DD
1
V
Allowable Operating Conditions
at Ta = 25C, V
SS
= 0 V
Continued on next page.
No. 6329-4/40
LC78628E
Continued from preceding page.
Notes: The same voltage must be applied to all 5 V system power supply pins.
*
When used in conjunction with an ASP that provides a command interface, the stricter ratings of the ASP shall be given priority.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Input level
V
IN
1
EFMIN: Slice level control
1.0
Vp-p
V
IN
2
XIN: Capacitor coupled input
1.0
Vp-p
Data setup time
t
SU
COIN, RWC,
*
: See figure 1.
400
ns
Data hold time
t
HD
COIN, RWC,
*
: See figure 1.
400
ns
High-level clock pulse width
t
WH
CQCK,
*
: See figures 1 and 2.
400
ns
Low-level clock pulse width
t
WL
CQCK,
*
: See figures 1 and 2.
400
ns
Data read access time
t
RAC
SQOUT: See figures 2.
0
400
ns
Command output time
t
RWC
RWC,
*
: See figures 1.
1000
ns
Subcode Q readout enable time
t
SQE
WRQ, normal speed: See figures 2, RWC = V
IL
1
11.2
ms
Port input setup time
t
CSU
P0 to P4, RWC: See figures 3.
400
ns
Port input hold time
t
CHD
P0 to P4, RWC: See figures 3.
400
ns
Port input clock setup time
t
RCQ
CQCK, RWC,
*
: See figures 3.
100
ns
Port output data delay time
t
CDD
P0 to P4, RWC: See figure 4.
1200
ns
Text readout period
t
CW
DQSY, normal speed: See figure 5.
1.5
3.3
3.7
ms
DQSY pulse width
t
W
DQSY, normal speed: See figure 5.
60
136
150
s
SCLK high-level clock pulse width
t
WTH
SCLK: See figure 5.
100
ns
SCLK low-level clock pulse width
t
WTL
SCLK: See figure 5.
100
ns
SCLK clock delay time
t
D
1
SCLK: See figure 5.
100
ns
Text data delay time
t
D
2
SRDT: See figure 5.
50
ns
t
D
3
SRDT: See figure 5.
50
ns
Reset time
t
RES
RES
400
ns
Operating frequency range
f
OP
EFMIN
10
MHz
Crystal oscillator frequency
f
X
X
IN
, X
OUT
16.9344
MHz
No. 6329-5/40
LC78628E
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Current drain
I
DD
1
V
DD
, VV
DD
, XV
DD
, LV
DD
, RV
DD
: 4.5 V to 5.5 V
17
24
mA
I
DD
2
V
DD
3V: 3.0 V to 3.6 V
55
85
mA
I
IH
1
DEFI, EFMIN, SCLK, COIN, RES, HFL, TES, RWC,
10
+10
A
High-level input current
CQCK, TEST1, LRCKI, BCKI, DATAI, XIN: V
IN
= V
DD
1
I
IH
2
TAI, TEST2 to TEST5, CS, PCCL: V
IN
= V
DD
1
10
200
A
DEFI, EFMIN, SCLK, COIN, RES, HFL, TES, RWC,
Low-level input current
I
IL
CQCK, TAI, TEST1 to TEST5, CS, PCCL, LRCKI, BCKI,
10
+10
A
DATAI, XIN: V
IN
= 0 V
V
OH
1
EFMO: I
OH
= 1 mA
4
V
CLV
+
, CLV
, V/P, P0 to P4, PCK, FSEQ, TOFF, TGL,
JP
+
, JP
, 16M, EMPH, LRCKO, DACKO, DFOLO,
V
OH
2
DFORO, GAIN, MUTEL, MUTER, DOUT, EFLG, TEST6, V
DD
1 2.1
V
High-level output voltage
FSX, WRQ, SQOUT, TST11, DQSY, 4.2M, SRDT, LRSY,
CK2, ROMXA, C2F: I
OH
= 4 mA
V
OH
3
HDCD: I
OH
= 12 mA
V
DD
1 2.1
V
V
OH
4
LCHP, LCHN, RCHP, RCHN: I
OH
= 1 mA
3.0
4.5
V
V
OL
1
EFMO: I
OL
= 1 mA
1
V
CLV
+
, CLV
, V/P, P0 to P4, PCK, FSEQ, TOFF, TGL,
JP
+
, JP
, 16M, EMPH, LRCKO, DACKO, DFOLO,
Low-level output voltage
V
OL
2
DFORO, GAIN, MUTEL, MUTER, DOUT, EFLG, TEST6,
0.4
V
FSX, WRQ, SQOUT, TST11, DQSY, 4.2M, SRDT, LRSY,
CK2, ROMXA, C2F: I
OL
= 4 mA
V
OL
3
HDCD: I
OL
= 12 mA
0.4
V
V
OL
4
LCHP, LCHN, RCHP, RCHN: I
OH
= 1 mA
0.5
2.0
V
Output off leakage current
I
OFF
1
PDO, CLV
+
, CLV
, JP
+
, JP
, P0 to P4, EMPH, SQOUT,
10
+10
A
EFMO: In the high-impedance output state
Charge pump output current
I
PDOH
PDO: R
ISET
= 68 k
64
80
96
A
I
PDOL
PDO: R
ISET
= 68 k
96
80
64
A
Electrical Characteristics
at Ta = 25C, V
DD
1 = 5 V, V
DD
2 = 3.3 V, V
SS
= 0 V
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