91400 RM (IM) SK No.6690-1/22
Ver.1.03
80696
Preliminary
Overview
The LC86P6548 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC866500 series.
This microcontroller has the function and the pin description of the LC866500 series mask ROM version, and 48K-byte
PROM.
Features
(1) Option switching by PROM data
The option function of the LC866500 series can be specified by the PROM data.
LC86P6548 can be checked the function of the trial pieces using the mass production board.
(2) Internal one-time PROM capacity
: 49408 bytes
(3) Internal RAM capacity
: 1152 bytes
Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P6548.
Mask ROM version
PROM capacity
RAM capacity
LC866548 49152
bytes
1152
bytes
LC866540 40960
bytes
1152
bytes
LC866532 32768
bytes
1152
bytes
LC866528 28672
bytes
896
bytes
LC866524 24576
bytes
896
bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package
stamping and the screening. Contact our representative for further information.
8-Bit Single Chip Microcontroller
with One-Time Programmable PROM
LC86P6548
Ordering number : ENN*6690
CMOS IC
LC86P6548
No.6690-2/22
(4) Operating supply voltage
: 4.5V to 6.0V
(5) Instruction cycle time
: 1.0
s to 366
s
(6) Operating temperature
: -30
C to +70
C
(7) The pin and the package compatible with the LC866500 series mask ROM devices
(8) Applicable mask ROM version
: LC866548/LC866540//LC866532/LC866528/LC866524
Notice for use
LC86P6548 is provided for the first release and small shipping of the LC866500 series.
At using, take notice of the followings.
(1) A point of difference LC86P6548 and LC866500 series
Item LC86P6548
LC866548/40/32/28/24
Operation after reset
releasing
The option is specified until 3ms after
going to a `H' level to the reset terminal
by dgrees. The program is executed
from 00H of the program counter.
The program is executed from 00H of the
program counter immediately after going to
a `H' level to reset terminal.
Pull-down resistor of
the following pins
S0/T0 S6/T6
S7/T7 S15/T15
S16 S31
S32 S47
S48 S51
Pull-down resistor
provided/not provided
Not provided
Provided (fixed)
Provided (fixed)
Not provided
Not provided
Pull-down resistor
provided/not provided
Specified by the option
Provided (fixed)
Specified by the option
Specified by the option
Not provided
Power dissipation
Refer to `electrical characteristics' on the semiconductor news.
LC86P6548 uses 256 bytes that is addressed on FF00H to FFFFH in the program memory as the option configuration data
area. This option configuration cannot execute all options which LC866500 series have. Next tables show the options
that correspond and not correspond to LC86P6548.
A kind of the option corresponding of the LC86P6548
A kind of option
Pins, Circuits
Contents of the option
1. N-channel open drain output
2. CMOS output
*1
Port 0
3. Pull-up MOS Tr. proveded
4. Pull-up MOS Tr. not provided
*2
Port 1
*1
1. Input
: Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input
: Programmable pull-up MOS Tr.
Output :
CMOS
Input/output form of
Input/output ports
Port 3
*1
1. Input
: No Programmable pull-up MOS Tr.
Output : N-channel open drain
2. Input
: Programmable pull-up MOS Tr.
Output : CMOS
*1) Specified in a bit
*2) Specified in nibble unit. The port of N-channel open drain output does not have the Pull-up MOS Tr..
LC86P6548
No.6690-3/22
A kind of the option not corresponding of the LC86P6548
A kind of option
Pins, Circuits
LC86P6548
LC866548/40/32/28/24
Pull-down resistor of
the high voltage
Withstand output terminals
S0/T0 to S6/T6
S16 to S31
S32 to S47
Not provided
Provided (fixed)
Not provided
Specified by the option
Specified by the option
Specified by the option
(2) Option
The option data is created by the option specified program "SU86K.EXE". The created option data is linked to the
program area by linkage loader "L86K.EXE".
(3) ROM space
LC86P6548 and LC866500 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the
option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to BFFFH.
(4) Ordering information
1. When ordering the identical mask ROM and PROM devices simultaneously.
Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask
ROM and PROM versions.
2. When ordering a PROM device.
Provide an EPROM containing the target memory contents together with an order form.
0FFFFH
0FF00H
0EFFFH
0DFFFH
0CFFFH
0BFFFH
0AFFFH
9FFFH
8FFFH
7FFFH
6FFFH
5FFFH
4FFFH
3FFFH
2FFFH
1FFFH
0FFFH
0000H
The option
specified area
256 bytes
The option
specified area
Program area
48K bytes
Program area
40K bytes
Program area
32K bytes
Program area
28K bytes
Program area
24K bytes
LC866540
LC866548
LC866532 LC866528 LC866524
The option
specified area
The option
specified area
The option
specified area
LC86P6548
No.6690-4/22
How to use
(1) Specification of option
Programming data for PROM of the LC86P6548 is required.
Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter
program, EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P6548.
(2) How to program for the PROM
LC86P6548 can be programmed by the EPROM programmer with attachment ; W86EP6548Q.
Recommended EPROM programmer
Productor EPROM
programmer
Advantest
R4945, R4944, R4943
Andou AF-9704
AVAL PKW-1100,
PKW-3000
Minato electronics
MODEL 1890A
"27512 (Vpp=12.5V) Intel high speed programming" mode available. The address must be set to
"0 to 0FFFFH" and a jumper (DASEC) must be set to `OFF' at programming.
(3) How to use the data security function
"Data security" is the disabled function to read the data of the PROM.
The following is the process in order to execute the data security.
1. Set `ON' the jumper of attachment.
2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data
security. It is not a trouble of the EPROM programmer or the LSI.
Notes
Data security is not executed when the data of all address have `FFH' at the sequence 2 above.
The programming by a sequential operation "BLANK
PROGRAM
VERIFY" cannot be executed data security at the
sequence 2 above.
Set to `OFF' the jumper after executing the data security.
W86EP6548Q
Data security
1 pin
1 pin mark
of LSI
Not data security
LC86P6548
No.6690-5/22
Pin Assignment
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80
79
78 77
76 75
74 73
72
71 70
69 68
67 66
65 64
63
62 61
60 59
58 57
56 55
54
53 52
51
1
2
3 4
5 6
7 8
9
10 11
12 13
14 15
16 17
18
19 20
21 22
23 24
25 26
27
28 29
30
S48/PG0
S49/PG1
S50/PG2
S51/PG3
P00
P01
P02
P03
VSS2
VDD2
P04
P05
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
S19/PC3
S18/PC2
S17/PC1
S16/PC0
VDD3
S15/T15
S14/T14
S13/T13
S12/T12
S11/T11
S10/T10
S9/T9
S8/T8
S7/T7
S6/T6
S5/T5
S4/T4
S3/T3
S2/T2
S1/T1
S
47/P
F
7
S
46/P
F
6
S
45/P
F
5
S
44/P
F
4
S
43/P
F
3
S
42/P
F
2
S
41/P
F
1
S
40/P
F
0
VDD4
S
39/P
E7
S
38/P
E6
S
37/P
E5
S
36/P
E4
S
35/P
E3
S
34/P
E2
S
33/P
E1
S
32/P
E0
S
31/P
D
7
S
30/P
D
6
S
29/P
D
5
S
28/P
D
4
S
27/P
D
3
S
26/P
D
2
S
25/P
D
1
S
24/P
D
0
S
23/P
C
7
S
22/P
C
6
S
21/P
C
5
S
20/P
C
4
VP
P
16/B
U
Z
Z
P
17/P
W
M
0
P3
0
P3
1
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
P
70/I
N
T
0
RE
S
X
T
1/P
74
X
T
2/P
75
V
SS1
CF
1
CF
2
VDD1
P
80/A
N
0
P
81/A
N
1
P
82/A
N
2
P
83/A
N
3
P
84/A
N
4
P
85/A
N
5
P
86/A
N
6
P
87/A
N
7
P
71/I
N
T
1
P
72/I
N
T
2/T
0
I
N
P
72/I
N
T
3/T
0
I
N
S
0/T
0
LC86P6548
No.6690-6/22
System Block Diagram
Interrupt Control
A15-A0
D7-D0
TA
CE
OE
DASEC
Standby Control
Cl
o
c
k
Ge
n
e
r
a
t
o
r
CF
RC
X'tal
Base Timer
SIO0
SIO1
Timer 0
Timer 1
ADC
INT0-3
Noise Filter
SIO Automatic
transmission
RAM
128 bytes
VFD
Controller
High voltage Output
Bus Interface
Port 1
Port 3
Port 7
Port 8
IR
PLA
PROM
Control
PROM(48KB)
PC
ACC
B Register
C Register
ALU
PSW
RAR
RAM
Stack Pointer
Port 0
Watchdog Timer
LC86P6548
No.6690-7/22
LC86P6548 Pin Description
Pin name
I/O
Function description
Option
PROM mode
VSS1,2 -
Power
pin
(-)
*4
-
-
VDD1,2,3,4 - Power
pin
(+)
*4 -
-
VP
-
Power pin (+) for the VFD output pull-down resist
-
-
PORT0
P00 to P07
I/O 8-bit input/output port
Input for port 0 interrupt
Input/output in nibble units
Input for HOLD release
15V withstand at N-channel open drain
output
Pull-up resistor :
Provided/Not provided
(each nibble)
Output form :
CMOS/N-channel open
drain (each bit)
-
PORT1
P10 to P17
I/O 8-bit input/output port
Input/output can be specified in a bit unit
Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
Output form :
CMOS/N-channel open
drain (each bit)
Data line
D0 to D7
PORT3
P30 to P37
I/O 8-bit input/output port
Input/output in bit unit
15V withstand at N-channel open drain
output
Output form :
CMOS/N-channel open
drain (each bit)
-
4-bit input/output port
Input/output in bit unit
2-bit input port
Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event
input
P74 : 32.768kHz crystal oscillation terminal XT1
P75 : 32.768kHz crystal oscillation terminal XT2
Interrupt received forms, the vector addresses
rising falling rising
&
falling
high
level
low
level
vector
INT0 enable enable disable enable enable 03H
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
PORT7
P70 to P73
P74
to P75
I/O
I
INT3 enable enable enable disable disable 1BH
PROM control
signals
DASEC (*1)
OE (*2)
,bE (*3)
Continue.
CE
LC86P6548
No.6690-8/22
Pin name I/O
Function description
Option
PROM mode
PORT8
P80 to 83
P84 to 87
I
I/O
4-bit input port
Input/output in bit unit
4-bit input port
Other function
AD input port (8 port pins)
- -
S0/T0 to
S6/T6 *6
O Output for VFD display controller
segment/timing in common
- -
S7/T7 to
S15/T15
*7
O
Output for VFD display controller
segment/timing with internal pull-down
resistor in common
Internal pull-down resistor output
- TA
(*5)
S16 to S31
*8
I/O Output for VFD display controller Segment
output
Other function
S16 : High voltage input port PC0
S17 : High voltage input port PC1
S18 : High voltage input port PC2
S19 : High voltage input port PC3
S20 : High voltage input port PC4
S21 : High voltage input port PC5
S22 : High voltage input port PC6
S23 : High voltage input port PC7
S24 : High voltage input port PD0
S25 : High voltage input port PD1
S26 : High voltage input port PD2
S27 : High voltage input port PD3
S28 : High voltage input port PD4
S29 : High voltage input port PD5
S30 : High voltage input port PD6
S31 : High voltage input port PD7
- Address
input
A15 to A0
S32 to S47
*9
I/O Output for VFD display controller Segment
Other function
S32 : High voltage input port PE0
S33 : High voltage input port PE1
S34 : High voltage input port PE2
S35 : High voltage input port PE3
S36 : High voltage input port PE4
S37 : High voltage input port PE5
S38 : High voltage input port PE6
S39 : High voltage input port PE7
S40 : High voltage I/O port PF0
S41 : High voltage I/O port PF1
S42 : High voltage I/O port PF2
S43 : High voltage I/O port PF3
S44 : High voltage I/O port PF4
S45 : High voltage I/O port PF5
S46 : High voltage I/O port PF6
S47 : High voltage I/O port PF7
- -
Continue.
LC86P6548
No.6690-9/22
Pin name
I/O
Function description
Option
PROM mode
S48 to S51
*9
I/O Output for VFD display controller Segment
Other function
S48 : High voltage I/O port PG0
S49 : High voltage I/O port PG1
S50 : High voltage I/O port PG2
S51 : High voltage I/O port PG3
- -
RES
I Reset
pin
-
-
XT1/ P74
I
Input pin for 32.768kHz crystal oscillation
Other function
XT1 : Input port P74
In case of non use, connect to VDD1.
- -
XT2/P75
O
Output pin for 32.768kHz crystal oscillation
Other function
XT2 : Input port P75
In case of non use, connect to VDD1 at using
as port or unconnect at using as oscillation.
- -
CF1
I
Input pin for the ceramic resonator oscillation
-
-
CF2
O
Output pin for the ceramic resonator oscillation
-
-
All of port options (except pull-up resistor of port 0) can be specified in bit unit.
*1 Memory select input for data security
*2 Output enable input
*3 Chip enable input
*4 Connect like the following figure to reduce noise into a VDD1 terminal.
Shorted the VSS1 terminal to the VSS2 terminal and to make the back-up time long.
*5 TA
! PROM control signal input
*6 S0/T0 to S6/T6 : not provided the pull-down resistor
*7 S7/T7 to S15/T15 : provided the pull-down resistor (fixed)
*8 S16 to S31 : provided the pull-down resistor (fixed)
*9 S32 to S51 : not provided the pull-down resistor
Power
Supply
LSI
VDD1
Back-up capacitor
VDD2
VDD3
VSS2
VSS1
VDD4
VFD
powers
LC86P6548
No.6690-10/22
1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25
C
Ratings
Parameter Symbol
Pins
Conditions
VDD
[V]
min. typ.
max.
unit
Supply voltage
VDDMAX
VDD1, VDD2
VDD3, VDD4
VDD1=VDD2
=VDD3=VDD4
-0.3
+7.0
VI(1) Ports
74
,75
Ports 80,81,82,83
Port 8
RES
-0.3
VDD+
0.3
Input voltage
VI(2) VP
VDD-45
VDD+
0.3
Output voltage
VO(1)
S0/T0 to S15/T15
VDD-45
VDD+
0.3
VIO(1) Port
1
Ports 70,71,72,73
Ports 84,85,86,87
Ports 0, 3 at CMOS
output option
-0.3
VDD+
0.3
VIO(2)
Ports 0, 3 at N-ch open
drain output option
-0.3
15
Input/Output
voltage
VIO(3)
S16 to S51
VDD-45
VDD+
0.3
V
IOPH(1) Ports 0, 1, 3
CMOS output
At each pins
-10
IOPH(2) S0/T0 to S15/T15
At each pins
-30
Peak
output
current
IOPH(3) S16 to S51
At each pins
-15
IOAH(1) Port 0
The total of all pins
-30
IOAH(2) Ports 1, 3
The total of all pins
-30
IOAH(3) S0/T0 to S15/T15
The total of all pins
-55
IOAH(4) S16 to S27
The total of all pins
-60
IOAH(5) S28to S39
The total of all pins
-60
High
level
output
current
Total
output
current
IOAH(6) S40 to S51
The total of all pins
-60
IOPL(1)
Ports 0,1,3
At each pins
20
Peak
output
current
IOPL(2) Ports
70,71,72,73
Ports 84,85,86,87
At each pins
15
IOAL(1) Port 0
The total of all pins
60
IOAL(2) Ports 1,3,70
The total of all pins
50
Low
level
output
current Total
output
current
IOAL(3) Ports 71,72,73
Ports 84,85,86,87
The total of all pins
20
mA
Maximum
power
dissipation
Pdmax QFP100E
Ta=-30
to+70
C
500
mW
Operating
temperature
range
Topr
-30 70
Storage
temperature
range
Tstg
-55
125
C
LC86P6548
No.6690-11/22
2. Recommended Operating Range at Ta=-30
C to +70
C, VSS1=VSS2=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
Operating
Supply voltage
VDD(1) VDD1=VDD2
=VVDD3=VDD4
0.98s
t
CYC
t
CYC
400s
4.5 6.0
Hold voltage
VHD
VDD1=VDD2
RAMs and the
registers hold
voltage at HOLD
mode.
2.0 6.0
Pull-down
Voltage
VP VP
4.5
to
6.0
-35
VDD
VIH(1)
Port 0 at CMOS output
Output disable
4.5 to 6.0 0.33VDD
+1.0
VDD
VIH(2)
Port 0 at N-ch open drain
output
Output disable
4.5 to 6.0 0.75VDD
13.5
VIH(3) Port
1
Ports 72,73
Port 3 at CMOS
output
Output disable
4.5 to 6.0 0.75VDD
VDD
VIH(4)
Port 3 at N-ch open
drain output
Output disable
Tr. OFF
4.5 to 6.0 0.75VDD
13.5
VIH(5) Port
70
Port input/interrupt
Port 71
RES
Output disable
4.5 to 6.0 0.75VDD
VDD
Input high
voltage
VIH(6) Port
70
Watchdog timer
Output disable
4.5 to 6.0 0.9VDD
VDD
VIH(7) Port
8
Ports 74 ,75
Output disable
4.5 to 6.0 0.75VDD
VDD
VIH(8)
S16 to S51
Output P-channel
Tr. OFF
4.5 to 6.0 0.33VDD
+1.0
VDD
VIL(1)
Port 0 at CMOS
output option
Output disable
4.5 to 6.0
VSS
0.2VDD
VIL(2)
Port 0 at N-ch open
drain output
Output disable
4.5 to 6.0
VSS
0.25VDD
VIL(3) Ports
1,3
Ports 72,73
Output disable
4.5 to 6.0
VSS
0.25VDD
VIL(4) Port
70
Port input/interrupt
Port 71
RES
Output disable
4.5 to 6.0
VSS
0.25VDD
VIL(5) Port
70
Watchdog timer
Output disable
4.5 to 6.0
VSS
0. 8VDD
-1.0
VIL(6) Port
8
Ports 74 ,75
Output disable
4.5 to 6.0
VSS
0.25VDD
Input low
voltage
VIL(7)
S16 to S51
Output P-channel
Tr. OFF
4.5 to 6.0
VP
0.2VDD
V
Operation
cycle time
t
CYC
4.5
to
6.0
0.98
400
s
Continue.
LC86P6548
No.6690-12/22
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
FmCF(1) CF1,
CF2
6MHz
(ceramic resonator
oscillation)
Refer to figure 1
4.5 to 6.0
6
FmCF(2) CF1,
CF2
3MHz
(ceramic resonator
oscillation)
Refer to figure 1
4.5 to 6.0
3
FmRC
RC oscillation
4.5 to 6.0
0.3
0.8
3.0
MHz
Oscillation
frequency
range
(Note 1)
FsXtal XT1,
XT2 32.768kHz
(crystal oscillation)
Refer to figure 2
4.5 to 6.0
32.768
kHz
tmsCF(1) CF1,
CF2
6MHz
(ceramic resonator
oscillation)
Refer to figure 3
4.5 to 6.0
tmsCF(2) CF1,
CF2
3MHz
(ceramic resonator
oscillation)
Refer to figure 3
4.5 to 6.0
ms
Oscillation
stabilizing
time period
(Note 1)
tssXtal XT1,
XT2 32.768kHz
(crystal oscillation)
Refer to figure 3
4.5 to 6.0
s
(Note 1) The oscillation constant is shown on table 1.
LC86P6548
No.6690-13/22
3. Electrical Characteristics at Ta=-30
C to +70
C, VSS1=VSS2=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ.
max.
unit
IIH(1)
Ports 0,3 at open
drain output
Output disable
VIN=13.5V
(including off-leakage
current of the output Tr.)
4.5 to 6.0
5
Input high
current
IIH(2) Ports
1,3
Port 0 without
pull-up MOS Tr.
Output disable
Pull-up MOS Tr. OFF.
VIN=VDD
(including off-leakage
current of the output Tr.)
4.5 to 6.0
1
IIH(3) Ports
70,71,72,73
Port 8
Output disable
VIN=VDD
(including off-leakage
current of the output Tr.)
4.5 to 6.0
1
IIH(4)
RES VIN=VDD 4.5 to 6.0
1
IIH(5) Ports
74
,75 VIN=VDD
4.5 to 6.0
1
IIH(6)
S32 to S51 without
pull-down resistor
Output P-channel Tr. OFF.
VIN=VDD
4.5 to 6.0
1
IIL(1) Ports
1,3
Port 0 without
pull-up MOS Tr.
Output disable
Pull-up MOS Tr. OFF.
VIN=VSS
(including off-leakage
current of the output Tr.)
4.5 to 6.0
-1
IIL(2) Ports
70,71,72,73
Port 8
Output disable
VIN=VSS
(including off-leakage
current of the output Tr.)
4.5 to 6.0
-1
IIL(3)
RES VIN=VSS 4.5 to 6.0
-1
Input low
current
IIL(4) Ports
74 ,75 VIN=VSS
4.5 to 6.0
-1
A
VOH(1) IOH=-1.0mA
4.5 to 6.0 VDD-1
VOH(2)
Ports 0,1,3 of
CMOS output
IOH=-0.1mA
4.5 to 6.0 VDD-0.5
VOH(3) IOH=-20mA
4.5 to 6.0 VDD-1.8
VOH(4)
S0/T0 to S15/T15
IOH=-1.0mA
The current of any
unmeasurement pin is not
over 1mA.
4.5 to 6.0 VDD-1
VOH(5) IOH=-5mA
4.5 to 6.0 VDD-1.8
Output high
voltage
VOH(6)
S16 to S51
IOH=-1.0mA
The current of any
unmeasurement pins is not
over 1mA.
4.5 to 6.0 VDD-1
VOL(1) IOL=10mA
4.5 to 6.0
1.5
VOL(2)
Ports 0,1,3
IOL=1.6mA
4.5 to 6.0
0.4
VOL(3) Port 70
IOL=1mA
4.5 to 6.0
0.4
Output low
voltage
VOL(4) Ports 71,72,73
Ports 84,85,86,87
IOL=1.6mA
4.5 to 6.0
0.4
V
Pull-up MOS
Tr. resistor
Rpu Ports
0,1,3
VOH=0.9VDD
4.5 to 6.0
15 40
70
K
Continue.
LC86P6548
No.6690-14/22
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
IOFF(1) Output
P-channel
Tr. OFF
VOUT=VSS
4.5 to 6.0
-1
Output off-
leakage current
IOFF(2)
S0/T0 to S6/T6
S32 to S51
(without pull-down
resistor)
Output P-channel
Tr. OFF
VOUT=VDD-40V
4.5 to 6.0
-30
A
Resistance of
The low level
Hold Tr.
Rinpd
S16 to S51
Output P-channel
Tr. OFF
Using as input ports
4.5 to 6.0
200
High voltage
Pull-down
resistor
Rpd
S7/T7 to S15/T15
S16 to S31
Output P-channel
Tr. OFF
VOUT=3V
Vp=-30V
5.0 60 100
200
VP pull-down
resistor
Rvppd Vp
VSS=GND
Vp=-30V
5.0 60 100
200
K
Hysteresis
voltage
VHIS Port
1
Ports 70,71,72,73,75
RES
Output disable
4.5 to 6.0
0.1VDD
V
Pin capacitance
CP
All pins
f=1MHz
VIN=VSS for all
unmeasured terminals.
Ta=25
C
4.5 to 6.0
10
pF
4. Serial Input/Output Characteristics at Ta=-30
C to +70
C, VSS1=VSS2=0V
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ.
max.
unit
Cycle t
CKCY
(1) 2
Low Level
pulse width
t
CKL
(1) 1
In
put
c
l
oc
k
High Level
pulse width
t
CKH
(1)
SCK0,SCK1 Refer to figure 5
4.5 to 6.0
1
Cycle t
CKCY
(2) 2
Low Level
pulse width
t
CKL
(2)
1/2t
CKCY
Se
ri
al
cl
o
c
k
Ou
tp
u
t
cl
ock
High Level
pulse width
t
CKH
(2)
SCK0,SCK1 Use
pull-up
resistor (1k
) in
the open drain
output.
Refer to figure 5
4.5 to 6.0
1/2t
CKCY
t
CYC
Data set-up time
t
ICK
0.1
S
e
r
i
a
l
inpu
t
Data hold time
t
CKI
SI0,SI1
SB0,SB1
Data set-up to
SCK0,1
Data hold from
SCK0,1
Refer to figure 5
4.5 to 6.0
0.1
Output delay time
(External clock
using for serial
transfer clock)
t
CKO(1)
7/12
t
CYC
+0.2
S
e
r
i
a
l
outp
u
t
Output delay time
(Internal clock
using for serial
transfer clock)
t
CKO(2)
SO0,SO1
SB0,SB1
Use pull-up
resistor (1k
) in
the open drain
output.
Data hold from
SCK0,1
Refer to figure 5
4.5 to 6.0
1/3
t
CYC
+0.2
s
LC86P6548
No.6690-15/22
5. Pulse Input Conditions at Ta=-30
C to +70
C, VSS1=VSS2=0V
Ratings
Parameter Symbol
Pins
Conditions
VDD[V] min. typ. max.
unit
tPIH(1)
tPIL(1)
INT0, INT1
INT2/T0IN
Interrupt acceptable
Timer0-countable
4.5 to 6.0
1
tPIH(2)
tPIL(2)
INT3/T0IN
(The noise rejection clock
selected to 1/1.)
Interrupt acceptable
Timer0-countable
4.5 to 6.0
2
tPIH(3)
tPIL(3)
INT3/T0IN
(The noise rejection clock
selected to 1/16.)
Interrupt acceptable
Timer0-countable
4.5 to 6.0
32
tPIH(4)
tPIL(4)
INT3/T0IN
(The noise rejection clock
selected to 1/64.)
Interrupt acceptable
Timer0-countable
4.5 to 6.0 128
t
CYC
High/low level
pulse width
tPIL(5) RES
Reset acceptable
4.5 to 6.0 200
s
6. AD Converter Characteristics at Ta=-30
C to + 70
C, VSS1=VSS2=0V
Ratings
Parameter Symbol Pins
Conditions
VDD[V] min. typ. max.
unit
Resolution N
4.5
to
6.0
8
bit
Absolute precision
(Note 2)
ET
4.5
to
6.0 1.5
LSB
AD conversion time =
16
tCYC
(ADCR2=0)
(Note 3)
15.68
(tCYC=
0.98
s)
65.28
(tCYC=
4.08
s)
Conversion time
tCAD
AD conversion time =
32
tCYC
(ADCR2=1)
(Note 3)
4.5 to 6.0
31.36
(tCYC=
0.98
s)
130.56
(tCYC=
4.08
s)
s
Analog input
voltage range
VAIN 4.5
to
6.0
VSS
VDD
V
IAINH VAIN=VDD
4.5
to
6.0
1
Analog port
input current
IAINL
AN0 to AN7
VAIN=VSS 4.5
to
6.0
-1
A
(Note 2) Absolute precision excepts the quantizing error (1/2 LSB).
(Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital
conversion value to the register.
LC86P6548
No.6690-16/22
7. Current Dissipation Characteristics at Ta=-30
C to +70
C, VSS1=VSS2=0V
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ. max.
unit
IDDOP(1) FmCF=6MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/1 divided
4.5 to 6.0
14
33
IDDOP(2) FmCF=3MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
6
18
IDDOP(3) FmCF=0Hz
(The oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
RC oscillation
1/2 divided
4.5 to 6.0
4
13
Current dissipation
during basic
operation
(Note 4)
IDDOP(4)
FmCF=0Hz
(The oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
32.768kHz
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
3
10
mA
Continue.
LC86P6548
No.6690-17/22
Ratings
Parameter Symbol
Pins Conditions
VDD[V] min. typ. max.
unit
IDDHALT(1) HALT
mode
FmCF=6MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/1 divided
4.5 to 6.0
5
14
IDDHALT(2) HALT
mode
FmCF=3MHz
Ceramic resonator
oscillation
FsXtal=32.768kHz
crystal oscillation
System clock :
CF oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
2.2
7
mA
IDDHALT(3) HALT
mode
FmCF=0Hz
(The oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
RC oscillation
1/2 divided
4.5 to 6.0
400
1600
Current dissipation
in HALT mode
(Note 4)
IDDHALT(4)
HALT mode
FmCF=0Hz
(The oscillation
stops)
FsXtal=32.768kHz
crystal oscillation
System clock :
crystal oscillation
Internal RC
oscillation stops
1/2 divided
4.5 to 6.0
25
100
Current dissipation
in HOLD mode
(Note 4)
IDDHOLD(1)
HOLD mode
4.5 to 6.0
0.05
30
A
(Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored.
LC86P6548
No.6690-18/22
Table 1. Ceramic resonator oscillation recommended constant (main-clock)
Oscillation type
Maker
Oscillator
C1
C2
Murata
6MHz ceramic resonator
oscillation
Kyocera
Murata
3MHz ceramic resonator
oscillation
Kyocera
* Both C1 and C2 must be use K rank (10%) and SL characteristics.
Table 2. Crystal oscillation guaranteed constant (sub-clock)
Oscillation type
Maker
Oscillator
C3
C4
Rd
Rf
32.768kHz crystal oscillation
* Both C3 and C4 must be use J rank (5%) and CH characteristics.
(Not in need of high precision, use K rank (10%) and SL characteristics.)
(Notes) Please place the oscillation-related parts as close to the oscillation pins as possible with the shortest
possible pattern length since the circuit pattern affects the oscillation frequency.
If you use other oscillators herein, we provide no guarantee for the characteristics.
Figure 1 Main-clock circuit
Figure 2 Sub-clock circuit
Ceramic resonator oscillation
Crystal oscillation
C1
C2
CF
CF2
CF1
C3
Rd
C4
X'tal
XT2
XT1
Rf
LC86P6548
No.6690-19/22
Figure 3 Oscillation stable time
<Reset time and oscillation stable time>
<HOLD release signal and oscillation stable time>
Operation mode
XT1, XT2
CF1, CF2
Internal RC resonator
oscillation
RES
Instruction execution mode
Instruction execution mode
Instruction
execution mode
OCR6=1
Reset
Valid
Unfixed
tssXtal
tmsCF
Reset time
VDD
VDD limit
0V
Power supply
Operation mode
XT1, XT2
CF1, CF2
HOLD release signal
HOLD
tssXtal
tmsCF
Internal RC resonator
oscillation
LC86P6548
No.6690-20/22
Figure 4 Reset circuit
Figure 5 Serial input / output test condition
Figure 6 Pulse input timing condition
SO0, SO1
SB0, SB1
SI0
SI1
SCK0
SCK1
<Timing>
50pF
1K
VDD
tCKO
tCKI
tICK
tCKH
tCKL
tCKCY
<AC timing point>
0.5VDD
tPIH
tPIL
(Note) Fix the value of CRES, RRES that is
sure to reset until 200
s, after Power
supply has been over inferior limit of
supply voltage.
C
RES
VDD
R
RES
RES
LC86P6548
No.6690-21/22
Notice For Use
The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for
Sanyo to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening
procedure shown in the following figure should always be followed.
It is not possible to perform a writing test on the blank PROM. 100% yield, therefore, cannot be guaranteed.
Keeping the dry packing
The environment must be held at a temperature of 30
C or less and a humidity level of 70% or less.
After opening the packing
The preparation procedures shown in the following figure should always be followed prior to mounting the packages on
the substrate. After opening the packing, a controlled environment must be maintained until soldering. The
environment must be held at a temperature of 30
C or less and a humidity level of 70% or less. Please solder within 96
hours.
Unused devices should be kept in the dry atmosphere such as inside of desiccator or dry these up before assembling on the
board.
a. Shipping with a blank PROM
b. Shipping with a programmed PROM
(Programming the data by yourself)
(Programming the data by Sanyo)
QFP
QFP
Writing data for
program/Verifying
Recommended process of screening
Heat-soak
1505
C,24 Hr
+1
-0
Reading ascertain of program
VDD=50.5V
Mounting
Mounting
LC86P6548
No.6690-22/22
memo:
PS
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